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xburst: add support for 3.8
[openwrt/openwrt.git] / target / linux / xburst / patches-3.8 / 0002-Add-jz4740-udc-driver.patch
1 From 537082e01849ca85227c5b462b8ac9aceb11b77a Mon Sep 17 00:00:00 2001
2 From: Lars-Peter Clausen <lars@metafoo.de>
3 Date: Sat, 24 Apr 2010 12:18:46 +0200
4 Subject: [PATCH 02/21] Add jz4740 udc driver
5
6 History:
7 - driver by Ingenic
8 - patch by Lars-Peter Clausen.
9 - updated to 3.1 by Maarten ter Huurne
10 ---
11 drivers/usb/gadget/Kconfig | 8 +
12 drivers/usb/gadget/Makefile | 1 +
13 drivers/usb/gadget/gadget_chips.h | 3 +
14 drivers/usb/gadget/jz4740_udc.c | 2199 +++++++++++++++++++++++++++++++++++++
15 drivers/usb/gadget/jz4740_udc.h | 101 ++
16 5 files changed, 2312 insertions(+), 0 deletions(-)
17 create mode 100644 drivers/usb/gadget/jz4740_udc.c
18 create mode 100644 drivers/usb/gadget/jz4740_udc.h
19
20 --- a/drivers/usb/gadget/Kconfig
21 +++ b/drivers/usb/gadget/Kconfig
22 @@ -191,6 +191,14 @@ config USB_FUSB300
23 help
24 Faraday usb device controller FUSB300 driver
25
26 +config USB_JZ4740
27 + tristate "JZ4740 UDC"
28 + depends on MACH_JZ4740
29 + select USB_GADGET_DUALSPEED
30 + help
31 + Select this to support the Ingenic JZ4740 processor
32 + high speed USB device controller.
33 +
34 config USB_OMAP
35 tristate "OMAP USB Device Controller"
36 depends on ARCH_OMAP1
37 --- a/drivers/usb/gadget/Makefile
38 +++ b/drivers/usb/gadget/Makefile
39 @@ -34,6 +34,7 @@ obj-$(CONFIG_USB_MV_UDC) += mv_udc.o
40 mv_udc-y := mv_udc_core.o
41 obj-$(CONFIG_USB_FUSB300) += fusb300_udc.o
42 obj-$(CONFIG_USB_MV_U3D) += mv_u3d_core.o
43 +obj-$(CONFIG_USB_JZ4740) += jz4740_udc.o
44
45 #
46 # USB gadget drivers
47 --- a/drivers/usb/gadget/gadget_chips.h
48 +++ b/drivers/usb/gadget/gadget_chips.h
49 @@ -30,6 +30,7 @@
50 #define gadget_is_at91(g) (!strcmp("at91_udc", (g)->name))
51 #define gadget_is_goku(g) (!strcmp("goku_udc", (g)->name))
52 #define gadget_is_musbhdrc(g) (!strcmp("musb-hdrc", (g)->name))
53 +#define gadget_is_jz4740(g) (!strcmp("ingenic_hsusb", (g)->name))
54 #define gadget_is_net2280(g) (!strcmp("net2280", (g)->name))
55 #define gadget_is_pxa(g) (!strcmp("pxa25x_udc", (g)->name))
56 #define gadget_is_pxa27x(g) (!strcmp("pxa27x_udc", (g)->name))
57 --- /dev/null
58 +++ b/drivers/usb/gadget/jz4740_udc.c
59 @@ -0,0 +1,2199 @@
60 +/*
61 + * linux/drivers/usb/gadget/jz4740_udc.c
62 + *
63 + * Ingenic JZ4740 on-chip high speed USB device controller
64 + *
65 + * Copyright (C) 2006 - 2008 Ingenic Semiconductor Inc.
66 + * Author: <jlwei@ingenic.cn>
67 + *
68 + * This program is free software; you can redistribute it and/or modify
69 + * it under the terms of the GNU General Public License as published by
70 + * the Free Software Foundation; either version 2 of the License, or
71 + * (at your option) any later version.
72 + */
73 +
74 +/*
75 + * This device has ep0, two bulk-in/interrupt-in endpoints, and one bulk-out endpoint.
76 + *
77 + * - Endpoint numbering is fixed: ep0, ep1in-int, ep2in-bulk, ep1out-bulk.
78 + * - DMA works with bulk-in (channel 1) and bulk-out (channel 2) endpoints.
79 + */
80 +
81 +#include <linux/kernel.h>
82 +#include <linux/module.h>
83 +#include <linux/platform_device.h>
84 +#include <linux/delay.h>
85 +#include <linux/ioport.h>
86 +#include <linux/slab.h>
87 +#include <linux/errno.h>
88 +#include <linux/init.h>
89 +#include <linux/list.h>
90 +#include <linux/interrupt.h>
91 +#include <linux/proc_fs.h>
92 +#include <linux/usb.h>
93 +#include <linux/usb/gadget.h>
94 +#include <linux/clk.h>
95 +
96 +#include <asm/byteorder.h>
97 +#include <asm/io.h>
98 +#include <asm/irq.h>
99 +#include <asm/system.h>
100 +#include <asm/mach-jz4740/clock.h>
101 +
102 +#include "jz4740_udc.h"
103 +
104 +#define JZ_REG_UDC_FADDR 0x00 /* Function Address 8-bit */
105 +#define JZ_REG_UDC_POWER 0x01 /* Power Management 8-bit */
106 +#define JZ_REG_UDC_INTRIN 0x02 /* Interrupt IN 16-bit */
107 +#define JZ_REG_UDC_INTROUT 0x04 /* Interrupt OUT 16-bit */
108 +#define JZ_REG_UDC_INTRINE 0x06 /* Intr IN enable 16-bit */
109 +#define JZ_REG_UDC_INTROUTE 0x08 /* Intr OUT enable 16-bit */
110 +#define JZ_REG_UDC_INTRUSB 0x0a /* Interrupt USB 8-bit */
111 +#define JZ_REG_UDC_INTRUSBE 0x0b /* Interrupt USB Enable 8-bit */
112 +#define JZ_REG_UDC_FRAME 0x0c /* Frame number 16-bit */
113 +#define JZ_REG_UDC_INDEX 0x0e /* Index register 8-bit */
114 +#define JZ_REG_UDC_TESTMODE 0x0f /* USB test mode 8-bit */
115 +
116 +#define JZ_REG_UDC_CSR0 0x12 /* EP0 CSR 8-bit */
117 +#define JZ_REG_UDC_INMAXP 0x10 /* EP1-2 IN Max Pkt Size 16-bit */
118 +#define JZ_REG_UDC_INCSR 0x12 /* EP1-2 IN CSR LSB 8/16bit */
119 +#define JZ_REG_UDC_INCSRH 0x13 /* EP1-2 IN CSR MSB 8-bit */
120 +
121 +#define JZ_REG_UDC_OUTMAXP 0x14 /* EP1 OUT Max Pkt Size 16-bit */
122 +#define JZ_REG_UDC_OUTCSR 0x16 /* EP1 OUT CSR LSB 8/16bit */
123 +#define JZ_REG_UDC_OUTCSRH 0x17 /* EP1 OUT CSR MSB 8-bit */
124 +#define JZ_REG_UDC_OUTCOUNT 0x18 /* bytes in EP0/1 OUT FIFO 16-bit */
125 +
126 +#define JZ_REG_UDC_EP_FIFO(x) (4 * (x) + 0x20)
127 +
128 +#define JZ_REG_UDC_EPINFO 0x78 /* Endpoint information */
129 +#define JZ_REG_UDC_RAMINFO 0x79 /* RAM information */
130 +
131 +#define JZ_REG_UDC_INTR 0x200 /* DMA pending interrupts */
132 +#define JZ_REG_UDC_CNTL1 0x204 /* DMA channel 1 control */
133 +#define JZ_REG_UDC_ADDR1 0x208 /* DMA channel 1 AHB memory addr */
134 +#define JZ_REG_UDC_COUNT1 0x20c /* DMA channel 1 byte count */
135 +#define JZ_REG_UDC_CNTL2 0x214 /* DMA channel 2 control */
136 +#define JZ_REG_UDC_ADDR2 0x218 /* DMA channel 2 AHB memory addr */
137 +#define JZ_REG_UDC_COUNT2 0x21c /* DMA channel 2 byte count */
138 +
139 +/* Power register bit masks */
140 +#define USB_POWER_SUSPENDM 0x01
141 +#define USB_POWER_RESUME 0x04
142 +#define USB_POWER_HSMODE 0x10
143 +#define USB_POWER_HSENAB 0x20
144 +#define USB_POWER_SOFTCONN 0x40
145 +
146 +/* Interrupt register bit masks */
147 +#define USB_INTR_SUSPEND 0x01
148 +#define USB_INTR_RESUME 0x02
149 +#define USB_INTR_RESET 0x04
150 +
151 +#define USB_INTR_EP0 0x0001
152 +#define USB_INTR_INEP1 0x0002
153 +#define USB_INTR_INEP2 0x0004
154 +#define USB_INTR_OUTEP1 0x0002
155 +
156 +/* CSR0 bit masks */
157 +#define USB_CSR0_OUTPKTRDY 0x01
158 +#define USB_CSR0_INPKTRDY 0x02
159 +#define USB_CSR0_SENTSTALL 0x04
160 +#define USB_CSR0_DATAEND 0x08
161 +#define USB_CSR0_SETUPEND 0x10
162 +#define USB_CSR0_SENDSTALL 0x20
163 +#define USB_CSR0_SVDOUTPKTRDY 0x40
164 +#define USB_CSR0_SVDSETUPEND 0x80
165 +
166 +/* Endpoint CSR register bits */
167 +#define USB_INCSRH_AUTOSET 0x80
168 +#define USB_INCSRH_ISO 0x40
169 +#define USB_INCSRH_MODE 0x20
170 +#define USB_INCSRH_DMAREQENAB 0x10
171 +#define USB_INCSRH_DMAREQMODE 0x04
172 +#define USB_INCSR_CDT 0x40
173 +#define USB_INCSR_SENTSTALL 0x20
174 +#define USB_INCSR_SENDSTALL 0x10
175 +#define USB_INCSR_FF 0x08
176 +#define USB_INCSR_UNDERRUN 0x04
177 +#define USB_INCSR_FFNOTEMPT 0x02
178 +#define USB_INCSR_INPKTRDY 0x01
179 +
180 +#define USB_OUTCSRH_AUTOCLR 0x80
181 +#define USB_OUTCSRH_ISO 0x40
182 +#define USB_OUTCSRH_DMAREQENAB 0x20
183 +#define USB_OUTCSRH_DNYT 0x10
184 +#define USB_OUTCSRH_DMAREQMODE 0x08
185 +#define USB_OUTCSR_CDT 0x80
186 +#define USB_OUTCSR_SENTSTALL 0x40
187 +#define USB_OUTCSR_SENDSTALL 0x20
188 +#define USB_OUTCSR_FF 0x10
189 +#define USB_OUTCSR_DATAERR 0x08
190 +#define USB_OUTCSR_OVERRUN 0x04
191 +#define USB_OUTCSR_FFFULL 0x02
192 +#define USB_OUTCSR_OUTPKTRDY 0x01
193 +
194 +/* DMA control bits */
195 +#define USB_CNTL_ENA 0x01
196 +#define USB_CNTL_DIR_IN 0x02
197 +#define USB_CNTL_MODE_1 0x04
198 +#define USB_CNTL_INTR_EN 0x08
199 +#define USB_CNTL_EP(n) ((n) << 4)
200 +#define USB_CNTL_BURST_0 (0 << 9)
201 +#define USB_CNTL_BURST_4 (1 << 9)
202 +#define USB_CNTL_BURST_8 (2 << 9)
203 +#define USB_CNTL_BURST_16 (3 << 9)
204 +
205 +
206 +#ifndef DEBUG
207 +# define DEBUG(fmt,args...) do {} while(0)
208 +#endif
209 +#ifndef DEBUG_EP0
210 +# define NO_STATES
211 +# define DEBUG_EP0(fmt,args...) do {} while(0)
212 +#endif
213 +#ifndef DEBUG_SETUP
214 +# define DEBUG_SETUP(fmt,args...) do {} while(0)
215 +#endif
216 +
217 +static struct jz4740_udc jz4740_udc_controller;
218 +
219 +/*
220 + * Local declarations.
221 + */
222 +static int jz4740_udc_start(struct usb_gadget_driver *driver,
223 + int (*bind)(struct usb_gadget *));
224 +static int jz4740_udc_stop(struct usb_gadget_driver *driver);
225 +static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep);
226 +static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr);
227 +
228 +static void done(struct jz4740_ep *ep, struct jz4740_request *req,
229 + int status);
230 +static void pio_irq_enable(struct jz4740_ep *ep);
231 +static void pio_irq_disable(struct jz4740_ep *ep);
232 +static void stop_activity(struct jz4740_udc *dev,
233 + struct usb_gadget_driver *driver);
234 +static void nuke(struct jz4740_ep *ep, int status);
235 +static void flush(struct jz4740_ep *ep);
236 +static void udc_set_address(struct jz4740_udc *dev, unsigned char address);
237 +
238 +/*-------------------------------------------------------------------------*/
239 +
240 +/* inline functions of register read/write/set/clear */
241 +
242 +static inline uint8_t usb_readb(struct jz4740_udc *udc, size_t reg)
243 +{
244 + return readb(udc->base + reg);
245 +}
246 +
247 +static inline uint16_t usb_readw(struct jz4740_udc *udc, size_t reg)
248 +{
249 + return readw(udc->base + reg);
250 +}
251 +
252 +static inline uint32_t usb_readl(struct jz4740_udc *udc, size_t reg)
253 +{
254 + return readl(udc->base + reg);
255 +}
256 +
257 +static inline void usb_writeb(struct jz4740_udc *udc, size_t reg, uint8_t val)
258 +{
259 + writeb(val, udc->base + reg);
260 +}
261 +
262 +static inline void usb_writew(struct jz4740_udc *udc, size_t reg, uint16_t val)
263 +{
264 + writew(val, udc->base + reg);
265 +}
266 +
267 +static inline void usb_writel(struct jz4740_udc *udc, size_t reg, uint32_t val)
268 +{
269 + writel(val, udc->base + reg);
270 +}
271 +
272 +static inline void usb_setb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
273 +{
274 + usb_writeb(udc, reg, usb_readb(udc, reg) | mask);
275 +}
276 +
277 +static inline void usb_setw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
278 +{
279 + usb_writew(udc, reg, usb_readw(udc, reg) | mask);
280 +}
281 +
282 +static inline void usb_clearb(struct jz4740_udc *udc, size_t reg, uint8_t mask)
283 +{
284 + usb_writeb(udc, reg, usb_readb(udc, reg) & ~mask);
285 +}
286 +
287 +static inline void usb_clearw(struct jz4740_udc *udc, size_t reg, uint16_t mask)
288 +{
289 + usb_writew(udc, reg, usb_readw(udc, reg) & ~mask);
290 +}
291 +
292 +/*-------------------------------------------------------------------------*/
293 +
294 +static inline void jz_udc_set_index(struct jz4740_udc *udc, uint8_t index)
295 +{
296 + usb_writeb(udc, JZ_REG_UDC_INDEX, index);
297 +}
298 +
299 +static inline void jz_udc_select_ep(struct jz4740_ep *ep)
300 +{
301 + jz_udc_set_index(ep->dev, ep_index(ep));
302 +}
303 +
304 +static inline int write_packet(struct jz4740_ep *ep,
305 + struct jz4740_request *req, unsigned int count)
306 +{
307 + uint8_t *buf;
308 + unsigned int length;
309 + void __iomem *fifo = ep->dev->base + ep->fifo;
310 +
311 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
312 +
313 + buf = req->req.buf + req->req.actual;
314 +
315 + length = req->req.length - req->req.actual;
316 + if (length > count)
317 + length = count;
318 + req->req.actual += length;
319 +
320 + DEBUG("Write %d (count %d), fifo %x\n", length, count, ep->fifo);
321 +
322 + writesl(fifo, buf, length >> 2);
323 + writesb(fifo, &buf[length - (length & 3)], length & 3);
324 +
325 + return length;
326 +}
327 +
328 +static int read_packet(struct jz4740_ep *ep,
329 + struct jz4740_request *req, unsigned int count)
330 +{
331 + uint8_t *buf;
332 + unsigned int length;
333 + void __iomem *fifo = ep->dev->base + ep->fifo;
334 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
335 +
336 + buf = req->req.buf + req->req.actual;
337 +
338 + length = req->req.length - req->req.actual;
339 + if (length > count)
340 + length = count;
341 + req->req.actual += length;
342 +
343 + DEBUG("Read %d, fifo %x\n", length, ep->fifo);
344 +
345 + readsl(fifo, buf, length >> 2);
346 + readsb(fifo, &buf[length - (length & 3)], length & 3);
347 +
348 + return length;
349 +}
350 +
351 +/*-------------------------------------------------------------------------*/
352 +
353 +/*
354 + * udc_disable - disable USB device controller
355 + */
356 +static void udc_disable(struct jz4740_udc *dev)
357 +{
358 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
359 +
360 + udc_set_address(dev, 0);
361 +
362 + /* Disable interrupts */
363 + usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
364 + usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
365 + usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);
366 +
367 + /* Disable DMA */
368 + usb_writel(dev, JZ_REG_UDC_CNTL1, 0);
369 + usb_writel(dev, JZ_REG_UDC_CNTL2, 0);
370 +
371 + /* Disconnect from usb */
372 + usb_clearb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
373 +
374 + /* Disable the USB PHY */
375 + clk_disable(dev->clk);
376 +
377 + dev->ep0state = WAIT_FOR_SETUP;
378 + dev->gadget.speed = USB_SPEED_UNKNOWN;
379 +
380 + return;
381 +}
382 +
383 +/*
384 + * udc_reinit - initialize software state
385 + */
386 +static void udc_reinit(struct jz4740_udc *dev)
387 +{
388 + int i;
389 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
390 +
391 + /* device/ep0 records init */
392 + INIT_LIST_HEAD(&dev->gadget.ep_list);
393 + INIT_LIST_HEAD(&dev->gadget.ep0->ep_list);
394 + dev->ep0state = WAIT_FOR_SETUP;
395 +
396 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
397 + struct jz4740_ep *ep = &dev->ep[i];
398 +
399 + if (i != 0)
400 + list_add_tail(&ep->ep.ep_list, &dev->gadget.ep_list);
401 +
402 + INIT_LIST_HEAD(&ep->queue);
403 + ep->desc = 0;
404 + ep->stopped = 0;
405 + }
406 +}
407 +
408 +/* until it's enabled, this UDC should be completely invisible
409 + * to any USB host.
410 + */
411 +static void udc_enable(struct jz4740_udc *dev)
412 +{
413 + int i;
414 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
415 +
416 + /* UDC state is incorrect - Added by River */
417 + if (dev->state != UDC_STATE_ENABLE) {
418 + return;
419 + }
420 +
421 + dev->gadget.speed = USB_SPEED_UNKNOWN;
422 +
423 + /* Flush FIFO for each */
424 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
425 + struct jz4740_ep *ep = &dev->ep[i];
426 +
427 + jz_udc_select_ep(ep);
428 + flush(ep);
429 + }
430 +
431 + /* Set this bit to allow the UDC entering low-power mode when
432 + * there are no actions on the USB bus.
433 + * UDC still works during this bit was set.
434 + */
435 + jz4740_clock_udc_enable_auto_suspend();
436 +
437 + /* Enable the USB PHY */
438 + clk_enable(dev->clk);
439 +
440 + /* Disable interrupts */
441 +/* usb_writew(dev, JZ_REG_UDC_INTRINE, 0);
442 + usb_writew(dev, JZ_REG_UDC_INTROUTE, 0);
443 + usb_writeb(dev, JZ_REG_UDC_INTRUSBE, 0);*/
444 +
445 + /* Enable interrupts */
446 + usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_EP0);
447 + usb_setb(dev, JZ_REG_UDC_INTRUSBE, USB_INTR_RESET);
448 + /* Don't enable rest of the interrupts */
449 + /* usb_setw(dev, JZ_REG_UDC_INTRINE, USB_INTR_INEP1 | USB_INTR_INEP2);
450 + usb_setw(dev, JZ_REG_UDC_INTROUTE, USB_INTR_OUTEP1); */
451 +
452 + /* Enable SUSPEND */
453 + /* usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SUSPENDM); */
454 +
455 + /* Enable HS Mode */
456 + usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_HSENAB);
457 +
458 + /* Let host detect UDC:
459 + * Software must write a 1 to the PMR:USB_POWER_SOFTCONN bit to turn this
460 + * transistor on and pull the USBDP pin HIGH.
461 + */
462 + usb_setb(dev, JZ_REG_UDC_POWER, USB_POWER_SOFTCONN);
463 +
464 + return;
465 +}
466 +
467 +/*-------------------------------------------------------------------------*/
468 +
469 +/* keeping it simple:
470 + * - one bus driver, initted first;
471 + * - one function driver, initted second
472 + */
473 +
474 +/*
475 + * Register entry point for the peripheral controller driver.
476 + */
477 +
478 +static int jz4740_udc_start(struct usb_gadget_driver *driver,
479 + int (*bind)(struct usb_gadget *))
480 +{
481 + struct jz4740_udc *dev = &jz4740_udc_controller;
482 + int retval;
483 +
484 + if (!driver || !bind)
485 + return -EINVAL;
486 +
487 + if (!dev)
488 + return -ENODEV;
489 +
490 + if (dev->driver)
491 + return -EBUSY;
492 +
493 + /* hook up the driver */
494 + dev->driver = driver;
495 + dev->gadget.dev.driver = &driver->driver;
496 +
497 + retval = bind(&dev->gadget);
498 + if (retval) {
499 + DEBUG("%s: bind to driver %s --> error %d\n", dev->gadget.name,
500 + driver->driver.name, retval);
501 + dev->driver = 0;
502 + return retval;
503 + }
504 +
505 + /* then enable host detection and ep0; and we're ready
506 + * for set_configuration as well as eventual disconnect.
507 + */
508 + udc_enable(dev);
509 +
510 + DEBUG("%s: registered gadget driver '%s'\n", dev->gadget.name,
511 + driver->driver.name);
512 +
513 + return 0;
514 +}
515 +
516 +static void stop_activity(struct jz4740_udc *dev,
517 + struct usb_gadget_driver *driver)
518 +{
519 + int i;
520 +
521 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
522 +
523 + /* don't disconnect drivers more than once */
524 + if (dev->gadget.speed == USB_SPEED_UNKNOWN)
525 + driver = 0;
526 + dev->gadget.speed = USB_SPEED_UNKNOWN;
527 +
528 + /* prevent new request submissions, kill any outstanding requests */
529 + for (i = 0; i < UDC_MAX_ENDPOINTS; i++) {
530 + struct jz4740_ep *ep = &dev->ep[i];
531 +
532 + ep->stopped = 1;
533 +
534 + jz_udc_select_ep(ep);
535 + nuke(ep, -ESHUTDOWN);
536 + }
537 +
538 + /* report disconnect; the driver is already quiesced */
539 + if (driver) {
540 + spin_unlock(&dev->lock);
541 + driver->disconnect(&dev->gadget);
542 + spin_lock(&dev->lock);
543 + }
544 +
545 + /* re-init driver-visible data structures */
546 + udc_reinit(dev);
547 +}
548 +
549 +
550 +/*
551 + * Unregister entry point for the peripheral controller driver.
552 + */
553 +static int jz4740_udc_stop(struct usb_gadget_driver *driver)
554 +{
555 + struct jz4740_udc *dev = &jz4740_udc_controller;
556 + unsigned long flags;
557 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
558 +
559 + if (!dev)
560 + return -ENODEV;
561 + if (!driver || driver != dev->driver)
562 + return -EINVAL;
563 + if (!driver->unbind)
564 + return -EBUSY;
565 +
566 + spin_lock_irqsave(&dev->lock, flags);
567 + dev->driver = 0;
568 + stop_activity(dev, driver);
569 + spin_unlock_irqrestore(&dev->lock, flags);
570 +
571 + driver->unbind(&dev->gadget);
572 +
573 + udc_disable(dev);
574 +
575 + DEBUG("unregistered driver '%s'\n", driver->driver.name);
576 +
577 + return 0;
578 +}
579 +
580 +/*-------------------------------------------------------------------------*/
581 +
582 +/** Write request to FIFO (max write == maxp size)
583 + * Return: 0 = still running, 1 = completed, negative = errno
584 + * NOTE: INDEX register must be set for EP
585 + */
586 +static int write_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
587 +{
588 + struct jz4740_udc *dev = ep->dev;
589 + uint32_t max, csr;
590 +
591 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
592 + max = le16_to_cpu(ep->desc->wMaxPacketSize);
593 +
594 + csr = usb_readb(dev, ep->csr);
595 +
596 + if (!(csr & USB_INCSR_FFNOTEMPT)) {
597 + unsigned count;
598 + int is_last, is_short;
599 +
600 + count = write_packet(ep, req, max);
601 + usb_setb(dev, ep->csr, USB_INCSR_INPKTRDY);
602 +
603 + /* last packet is usually short (or a zlp) */
604 + if (unlikely(count != max))
605 + is_last = is_short = 1;
606 + else {
607 + if (likely(req->req.length != req->req.actual)
608 + || req->req.zero)
609 + is_last = 0;
610 + else
611 + is_last = 1;
612 + /* interrupt/iso maxpacket may not fill the fifo */
613 + is_short = unlikely(max < ep_maxpacket(ep));
614 + }
615 +
616 + DEBUG("%s: wrote %s %d bytes%s%s %d left %p\n", __FUNCTION__,
617 + ep->ep.name, count,
618 + is_last ? "/L" : "", is_short ? "/S" : "",
619 + req->req.length - req->req.actual, req);
620 +
621 + /* requests complete when all IN data is in the FIFO */
622 + if (is_last) {
623 + done(ep, req, 0);
624 + if (list_empty(&ep->queue)) {
625 + pio_irq_disable(ep);
626 + }
627 + return 1;
628 + }
629 + } else {
630 + DEBUG("Hmm.. %d ep FIFO is not empty!\n", ep_index(ep));
631 + }
632 +
633 + return 0;
634 +}
635 +
636 +/** Read to request from FIFO (max read == bytes in fifo)
637 + * Return: 0 = still running, 1 = completed, negative = errno
638 + * NOTE: INDEX register must be set for EP
639 + */
640 +static int read_fifo(struct jz4740_ep *ep, struct jz4740_request *req)
641 +{
642 + struct jz4740_udc *dev = ep->dev;
643 + uint32_t csr;
644 + unsigned count, is_short;
645 +
646 + /* make sure there's a packet in the FIFO. */
647 + csr = usb_readb(dev, ep->csr);
648 + if (!(csr & USB_OUTCSR_OUTPKTRDY)) {
649 + DEBUG("%s: Packet NOT ready!\n", __FUNCTION__);
650 + return -EINVAL;
651 + }
652 +
653 + /* read all bytes from this packet */
654 + count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
655 +
656 + is_short = (count < ep->ep.maxpacket);
657 +
658 + count = read_packet(ep, req, count);
659 +
660 + DEBUG("read %s %02x, %d bytes%s req %p %d/%d\n",
661 + ep->ep.name, csr, count,
662 + is_short ? "/S" : "", req, req->req.actual, req->req.length);
663 +
664 + /* Clear OutPktRdy */
665 + usb_clearb(dev, ep->csr, USB_OUTCSR_OUTPKTRDY);
666 +
667 + /* completion */
668 + if (is_short || req->req.actual == req->req.length) {
669 + done(ep, req, 0);
670 +
671 + if (list_empty(&ep->queue))
672 + pio_irq_disable(ep);
673 + return 1;
674 + }
675 +
676 + /* finished that packet. the next one may be waiting... */
677 + return 0;
678 +}
679 +
680 +/*
681 + * done - retire a request; caller blocked irqs
682 + * INDEX register is preserved to keep same
683 + */
684 +static void done(struct jz4740_ep *ep, struct jz4740_request *req, int status)
685 +{
686 + unsigned int stopped = ep->stopped;
687 + uint32_t index;
688 +
689 + DEBUG("%s, %p\n", __FUNCTION__, ep);
690 + list_del_init(&req->queue);
691 +
692 + if (likely(req->req.status == -EINPROGRESS))
693 + req->req.status = status;
694 + else
695 + status = req->req.status;
696 +
697 + if (status && status != -ESHUTDOWN)
698 + DEBUG("complete %s req %p stat %d len %u/%u\n",
699 + ep->ep.name, &req->req, status,
700 + req->req.actual, req->req.length);
701 +
702 + /* don't modify queue heads during completion callback */
703 + ep->stopped = 1;
704 + /* Read current index (completion may modify it) */
705 + index = usb_readb(ep->dev, JZ_REG_UDC_INDEX);
706 + spin_unlock_irqrestore(&ep->dev->lock, ep->dev->lock_flags);
707 +
708 + req->req.complete(&ep->ep, &req->req);
709 +
710 + spin_lock_irqsave(&ep->dev->lock, ep->dev->lock_flags);
711 + /* Restore index */
712 + jz_udc_set_index(ep->dev, index);
713 + ep->stopped = stopped;
714 +}
715 +
716 +static inline unsigned int jz4740_udc_ep_irq_enable_reg(struct jz4740_ep *ep)
717 +{
718 + if (ep_is_in(ep))
719 + return JZ_REG_UDC_INTRINE;
720 + else
721 + return JZ_REG_UDC_INTROUTE;
722 +}
723 +
724 +/** Enable EP interrupt */
725 +static void pio_irq_enable(struct jz4740_ep *ep)
726 +{
727 + DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
728 +
729 + usb_setw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep)));
730 +}
731 +
732 +/** Disable EP interrupt */
733 +static void pio_irq_disable(struct jz4740_ep *ep)
734 +{
735 + DEBUG("%s: EP%d %s\n", __FUNCTION__, ep_index(ep), ep_is_in(ep) ? "IN": "OUT");
736 +
737 + usb_clearw(ep->dev, jz4740_udc_ep_irq_enable_reg(ep), BIT(ep_index(ep)));
738 +}
739 +
740 +/*
741 + * nuke - dequeue ALL requests
742 + */
743 +static void nuke(struct jz4740_ep *ep, int status)
744 +{
745 + struct jz4740_request *req;
746 +
747 + DEBUG("%s, %p\n", __FUNCTION__, ep);
748 +
749 + /* Flush FIFO */
750 + flush(ep);
751 +
752 + /* called with irqs blocked */
753 + while (!list_empty(&ep->queue)) {
754 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
755 + done(ep, req, status);
756 + }
757 +
758 + /* Disable IRQ if EP is enabled (has descriptor) */
759 + if (ep->desc)
760 + pio_irq_disable(ep);
761 +}
762 +
763 +/** Flush EP FIFO
764 + * NOTE: INDEX register must be set before this call
765 + */
766 +static void flush(struct jz4740_ep *ep)
767 +{
768 + DEBUG("%s: %s\n", __FUNCTION__, ep->ep.name);
769 +
770 + switch (ep->type) {
771 + case ep_bulk_in:
772 + case ep_interrupt:
773 + usb_setb(ep->dev, ep->csr, USB_INCSR_FF);
774 + break;
775 + case ep_bulk_out:
776 + usb_setb(ep->dev, ep->csr, USB_OUTCSR_FF);
777 + break;
778 + case ep_control:
779 + break;
780 + }
781 +}
782 +
783 +/**
784 + * jz4740_in_epn - handle IN interrupt
785 + */
786 +static void jz4740_in_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
787 +{
788 + uint32_t csr;
789 + struct jz4740_ep *ep = &dev->ep[ep_idx + 1];
790 + struct jz4740_request *req;
791 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
792 +
793 + jz_udc_select_ep(ep);
794 +
795 + csr = usb_readb(dev, ep->csr);
796 + DEBUG("%s: %d, csr %x\n", __FUNCTION__, ep_idx, csr);
797 +
798 + if (csr & USB_INCSR_SENTSTALL) {
799 + DEBUG("USB_INCSR_SENTSTALL\n");
800 + usb_clearb(dev, ep->csr, USB_INCSR_SENTSTALL);
801 + return;
802 + }
803 +
804 + if (!ep->desc) {
805 + DEBUG("%s: NO EP DESC\n", __FUNCTION__);
806 + return;
807 + }
808 +
809 + if (!list_empty(&ep->queue)) {
810 + req = list_first_entry(&ep->queue, struct jz4740_request, queue);
811 + write_fifo(ep, req);
812 + }
813 +}
814 +
815 +/*
816 + * Bulk OUT (recv)
817 + */
818 +static void jz4740_out_epn(struct jz4740_udc *dev, uint32_t ep_idx, uint32_t intr)
819 +{
820 + struct jz4740_ep *ep = &dev->ep[ep_idx];
821 + struct jz4740_request *req;
822 +
823 + DEBUG("%s: %d\n", __FUNCTION__, ep_idx);
824 +
825 + jz_udc_select_ep(ep);
826 + if (ep->desc) {
827 + uint32_t csr;
828 +
829 + while ((csr = usb_readb(dev, ep->csr)) &
830 + (USB_OUTCSR_OUTPKTRDY | USB_OUTCSR_SENTSTALL)) {
831 + DEBUG("%s: %x\n", __FUNCTION__, csr);
832 +
833 + if (csr & USB_OUTCSR_SENTSTALL) {
834 + DEBUG("%s: stall sent, flush fifo\n",
835 + __FUNCTION__);
836 + /* usb_set(USB_OUT_CSR1_FIFO_FLUSH, ep->csr1); */
837 + flush(ep);
838 + } else if (csr & USB_OUTCSR_OUTPKTRDY) {
839 + if (list_empty(&ep->queue))
840 + req = 0;
841 + else
842 + req =
843 + list_entry(ep->queue.next,
844 + struct jz4740_request,
845 + queue);
846 +
847 + if (!req) {
848 + DEBUG("%s: NULL REQ %d\n",
849 + __FUNCTION__, ep_idx);
850 + break;
851 + } else {
852 + read_fifo(ep, req);
853 + }
854 + }
855 + }
856 + } else {
857 + /* Throw packet away.. */
858 + DEBUG("%s: ep %p ep_indx %d No descriptor?!?\n", __FUNCTION__, ep, ep_idx);
859 + flush(ep);
860 + }
861 +}
862 +
863 +/** Halt specific EP
864 + * Return 0 if success
865 + * NOTE: Sets INDEX register to EP !
866 + */
867 +static int jz4740_set_halt(struct usb_ep *_ep, int value)
868 +{
869 + struct jz4740_udc *dev;
870 + struct jz4740_ep *ep;
871 + unsigned long flags;
872 +
873 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
874 +
875 + ep = container_of(_ep, struct jz4740_ep, ep);
876 + if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
877 + DEBUG("%s, bad ep\n", __FUNCTION__);
878 + return -EINVAL;
879 + }
880 +
881 + dev = ep->dev;
882 +
883 + spin_lock_irqsave(&dev->lock, flags);
884 +
885 + jz_udc_select_ep(ep);
886 +
887 + DEBUG("%s, ep %d, val %d\n", __FUNCTION__, ep_index(ep), value);
888 +
889 + if (ep_index(ep) == 0) {
890 + /* EP0 */
891 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL);
892 + } else if (ep_is_in(ep)) {
893 + uint32_t csr = usb_readb(dev, ep->csr);
894 + if (value && ((csr & USB_INCSR_FFNOTEMPT)
895 + || !list_empty(&ep->queue))) {
896 + /*
897 + * Attempts to halt IN endpoints will fail (returning -EAGAIN)
898 + * if any transfer requests are still queued, or if the controller
899 + * FIFO still holds bytes that the host hasn\92t collected.
900 + */
901 + spin_unlock_irqrestore(&dev->lock, flags);
902 + DEBUG
903 + ("Attempt to halt IN endpoint failed (returning -EAGAIN) %d %d\n",
904 + (csr & USB_INCSR_FFNOTEMPT),
905 + !list_empty(&ep->queue));
906 + return -EAGAIN;
907 + }
908 + flush(ep);
909 + if (value) {
910 + usb_setb(dev, ep->csr, USB_INCSR_SENDSTALL);
911 + } else {
912 + usb_clearb(dev, ep->csr, USB_INCSR_SENDSTALL);
913 + usb_setb(dev, ep->csr, USB_INCSR_CDT);
914 + }
915 + } else {
916 +
917 + flush(ep);
918 + if (value) {
919 + usb_setb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
920 + } else {
921 + usb_clearb(dev, ep->csr, USB_OUTCSR_SENDSTALL);
922 + usb_setb(dev, ep->csr, USB_OUTCSR_CDT);
923 + }
924 + }
925 +
926 + ep->stopped = value;
927 +
928 + spin_unlock_irqrestore(&dev->lock, flags);
929 +
930 + DEBUG("%s %s halted\n", _ep->name, value == 0 ? "NOT" : "IS");
931 +
932 + return 0;
933 +}
934 +
935 +
936 +static int jz4740_ep_enable(struct usb_ep *_ep,
937 + const struct usb_endpoint_descriptor *desc)
938 +{
939 + struct jz4740_ep *ep;
940 + struct jz4740_udc *dev;
941 + unsigned long flags;
942 + uint32_t max, csrh = 0;
943 +
944 + DEBUG("%s: trying to enable %s\n", __FUNCTION__, _ep->name);
945 +
946 + if (!_ep || !desc)
947 + return -EINVAL;
948 +
949 + ep = container_of(_ep, struct jz4740_ep, ep);
950 + if (ep->desc || ep->type == ep_control
951 + || desc->bDescriptorType != USB_DT_ENDPOINT
952 + || ep->bEndpointAddress != desc->bEndpointAddress) {
953 + DEBUG("%s, bad ep or descriptor\n", __FUNCTION__);
954 + return -EINVAL;
955 + }
956 +
957 + /* xfer types must match, except that interrupt ~= bulk */
958 + if (ep->bmAttributes != desc->bmAttributes
959 + && ep->bmAttributes != USB_ENDPOINT_XFER_BULK
960 + && desc->bmAttributes != USB_ENDPOINT_XFER_INT) {
961 + DEBUG("%s, %s type mismatch\n", __FUNCTION__, _ep->name);
962 + return -EINVAL;
963 + }
964 +
965 + dev = ep->dev;
966 + if (!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN) {
967 + DEBUG("%s, bogus device state\n", __FUNCTION__);
968 + return -ESHUTDOWN;
969 + }
970 +
971 + max = le16_to_cpu(desc->wMaxPacketSize);
972 +
973 + spin_lock_irqsave(&ep->dev->lock, flags);
974 +
975 + /* Configure the endpoint */
976 + jz_udc_select_ep(ep);
977 + if (ep_is_in(ep)) {
978 + usb_writew(dev, JZ_REG_UDC_INMAXP, max);
979 + switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
980 + case USB_ENDPOINT_XFER_BULK:
981 + case USB_ENDPOINT_XFER_INT:
982 + csrh &= ~USB_INCSRH_ISO;
983 + break;
984 + case USB_ENDPOINT_XFER_ISOC:
985 + csrh |= USB_INCSRH_ISO;
986 + break;
987 + }
988 + usb_writeb(dev, JZ_REG_UDC_INCSRH, csrh);
989 + }
990 + else {
991 + usb_writew(dev, JZ_REG_UDC_OUTMAXP, max);
992 + switch (desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) {
993 + case USB_ENDPOINT_XFER_BULK:
994 + csrh &= ~USB_OUTCSRH_ISO;
995 + break;
996 + case USB_ENDPOINT_XFER_INT:
997 + csrh &= ~USB_OUTCSRH_ISO;
998 + csrh |= USB_OUTCSRH_DNYT;
999 + break;
1000 + case USB_ENDPOINT_XFER_ISOC:
1001 + csrh |= USB_OUTCSRH_ISO;
1002 + break;
1003 + }
1004 + usb_writeb(dev, JZ_REG_UDC_OUTCSRH, csrh);
1005 + }
1006 +
1007 +
1008 + ep->stopped = 0;
1009 + ep->desc = desc;
1010 + ep->ep.maxpacket = max;
1011 +
1012 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1013 +
1014 + /* Reset halt state (does flush) */
1015 + jz4740_set_halt(_ep, 0);
1016 +
1017 + DEBUG("%s: enabled %s\n", __FUNCTION__, _ep->name);
1018 +
1019 + return 0;
1020 +}
1021 +
1022 +/** Disable EP
1023 + * NOTE: Sets INDEX register
1024 + */
1025 +static int jz4740_ep_disable(struct usb_ep *_ep)
1026 +{
1027 + struct jz4740_ep *ep;
1028 + unsigned long flags;
1029 +
1030 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1031 +
1032 + ep = container_of(_ep, struct jz4740_ep, ep);
1033 + if (!_ep || !ep->desc) {
1034 + DEBUG("%s, %s not enabled\n", __FUNCTION__,
1035 + _ep ? ep->ep.name : NULL);
1036 + return -EINVAL;
1037 + }
1038 +
1039 + spin_lock_irqsave(&ep->dev->lock, flags);
1040 +
1041 + jz_udc_select_ep(ep);
1042 +
1043 + /* Nuke all pending requests (does flush) */
1044 + nuke(ep, -ESHUTDOWN);
1045 +
1046 + /* Disable ep IRQ */
1047 + pio_irq_disable(ep);
1048 +
1049 + ep->desc = 0;
1050 + ep->stopped = 1;
1051 +
1052 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1053 +
1054 + DEBUG("%s: disabled %s\n", __FUNCTION__, _ep->name);
1055 + return 0;
1056 +}
1057 +
1058 +static struct usb_request *jz4740_alloc_request(struct usb_ep *ep, gfp_t gfp_flags)
1059 +{
1060 + struct jz4740_request *req;
1061 +
1062 + req = kzalloc(sizeof(*req), gfp_flags);
1063 + if (!req)
1064 + return NULL;
1065 +
1066 + INIT_LIST_HEAD(&req->queue);
1067 +
1068 + return &req->req;
1069 +}
1070 +
1071 +static void jz4740_free_request(struct usb_ep *ep, struct usb_request *_req)
1072 +{
1073 + struct jz4740_request *req;
1074 +
1075 + req = container_of(_req, struct jz4740_request, req);
1076 + WARN_ON(!list_empty(&req->queue));
1077 +
1078 + kfree(req);
1079 +}
1080 +
1081 +/*--------------------------------------------------------------------*/
1082 +
1083 +/** Queue one request
1084 + * Kickstart transfer if needed
1085 + * NOTE: Sets INDEX register
1086 + */
1087 +static int jz4740_queue(struct usb_ep *_ep, struct usb_request *_req,
1088 + gfp_t gfp_flags)
1089 +{
1090 + struct jz4740_request *req;
1091 + struct jz4740_ep *ep;
1092 + struct jz4740_udc *dev;
1093 +
1094 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1095 +
1096 + req = container_of(_req, struct jz4740_request, req);
1097 + if (unlikely
1098 + (!_req || !_req->complete || !_req->buf
1099 + || !list_empty(&req->queue))) {
1100 + DEBUG("%s, bad params\n", __FUNCTION__);
1101 + return -EINVAL;
1102 + }
1103 +
1104 + ep = container_of(_ep, struct jz4740_ep, ep);
1105 + if (unlikely(!_ep || (!ep->desc && ep->type != ep_control))) {
1106 + DEBUG("%s, bad ep\n", __FUNCTION__);
1107 + return -EINVAL;
1108 + }
1109 +
1110 + dev = ep->dev;
1111 + if (unlikely(!dev->driver || dev->gadget.speed == USB_SPEED_UNKNOWN)) {
1112 + DEBUG("%s, bogus device state %p\n", __FUNCTION__, dev->driver);
1113 + return -ESHUTDOWN;
1114 + }
1115 +
1116 + DEBUG("%s queue req %p, len %d buf %p\n", _ep->name, _req, _req->length,
1117 + _req->buf);
1118 +
1119 + spin_lock_irqsave(&dev->lock, dev->lock_flags);
1120 +
1121 + _req->status = -EINPROGRESS;
1122 + _req->actual = 0;
1123 +
1124 + /* kickstart this i/o queue? */
1125 + DEBUG("Add to %d Q %d %d\n", ep_index(ep), list_empty(&ep->queue),
1126 + ep->stopped);
1127 + if (list_empty(&ep->queue) && likely(!ep->stopped)) {
1128 + uint32_t csr;
1129 +
1130 + if (unlikely(ep_index(ep) == 0)) {
1131 + /* EP0 */
1132 + list_add_tail(&req->queue, &ep->queue);
1133 + jz4740_ep0_kick(dev, ep);
1134 + req = 0;
1135 + }
1136 + else if (ep_is_in(ep)) {
1137 + /* EP1 & EP2 */
1138 + jz_udc_select_ep(ep);
1139 + csr = usb_readb(dev, ep->csr);
1140 + pio_irq_enable(ep);
1141 + if (!(csr & USB_INCSR_FFNOTEMPT)) {
1142 + if (write_fifo(ep, req) == 1)
1143 + req = 0;
1144 + }
1145 + } else {
1146 + /* EP1 */
1147 + jz_udc_select_ep(ep);
1148 + csr = usb_readb(dev, ep->csr);
1149 + pio_irq_enable(ep);
1150 + if (csr & USB_OUTCSR_OUTPKTRDY) {
1151 + if (read_fifo(ep, req) == 1)
1152 + req = 0;
1153 + }
1154 + }
1155 + }
1156 +
1157 + /* pio or dma irq handler advances the queue. */
1158 + if (likely(req != 0))
1159 + list_add_tail(&req->queue, &ep->queue);
1160 +
1161 + spin_unlock_irqrestore(&dev->lock, dev->lock_flags);
1162 +
1163 + return 0;
1164 +}
1165 +
1166 +/* dequeue JUST ONE request */
1167 +static int jz4740_dequeue(struct usb_ep *_ep, struct usb_request *_req)
1168 +{
1169 + struct jz4740_ep *ep;
1170 + struct jz4740_request *req;
1171 + unsigned long flags;
1172 +
1173 + DEBUG("%s, %p\n", __FUNCTION__, _ep);
1174 +
1175 + ep = container_of(_ep, struct jz4740_ep, ep);
1176 + if (!_ep || ep->type == ep_control)
1177 + return -EINVAL;
1178 +
1179 + spin_lock_irqsave(&ep->dev->lock, flags);
1180 +
1181 + /* make sure it's actually queued on this endpoint */
1182 + list_for_each_entry(req, &ep->queue, queue) {
1183 + if (&req->req == _req)
1184 + break;
1185 + }
1186 + if (&req->req != _req) {
1187 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1188 + return -EINVAL;
1189 + }
1190 + done(ep, req, -ECONNRESET);
1191 +
1192 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1193 + return 0;
1194 +}
1195 +
1196 +/** Return bytes in EP FIFO
1197 + * NOTE: Sets INDEX register to EP
1198 + */
1199 +static int jz4740_fifo_status(struct usb_ep *_ep)
1200 +{
1201 + uint32_t csr;
1202 + int count = 0;
1203 + struct jz4740_ep *ep;
1204 + unsigned long flags;
1205 +
1206 + ep = container_of(_ep, struct jz4740_ep, ep);
1207 + if (!_ep) {
1208 + DEBUG("%s, bad ep\n", __FUNCTION__);
1209 + return -ENODEV;
1210 + }
1211 +
1212 + DEBUG("%s, %d\n", __FUNCTION__, ep_index(ep));
1213 +
1214 + /* LPD can't report unclaimed bytes from IN fifos */
1215 + if (ep_is_in(ep))
1216 + return -EOPNOTSUPP;
1217 +
1218 + spin_lock_irqsave(&ep->dev->lock, flags);
1219 + jz_udc_select_ep(ep);
1220 +
1221 + csr = usb_readb(ep->dev, ep->csr);
1222 + if (ep->dev->gadget.speed != USB_SPEED_UNKNOWN ||
1223 + csr & 0x1) {
1224 + count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1225 + }
1226 +
1227 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1228 +
1229 + return count;
1230 +}
1231 +
1232 +/** Flush EP FIFO
1233 + * NOTE: Sets INDEX register to EP
1234 + */
1235 +static void jz4740_fifo_flush(struct usb_ep *_ep)
1236 +{
1237 + struct jz4740_ep *ep;
1238 + unsigned long flags;
1239 +
1240 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1241 +
1242 + ep = container_of(_ep, struct jz4740_ep, ep);
1243 + if (unlikely(!_ep || (!ep->desc && ep->type == ep_control))) {
1244 + DEBUG("%s, bad ep\n", __FUNCTION__);
1245 + return;
1246 + }
1247 +
1248 + spin_lock_irqsave(&ep->dev->lock, flags);
1249 +
1250 + jz_udc_select_ep(ep);
1251 + flush(ep);
1252 +
1253 + spin_unlock_irqrestore(&ep->dev->lock, flags);
1254 +}
1255 +
1256 +/****************************************************************/
1257 +/* End Point 0 related functions */
1258 +/****************************************************************/
1259 +
1260 +/* return: 0 = still running, 1 = completed, negative = errno */
1261 +static int write_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1262 +{
1263 + uint32_t max;
1264 + unsigned count;
1265 + int is_last;
1266 +
1267 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1268 + max = ep_maxpacket(ep);
1269 +
1270 + count = write_packet(ep, req, max);
1271 +
1272 + /* last packet is usually short (or a zlp) */
1273 + if (unlikely(count != max))
1274 + is_last = 1;
1275 + else {
1276 + if (likely(req->req.length != req->req.actual) || req->req.zero)
1277 + is_last = 0;
1278 + else
1279 + is_last = 1;
1280 + }
1281 +
1282 + DEBUG_EP0("%s: wrote %s %d bytes%s %d left %p\n", __FUNCTION__,
1283 + ep->ep.name, count,
1284 + is_last ? "/L" : "", req->req.length - req->req.actual, req);
1285 +
1286 + /* requests complete when all IN data is in the FIFO */
1287 + if (is_last) {
1288 + done(ep, req, 0);
1289 + return 1;
1290 + }
1291 +
1292 + return 0;
1293 +}
1294 +
1295 +static inline int jz4740_fifo_read(struct jz4740_ep *ep,
1296 + unsigned char *cp, int max)
1297 +{
1298 + int bytes;
1299 + int count = usb_readw(ep->dev, JZ_REG_UDC_OUTCOUNT);
1300 +
1301 + if (count > max)
1302 + count = max;
1303 + bytes = count;
1304 + while (count--)
1305 + *cp++ = usb_readb(ep->dev, ep->fifo);
1306 +
1307 + return bytes;
1308 +}
1309 +
1310 +static inline void jz4740_fifo_write(struct jz4740_ep *ep,
1311 + unsigned char *cp, int count)
1312 +{
1313 + DEBUG("fifo_write: %d %d\n", ep_index(ep), count);
1314 + while (count--)
1315 + usb_writeb(ep->dev, ep->fifo, *cp++);
1316 +}
1317 +
1318 +static int read_fifo_ep0(struct jz4740_ep *ep, struct jz4740_request *req)
1319 +{
1320 + struct jz4740_udc *dev = ep->dev;
1321 + uint32_t csr;
1322 + uint8_t *buf;
1323 + unsigned bufferspace, count, is_short;
1324 +
1325 + DEBUG_EP0("%s\n", __FUNCTION__);
1326 +
1327 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1328 + if (!(csr & USB_CSR0_OUTPKTRDY))
1329 + return 0;
1330 +
1331 + buf = req->req.buf + req->req.actual;
1332 + prefetchw(buf);
1333 + bufferspace = req->req.length - req->req.actual;
1334 +
1335 + /* read all bytes from this packet */
1336 + if (likely(csr & USB_CSR0_OUTPKTRDY)) {
1337 + count = usb_readw(dev, JZ_REG_UDC_OUTCOUNT);
1338 + req->req.actual += min(count, bufferspace);
1339 + } else /* zlp */
1340 + count = 0;
1341 +
1342 + is_short = (count < ep->ep.maxpacket);
1343 + DEBUG_EP0("read %s %02x, %d bytes%s req %p %d/%d\n",
1344 + ep->ep.name, csr, count,
1345 + is_short ? "/S" : "", req, req->req.actual, req->req.length);
1346 +
1347 + while (likely(count-- != 0)) {
1348 + uint8_t byte = (uint8_t)usb_readl(dev, ep->fifo);
1349 +
1350 + if (unlikely(bufferspace == 0)) {
1351 + /* this happens when the driver's buffer
1352 + * is smaller than what the host sent.
1353 + * discard the extra data.
1354 + */
1355 + if (req->req.status != -EOVERFLOW)
1356 + DEBUG_EP0("%s overflow %d\n", ep->ep.name,
1357 + count);
1358 + req->req.status = -EOVERFLOW;
1359 + } else {
1360 + *buf++ = byte;
1361 + bufferspace--;
1362 + }
1363 + }
1364 +
1365 + /* completion */
1366 + if (is_short || req->req.actual == req->req.length) {
1367 + done(ep, req, 0);
1368 + return 1;
1369 + }
1370 +
1371 + /* finished that packet. the next one may be waiting... */
1372 + return 0;
1373 +}
1374 +
1375 +/**
1376 + * udc_set_address - set the USB address for this device
1377 + * @address:
1378 + *
1379 + * Called from control endpoint function after it decodes a set address setup packet.
1380 + */
1381 +static void udc_set_address(struct jz4740_udc *dev, unsigned char address)
1382 +{
1383 + DEBUG_EP0("%s: %d\n", __FUNCTION__, address);
1384 +
1385 + usb_writeb(dev, JZ_REG_UDC_FADDR, address);
1386 +}
1387 +
1388 +/*
1389 + * DATA_STATE_RECV (USB_CSR0_OUTPKTRDY)
1390 + * - if error
1391 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1392 + * - else
1393 + * set USB_CSR0_SVDOUTPKTRDY bit
1394 + if last set USB_CSR0_DATAEND bit
1395 + */
1396 +static void jz4740_ep0_out(struct jz4740_udc *dev, uint32_t csr, int kickstart)
1397 +{
1398 + struct jz4740_request *req;
1399 + struct jz4740_ep *ep = &dev->ep[0];
1400 + int ret;
1401 +
1402 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1403 +
1404 + if (list_empty(&ep->queue))
1405 + req = 0;
1406 + else
1407 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
1408 +
1409 + if (req) {
1410 + if (req->req.length == 0) {
1411 + DEBUG_EP0("ZERO LENGTH OUT!\n");
1412 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1413 + dev->ep0state = WAIT_FOR_SETUP;
1414 + return;
1415 + } else if (kickstart) {
1416 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY));
1417 + return;
1418 + }
1419 + ret = read_fifo_ep0(ep, req);
1420 + if (ret) {
1421 + /* Done! */
1422 + DEBUG_EP0("%s: finished, waiting for status\n",
1423 + __FUNCTION__);
1424 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1425 + dev->ep0state = WAIT_FOR_SETUP;
1426 + } else {
1427 + /* Not done yet.. */
1428 + DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1429 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1430 + }
1431 + } else {
1432 + DEBUG_EP0("NO REQ??!\n");
1433 + }
1434 +}
1435 +
1436 +/*
1437 + * DATA_STATE_XMIT
1438 + */
1439 +static int jz4740_ep0_in(struct jz4740_udc *dev, uint32_t csr)
1440 +{
1441 + struct jz4740_request *req;
1442 + struct jz4740_ep *ep = &dev->ep[0];
1443 + int ret, need_zlp = 0;
1444 +
1445 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1446 +
1447 + if (list_empty(&ep->queue))
1448 + req = 0;
1449 + else
1450 + req = list_entry(ep->queue.next, struct jz4740_request, queue);
1451 +
1452 + if (!req) {
1453 + DEBUG_EP0("%s: NULL REQ\n", __FUNCTION__);
1454 + return 0;
1455 + }
1456 +
1457 + if (req->req.length == 0) {
1458 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1459 + dev->ep0state = WAIT_FOR_SETUP;
1460 + return 1;
1461 + }
1462 +
1463 + if (req->req.length - req->req.actual == EP0_MAXPACKETSIZE) {
1464 + /* Next write will end with the packet size, */
1465 + /* so we need zero-length-packet */
1466 + need_zlp = 1;
1467 + }
1468 +
1469 + ret = write_fifo_ep0(ep, req);
1470 +
1471 + if (ret == 1 && !need_zlp) {
1472 + /* Last packet */
1473 + DEBUG_EP0("%s: finished, waiting for status\n", __FUNCTION__);
1474 +
1475 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1476 + dev->ep0state = WAIT_FOR_SETUP;
1477 + } else {
1478 + DEBUG_EP0("%s: not finished\n", __FUNCTION__);
1479 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1480 + }
1481 +
1482 + if (need_zlp) {
1483 + DEBUG_EP0("%s: Need ZLP!\n", __FUNCTION__);
1484 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_INPKTRDY);
1485 + dev->ep0state = DATA_STATE_NEED_ZLP;
1486 + }
1487 +
1488 + return 1;
1489 +}
1490 +
1491 +static int jz4740_handle_get_status(struct jz4740_udc *dev,
1492 + struct usb_ctrlrequest *ctrl)
1493 +{
1494 + struct jz4740_ep *ep0 = &dev->ep[0];
1495 + struct jz4740_ep *qep;
1496 + int reqtype = (ctrl->bRequestType & USB_RECIP_MASK);
1497 + uint16_t val = 0;
1498 +
1499 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1500 +
1501 + if (reqtype == USB_RECIP_INTERFACE) {
1502 + /* This is not supported.
1503 + * And according to the USB spec, this one does nothing..
1504 + * Just return 0
1505 + */
1506 + DEBUG_SETUP("GET_STATUS: USB_RECIP_INTERFACE\n");
1507 + } else if (reqtype == USB_RECIP_DEVICE) {
1508 + DEBUG_SETUP("GET_STATUS: USB_RECIP_DEVICE\n");
1509 + val |= (1 << 0); /* Self powered */
1510 + /*val |= (1<<1); *//* Remote wakeup */
1511 + } else if (reqtype == USB_RECIP_ENDPOINT) {
1512 + int ep_num = (ctrl->wIndex & ~USB_DIR_IN);
1513 +
1514 + DEBUG_SETUP
1515 + ("GET_STATUS: USB_RECIP_ENDPOINT (%d), ctrl->wLength = %d\n",
1516 + ep_num, ctrl->wLength);
1517 +
1518 + if (ctrl->wLength > 2 || ep_num > 3)
1519 + return -EOPNOTSUPP;
1520 +
1521 + qep = &dev->ep[ep_num];
1522 + if (ep_is_in(qep) != ((ctrl->wIndex & USB_DIR_IN) ? 1 : 0)
1523 + && ep_index(qep) != 0) {
1524 + return -EOPNOTSUPP;
1525 + }
1526 +
1527 + jz_udc_select_ep(qep);
1528 +
1529 + /* Return status on next IN token */
1530 + switch (qep->type) {
1531 + case ep_control:
1532 + val =
1533 + (usb_readb(dev, qep->csr) & USB_CSR0_SENDSTALL) ==
1534 + USB_CSR0_SENDSTALL;
1535 + break;
1536 + case ep_bulk_in:
1537 + case ep_interrupt:
1538 + val =
1539 + (usb_readb(dev, qep->csr) & USB_INCSR_SENDSTALL) ==
1540 + USB_INCSR_SENDSTALL;
1541 + break;
1542 + case ep_bulk_out:
1543 + val =
1544 + (usb_readb(dev, qep->csr) & USB_OUTCSR_SENDSTALL) ==
1545 + USB_OUTCSR_SENDSTALL;
1546 + break;
1547 + }
1548 +
1549 + /* Back to EP0 index */
1550 + jz_udc_set_index(dev, 0);
1551 +
1552 + DEBUG_SETUP("GET_STATUS, ep: %d (%x), val = %d\n", ep_num,
1553 + ctrl->wIndex, val);
1554 + } else {
1555 + DEBUG_SETUP("Unknown REQ TYPE: %d\n", reqtype);
1556 + return -EOPNOTSUPP;
1557 + }
1558 +
1559 + /* Clear "out packet ready" */
1560 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1561 + /* Put status to FIFO */
1562 + jz4740_fifo_write(ep0, (uint8_t *)&val, sizeof(val));
1563 + /* Issue "In packet ready" */
1564 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1565 +
1566 + return 0;
1567 +}
1568 +
1569 +/*
1570 + * WAIT_FOR_SETUP (OUTPKTRDY)
1571 + * - read data packet from EP0 FIFO
1572 + * - decode command
1573 + * - if error
1574 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL bits
1575 + * - else
1576 + * set USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND bits
1577 + */
1578 +static void jz4740_ep0_setup(struct jz4740_udc *dev, uint32_t csr)
1579 +{
1580 + struct jz4740_ep *ep = &dev->ep[0];
1581 + struct usb_ctrlrequest ctrl;
1582 + int i;
1583 +
1584 + DEBUG_SETUP("%s: %x\n", __FUNCTION__, csr);
1585 +
1586 + /* Nuke all previous transfers */
1587 + nuke(ep, -EPROTO);
1588 +
1589 + /* read control req from fifo (8 bytes) */
1590 + jz4740_fifo_read(ep, (unsigned char *)&ctrl, 8);
1591 +
1592 + DEBUG_SETUP("SETUP %02x.%02x v%04x i%04x l%04x\n",
1593 + ctrl.bRequestType, ctrl.bRequest,
1594 + ctrl.wValue, ctrl.wIndex, ctrl.wLength);
1595 +
1596 + /* Set direction of EP0 */
1597 + if (likely(ctrl.bRequestType & USB_DIR_IN)) {
1598 + ep->bEndpointAddress |= USB_DIR_IN;
1599 + } else {
1600 + ep->bEndpointAddress &= ~USB_DIR_IN;
1601 + }
1602 +
1603 + /* Handle some SETUP packets ourselves */
1604 + switch (ctrl.bRequest) {
1605 + case USB_REQ_SET_ADDRESS:
1606 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1607 + break;
1608 +
1609 + DEBUG_SETUP("USB_REQ_SET_ADDRESS (%d)\n", ctrl.wValue);
1610 + udc_set_address(dev, ctrl.wValue);
1611 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1612 + return;
1613 +
1614 + case USB_REQ_SET_CONFIGURATION:
1615 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1616 + break;
1617 +
1618 + DEBUG_SETUP("USB_REQ_SET_CONFIGURATION (%d)\n", ctrl.wValue);
1619 +/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1620 +
1621 + /* Enable RESUME and SUSPEND interrupts */
1622 + usb_setb(dev, JZ_REG_UDC_INTRUSBE, (USB_INTR_RESUME | USB_INTR_SUSPEND));
1623 + break;
1624 +
1625 + case USB_REQ_SET_INTERFACE:
1626 + if (ctrl.bRequestType != (USB_TYPE_STANDARD | USB_RECIP_DEVICE))
1627 + break;
1628 +
1629 + DEBUG_SETUP("USB_REQ_SET_INTERFACE (%d)\n", ctrl.wValue);
1630 +/* usb_setb(JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));*/
1631 + break;
1632 +
1633 + case USB_REQ_GET_STATUS:
1634 + if (jz4740_handle_get_status(dev, &ctrl) == 0)
1635 + return;
1636 +
1637 + case USB_REQ_CLEAR_FEATURE:
1638 + case USB_REQ_SET_FEATURE:
1639 + if (ctrl.bRequestType == USB_RECIP_ENDPOINT) {
1640 + struct jz4740_ep *qep;
1641 + int ep_num = (ctrl.wIndex & 0x0f);
1642 +
1643 + /* Support only HALT feature */
1644 + if (ctrl.wValue != 0 || ctrl.wLength != 0
1645 + || ep_num > 3 || ep_num < 1)
1646 + break;
1647 +
1648 + qep = &dev->ep[ep_num];
1649 + spin_unlock(&dev->lock);
1650 + if (ctrl.bRequest == USB_REQ_SET_FEATURE) {
1651 + DEBUG_SETUP("SET_FEATURE (%d)\n",
1652 + ep_num);
1653 + jz4740_set_halt(&qep->ep, 1);
1654 + } else {
1655 + DEBUG_SETUP("CLR_FEATURE (%d)\n",
1656 + ep_num);
1657 + jz4740_set_halt(&qep->ep, 0);
1658 + }
1659 + spin_lock(&dev->lock);
1660 +
1661 + jz_udc_set_index(dev, 0);
1662 +
1663 + /* Reply with a ZLP on next IN token */
1664 + usb_setb(dev, JZ_REG_UDC_CSR0,
1665 + (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND));
1666 + return;
1667 + }
1668 + break;
1669 +
1670 + default:
1671 + break;
1672 + }
1673 +
1674 + /* gadget drivers see class/vendor specific requests,
1675 + * {SET,GET}_{INTERFACE,DESCRIPTOR,CONFIGURATION},
1676 + * and more.
1677 + */
1678 + if (dev->driver) {
1679 + /* device-2-host (IN) or no data setup command, process immediately */
1680 + spin_unlock(&dev->lock);
1681 +
1682 + i = dev->driver->setup(&dev->gadget, &ctrl);
1683 + spin_lock(&dev->lock);
1684 +
1685 + if (unlikely(i < 0)) {
1686 + /* setup processing failed, force stall */
1687 + DEBUG_SETUP
1688 + (" --> ERROR: gadget setup FAILED (stalling), setup returned %d\n",
1689 + i);
1690 + jz_udc_set_index(dev, 0);
1691 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_SVDOUTPKTRDY | USB_CSR0_DATAEND | USB_CSR0_SENDSTALL));
1692 +
1693 + /* ep->stopped = 1; */
1694 + dev->ep0state = WAIT_FOR_SETUP;
1695 + }
1696 + else {
1697 + DEBUG_SETUP("gadget driver setup ok (%d)\n", ctrl.wLength);
1698 +/* if (!ctrl.wLength) {
1699 + usb_setb(JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1700 + }*/
1701 + }
1702 + }
1703 +}
1704 +
1705 +/*
1706 + * DATA_STATE_NEED_ZLP
1707 + */
1708 +static void jz4740_ep0_in_zlp(struct jz4740_udc *dev, uint32_t csr)
1709 +{
1710 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1711 +
1712 + usb_setb(dev, JZ_REG_UDC_CSR0, (USB_CSR0_INPKTRDY | USB_CSR0_DATAEND));
1713 + dev->ep0state = WAIT_FOR_SETUP;
1714 +}
1715 +
1716 +/*
1717 + * handle ep0 interrupt
1718 + */
1719 +static void jz4740_handle_ep0(struct jz4740_udc *dev, uint32_t intr)
1720 +{
1721 + struct jz4740_ep *ep = &dev->ep[0];
1722 + uint32_t csr;
1723 +
1724 + DEBUG("%s:%s[%d]\n", __FILE__, __func__, __LINE__);
1725 + /* Set index 0 */
1726 + jz_udc_set_index(dev, 0);
1727 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1728 +
1729 + DEBUG_EP0("%s: csr = %x state = \n", __FUNCTION__, csr);//, state_names[dev->ep0state]);
1730 +
1731 + /*
1732 + * if SENT_STALL is set
1733 + * - clear the SENT_STALL bit
1734 + */
1735 + if (csr & USB_CSR0_SENTSTALL) {
1736 + DEBUG_EP0("%s: USB_CSR0_SENTSTALL is set: %x\n", __FUNCTION__, csr);
1737 + usb_clearb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SENDSTALL | USB_CSR0_SENTSTALL);
1738 + nuke(ep, -ECONNABORTED);
1739 + dev->ep0state = WAIT_FOR_SETUP;
1740 + return;
1741 + }
1742 +
1743 + /*
1744 + * if a transfer is in progress && INPKTRDY and OUTPKTRDY are clear
1745 + * - fill EP0 FIFO
1746 + * - if last packet
1747 + * - set IN_PKT_RDY | DATA_END
1748 + * - else
1749 + * set IN_PKT_RDY
1750 + */
1751 + if (!(csr & (USB_CSR0_INPKTRDY | USB_CSR0_OUTPKTRDY))) {
1752 + DEBUG_EP0("%s: INPKTRDY and OUTPKTRDY are clear\n",
1753 + __FUNCTION__);
1754 +
1755 + switch (dev->ep0state) {
1756 + case DATA_STATE_XMIT:
1757 + DEBUG_EP0("continue with DATA_STATE_XMIT\n");
1758 + jz4740_ep0_in(dev, csr);
1759 + return;
1760 + case DATA_STATE_NEED_ZLP:
1761 + DEBUG_EP0("continue with DATA_STATE_NEED_ZLP\n");
1762 + jz4740_ep0_in_zlp(dev, csr);
1763 + return;
1764 + default:
1765 + /* Stall? */
1766 +// DEBUG_EP0("Odd state!! state = %s\n",
1767 +// state_names[dev->ep0state]);
1768 + dev->ep0state = WAIT_FOR_SETUP;
1769 + /* nuke(ep, 0); */
1770 + /* usb_setb(ep->csr, USB_CSR0_SENDSTALL); */
1771 +// break;
1772 + return;
1773 + }
1774 + }
1775 +
1776 + /*
1777 + * if SETUPEND is set
1778 + * - abort the last transfer
1779 + * - set SERVICED_SETUP_END_BIT
1780 + */
1781 + if (csr & USB_CSR0_SETUPEND) {
1782 + DEBUG_EP0("%s: USB_CSR0_SETUPEND is set: %x\n", __FUNCTION__, csr);
1783 +
1784 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDSETUPEND);
1785 + nuke(ep, 0);
1786 + dev->ep0state = WAIT_FOR_SETUP;
1787 + }
1788 +
1789 + /*
1790 + * if USB_CSR0_OUTPKTRDY is set
1791 + * - read data packet from EP0 FIFO
1792 + * - decode command
1793 + * - if error
1794 + * set SVDOUTPKTRDY | DATAEND | SENDSTALL bits
1795 + * - else
1796 + * set SVDOUTPKTRDY | DATAEND bits
1797 + */
1798 + if (csr & USB_CSR0_OUTPKTRDY) {
1799 +
1800 + DEBUG_EP0("%s: EP0_OUT_PKT_RDY is set: %x\n", __FUNCTION__,
1801 + csr);
1802 +
1803 + switch (dev->ep0state) {
1804 + case WAIT_FOR_SETUP:
1805 + DEBUG_EP0("WAIT_FOR_SETUP\n");
1806 + jz4740_ep0_setup(dev, csr);
1807 + break;
1808 +
1809 + case DATA_STATE_RECV:
1810 + DEBUG_EP0("DATA_STATE_RECV\n");
1811 + jz4740_ep0_out(dev, csr, 0);
1812 + break;
1813 +
1814 + default:
1815 + /* send stall? */
1816 + DEBUG_EP0("strange state!! 2. send stall? state = %d\n",
1817 + dev->ep0state);
1818 + break;
1819 + }
1820 + }
1821 +}
1822 +
1823 +static void jz4740_ep0_kick(struct jz4740_udc *dev, struct jz4740_ep *ep)
1824 +{
1825 + uint32_t csr;
1826 +
1827 + jz_udc_set_index(dev, 0);
1828 +
1829 + DEBUG_EP0("%s: %x\n", __FUNCTION__, csr);
1830 +
1831 + /* Clear "out packet ready" */
1832 +
1833 + if (ep_is_in(ep)) {
1834 + usb_setb(dev, JZ_REG_UDC_CSR0, USB_CSR0_SVDOUTPKTRDY);
1835 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1836 + dev->ep0state = DATA_STATE_XMIT;
1837 + jz4740_ep0_in(dev, csr);
1838 + } else {
1839 + csr = usb_readb(dev, JZ_REG_UDC_CSR0);
1840 + dev->ep0state = DATA_STATE_RECV;
1841 + jz4740_ep0_out(dev, csr, 1);
1842 + }
1843 +}
1844 +
1845 +/** Handle USB RESET interrupt
1846 + */
1847 +static void jz4740_reset_irq(struct jz4740_udc *dev)
1848 +{
1849 + dev->gadget.speed = (usb_readb(dev, JZ_REG_UDC_POWER) & USB_POWER_HSMODE) ?
1850 + USB_SPEED_HIGH : USB_SPEED_FULL;
1851 +
1852 + DEBUG_SETUP("%s: address = %d, speed = %s\n", __FUNCTION__, 0,
1853 + (dev->gadget.speed == USB_SPEED_HIGH) ? "HIGH":"FULL" );
1854 +}
1855 +
1856 +/*
1857 + * jz4740 usb device interrupt handler.
1858 + */
1859 +static irqreturn_t jz4740_udc_irq(int irq, void *devid)
1860 +{
1861 + struct jz4740_udc *jz4740_udc = devid;
1862 + uint8_t index;
1863 +
1864 + uint32_t intr_usb = usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSB) & 0x7; /* mask SOF */
1865 + uint32_t intr_in = usb_readw(jz4740_udc, JZ_REG_UDC_INTRIN);
1866 + uint32_t intr_out = usb_readw(jz4740_udc, JZ_REG_UDC_INTROUT);
1867 + uint32_t intr_dma = usb_readb(jz4740_udc, JZ_REG_UDC_INTR);
1868 +
1869 + if (!intr_usb && !intr_in && !intr_out && !intr_dma)
1870 + return IRQ_HANDLED;
1871 +
1872 +
1873 + DEBUG("intr_out=%x intr_in=%x intr_usb=%x\n",
1874 + intr_out, intr_in, intr_usb);
1875 +
1876 + spin_lock(&jz4740_udc->lock);
1877 + index = usb_readb(jz4740_udc, JZ_REG_UDC_INDEX);
1878 +
1879 + /* Check for resume from suspend mode */
1880 + if ((intr_usb & USB_INTR_RESUME) &&
1881 + (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_RESUME)) {
1882 + DEBUG("USB resume\n");
1883 + jz4740_udc->driver->resume(&jz4740_udc->gadget); /* We have suspend(), so we must have resume() too. */
1884 + }
1885 +
1886 + /* Check for system interrupts */
1887 + if (intr_usb & USB_INTR_RESET) {
1888 + DEBUG("USB reset\n");
1889 + jz4740_reset_irq(jz4740_udc);
1890 + }
1891 +
1892 + /* Check for endpoint 0 interrupt */
1893 + if (intr_in & USB_INTR_EP0) {
1894 + DEBUG("USB_INTR_EP0 (control)\n");
1895 + jz4740_handle_ep0(jz4740_udc, intr_in);
1896 + }
1897 +
1898 + /* Check for Bulk-IN DMA interrupt */
1899 + if (intr_dma & 0x1) {
1900 + int ep_num;
1901 + struct jz4740_ep *ep;
1902 + ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL1) >> 4) & 0xf;
1903 + ep = &jz4740_udc->ep[ep_num + 1];
1904 + jz_udc_select_ep(ep);
1905 + usb_setb(jz4740_udc, ep->csr, USB_INCSR_INPKTRDY);
1906 +/* jz4740_in_epn(jz4740_udc, ep_num, intr_in);*/
1907 + }
1908 +
1909 + /* Check for Bulk-OUT DMA interrupt */
1910 + if (intr_dma & 0x2) {
1911 + int ep_num;
1912 + ep_num = (usb_readl(jz4740_udc, JZ_REG_UDC_CNTL2) >> 4) & 0xf;
1913 + jz4740_out_epn(jz4740_udc, ep_num, intr_out);
1914 + }
1915 +
1916 + /* Check for each configured endpoint interrupt */
1917 + if (intr_in & USB_INTR_INEP1) {
1918 + DEBUG("USB_INTR_INEP1\n");
1919 + jz4740_in_epn(jz4740_udc, 1, intr_in);
1920 + }
1921 +
1922 + if (intr_in & USB_INTR_INEP2) {
1923 + DEBUG("USB_INTR_INEP2\n");
1924 + jz4740_in_epn(jz4740_udc, 2, intr_in);
1925 + }
1926 +
1927 + if (intr_out & USB_INTR_OUTEP1) {
1928 + DEBUG("USB_INTR_OUTEP1\n");
1929 + jz4740_out_epn(jz4740_udc, 1, intr_out);
1930 + }
1931 +
1932 + /* Check for suspend mode */
1933 + if ((intr_usb & USB_INTR_SUSPEND) &&
1934 + (usb_readb(jz4740_udc, JZ_REG_UDC_INTRUSBE) & USB_INTR_SUSPEND)) {
1935 + DEBUG("USB suspend\n");
1936 + jz4740_udc->driver->suspend(&jz4740_udc->gadget);
1937 + /* Host unloaded from us, can do something, such as flushing
1938 + the NAND block cache etc. */
1939 + }
1940 +
1941 + jz_udc_set_index(jz4740_udc, index);
1942 +
1943 + spin_unlock(&jz4740_udc->lock);
1944 +
1945 + return IRQ_HANDLED;
1946 +}
1947 +
1948 +
1949 +
1950 +/*-------------------------------------------------------------------------*/
1951 +
1952 +
1953 +static inline struct jz4740_udc *gadget_to_udc(struct usb_gadget *gadget)
1954 +{
1955 + return container_of(gadget, struct jz4740_udc, gadget);
1956 +}
1957 +
1958 +static int jz4740_udc_get_frame(struct usb_gadget *_gadget)
1959 +{
1960 + DEBUG("%s, %p\n", __FUNCTION__, _gadget);
1961 + return usb_readw(gadget_to_udc(_gadget), JZ_REG_UDC_FRAME);
1962 +}
1963 +
1964 +static int jz4740_udc_wakeup(struct usb_gadget *_gadget)
1965 +{
1966 + /* host may not have enabled remote wakeup */
1967 + /*if ((UDCCS0 & UDCCS0_DRWF) == 0)
1968 + return -EHOSTUNREACH;
1969 + udc_set_mask_UDCCR(UDCCR_RSM); */
1970 + return -ENOTSUPP;
1971 +}
1972 +
1973 +static int jz4740_udc_pullup(struct usb_gadget *_gadget, int on)
1974 +{
1975 + struct jz4740_udc *udc = gadget_to_udc(_gadget);
1976 + unsigned long flags;
1977 +
1978 + local_irq_save(flags);
1979 +
1980 + if (on) {
1981 + udc->state = UDC_STATE_ENABLE;
1982 + udc_enable(udc);
1983 + } else {
1984 + udc->state = UDC_STATE_DISABLE;
1985 + udc_disable(udc);
1986 + }
1987 +
1988 + local_irq_restore(flags);
1989 +
1990 + return 0;
1991 +}
1992 +
1993 +
1994 +static const struct usb_gadget_ops jz4740_udc_ops = {
1995 + .get_frame = jz4740_udc_get_frame,
1996 + .wakeup = jz4740_udc_wakeup,
1997 + .pullup = jz4740_udc_pullup,
1998 + .start = jz4740_udc_start,
1999 + .stop = jz4740_udc_stop,
2000 +};
2001 +
2002 +static struct usb_ep_ops jz4740_ep_ops = {
2003 + .enable = jz4740_ep_enable,
2004 + .disable = jz4740_ep_disable,
2005 +
2006 + .alloc_request = jz4740_alloc_request,
2007 + .free_request = jz4740_free_request,
2008 +
2009 + .queue = jz4740_queue,
2010 + .dequeue = jz4740_dequeue,
2011 +
2012 + .set_halt = jz4740_set_halt,
2013 + .fifo_status = jz4740_fifo_status,
2014 + .fifo_flush = jz4740_fifo_flush,
2015 +};
2016 +
2017 +
2018 +/*-------------------------------------------------------------------------*/
2019 +
2020 +static struct jz4740_udc jz4740_udc_controller = {
2021 + .gadget = {
2022 + .ops = &jz4740_udc_ops,
2023 + .ep0 = &jz4740_udc_controller.ep[0].ep,
2024 + .name = "jz4740-udc",
2025 + .dev = {
2026 + .init_name = "gadget",
2027 + },
2028 + },
2029 +
2030 + /* control endpoint */
2031 + .ep[0] = {
2032 + .ep = {
2033 + .name = "ep0",
2034 + .ops = &jz4740_ep_ops,
2035 + .maxpacket = EP0_MAXPACKETSIZE,
2036 + },
2037 + .dev = &jz4740_udc_controller,
2038 +
2039 + .bEndpointAddress = 0,
2040 + .bmAttributes = 0,
2041 +
2042 + .type = ep_control,
2043 + .fifo = JZ_REG_UDC_EP_FIFO(0),
2044 + .csr = JZ_REG_UDC_CSR0,
2045 + },
2046 +
2047 + /* bulk out endpoint */
2048 + .ep[1] = {
2049 + .ep = {
2050 + .name = "ep1out-bulk",
2051 + .ops = &jz4740_ep_ops,
2052 + .maxpacket = EPBULK_MAXPACKETSIZE,
2053 + },
2054 + .dev = &jz4740_udc_controller,
2055 +
2056 + .bEndpointAddress = 1,
2057 + .bmAttributes = USB_ENDPOINT_XFER_BULK,
2058 +
2059 + .type = ep_bulk_out,
2060 + .fifo = JZ_REG_UDC_EP_FIFO(1),
2061 + .csr = JZ_REG_UDC_OUTCSR,
2062 + },
2063 +
2064 + /* bulk in endpoint */
2065 + .ep[2] = {
2066 + .ep = {
2067 + .name = "ep1in-bulk",
2068 + .ops = &jz4740_ep_ops,
2069 + .maxpacket = EPBULK_MAXPACKETSIZE,
2070 + },
2071 + .dev = &jz4740_udc_controller,
2072 +
2073 + .bEndpointAddress = 1 | USB_DIR_IN,
2074 + .bmAttributes = USB_ENDPOINT_XFER_BULK,
2075 +
2076 + .type = ep_bulk_in,
2077 + .fifo = JZ_REG_UDC_EP_FIFO(1),
2078 + .csr = JZ_REG_UDC_INCSR,
2079 + },
2080 +
2081 + /* interrupt in endpoint */
2082 + .ep[3] = {
2083 + .ep = {
2084 + .name = "ep2in-int",
2085 + .ops = &jz4740_ep_ops,
2086 + .maxpacket = EPINTR_MAXPACKETSIZE,
2087 + },
2088 + .dev = &jz4740_udc_controller,
2089 +
2090 + .bEndpointAddress = 2 | USB_DIR_IN,
2091 + .bmAttributes = USB_ENDPOINT_XFER_INT,
2092 +
2093 + .type = ep_interrupt,
2094 + .fifo = JZ_REG_UDC_EP_FIFO(2),
2095 + .csr = JZ_REG_UDC_INCSR,
2096 + },
2097 +};
2098 +
2099 +static int __devinit jz4740_udc_probe(struct platform_device *pdev)
2100 +{
2101 + struct jz4740_udc *jz4740_udc = &jz4740_udc_controller;
2102 + int ret;
2103 +
2104 + spin_lock_init(&jz4740_udc->lock);
2105 +
2106 + jz4740_udc->dev = &pdev->dev;
2107 + jz4740_udc->gadget.dev.parent = &pdev->dev;
2108 + jz4740_udc->gadget.dev.dma_mask = pdev->dev.dma_mask;
2109 +
2110 + ret = device_register(&jz4740_udc->gadget.dev);
2111 + if (ret)
2112 + return ret;
2113 +
2114 + jz4740_udc->clk = clk_get(&pdev->dev, "udc");
2115 + if (IS_ERR(jz4740_udc->clk)) {
2116 + ret = PTR_ERR(jz4740_udc->clk);
2117 + dev_err(&pdev->dev, "Failed to get udc clock: %d\n", ret);
2118 + goto err_device_unregister;
2119 + }
2120 +
2121 + platform_set_drvdata(pdev, jz4740_udc);
2122 +
2123 + jz4740_udc->mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2124 +
2125 + if (!jz4740_udc->mem) {
2126 + ret = -ENOENT;
2127 + dev_err(&pdev->dev, "Failed to get mmio memory resource\n");
2128 + goto err_clk_put;
2129 + }
2130 +
2131 + jz4740_udc->mem = request_mem_region(jz4740_udc->mem->start,
2132 + resource_size(jz4740_udc->mem), pdev->name);
2133 +
2134 + if (!jz4740_udc->mem) {
2135 + ret = -EBUSY;
2136 + dev_err(&pdev->dev, "Failed to request mmio memory region\n");
2137 + goto err_device_unregister;
2138 + }
2139 +
2140 + jz4740_udc->base = ioremap(jz4740_udc->mem->start, resource_size(jz4740_udc->mem));
2141 +
2142 + if (!jz4740_udc->base) {
2143 + ret = -EBUSY;
2144 + dev_err(&pdev->dev, "Failed to ioremap mmio memory\n");
2145 + goto err_release_mem_region;
2146 + }
2147 +
2148 + jz4740_udc->irq = platform_get_irq(pdev, 0);
2149 + ret = request_irq(jz4740_udc->irq, jz4740_udc_irq, 0, pdev->name,
2150 + jz4740_udc);
2151 + if (ret) {
2152 + dev_err(&pdev->dev, "Failed to request irq: %d\n", ret);
2153 + goto err_iounmap;
2154 + }
2155 +
2156 + ret = usb_add_gadget_udc(&pdev->dev, &jz4740_udc->gadget);
2157 + if (ret) {
2158 + dev_err(&pdev->dev, "Failed to add gadget: %d\n", ret);
2159 + goto err_free_irq;
2160 + }
2161 +
2162 + udc_disable(jz4740_udc);
2163 + udc_reinit(jz4740_udc);
2164 +
2165 + return 0;
2166 +
2167 +err_free_irq:
2168 + free_irq(jz4740_udc->irq, pdev);
2169 +err_iounmap:
2170 + iounmap(jz4740_udc->base);
2171 +err_release_mem_region:
2172 + release_mem_region(jz4740_udc->mem->start, resource_size(jz4740_udc->mem));
2173 +err_clk_put:
2174 + clk_put(jz4740_udc->clk);
2175 +err_device_unregister:
2176 + device_unregister(&jz4740_udc->gadget.dev);
2177 + platform_set_drvdata(pdev, NULL);
2178 +
2179 + return ret;
2180 +}
2181 +
2182 +static int __devexit jz4740_udc_remove(struct platform_device *pdev)
2183 +{
2184 + struct jz4740_udc *dev = platform_get_drvdata(pdev);
2185 +
2186 + usb_del_gadget_udc(&dev->gadget);
2187 + if (dev->driver)
2188 + return -EBUSY;
2189 +
2190 + udc_disable(dev);
2191 +
2192 + free_irq(dev->irq, dev);
2193 + iounmap(dev->base);
2194 + release_mem_region(dev->mem->start, resource_size(dev->mem));
2195 + clk_put(dev->clk);
2196 +
2197 + platform_set_drvdata(pdev, NULL);
2198 + device_unregister(&dev->gadget.dev);
2199 +
2200 + return 0;
2201 +}
2202 +
2203 +#ifdef CONFIG_PM
2204 +
2205 +static int jz4740_udc_suspend(struct device *dev)
2206 +{
2207 + struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev);
2208 +
2209 + if (jz4740_udc->state == UDC_STATE_ENABLE)
2210 + udc_disable(jz4740_udc);
2211 +
2212 + return 0;
2213 +}
2214 +
2215 +static int jz4740_udc_resume(struct device *dev)
2216 +{
2217 + struct jz4740_udc *jz4740_udc = dev_get_drvdata(dev);
2218 +
2219 + if (jz4740_udc->state == UDC_STATE_ENABLE)
2220 + udc_enable(jz4740_udc);
2221 +
2222 + return 0;
2223 +}
2224 +
2225 +static SIMPLE_DEV_PM_OPS(jz4740_udc_pm_ops, jz4740_udc_suspend, jz4740_udc_resume);
2226 +#define JZ4740_UDC_PM_OPS (&jz4740_udc_pm_ops)
2227 +
2228 +#else
2229 +#define JZ4740_UDC_PM_OPS NULL
2230 +#endif
2231 +
2232 +static struct platform_driver udc_driver = {
2233 + .probe = jz4740_udc_probe,
2234 + .remove = __devexit_p(jz4740_udc_remove),
2235 + .driver = {
2236 + .name = "jz-udc",
2237 + .owner = THIS_MODULE,
2238 + .pm = JZ4740_UDC_PM_OPS,
2239 + },
2240 +};
2241 +
2242 +/*-------------------------------------------------------------------------*/
2243 +
2244 +static int __init udc_init (void)
2245 +{
2246 + return platform_driver_register(&udc_driver);
2247 +}
2248 +module_init(udc_init);
2249 +
2250 +static void __exit udc_exit (void)
2251 +{
2252 + platform_driver_unregister(&udc_driver);
2253 +}
2254 +module_exit(udc_exit);
2255 +
2256 +MODULE_DESCRIPTION("JZ4740 USB Device Controller");
2257 +MODULE_AUTHOR("Wei Jianli <jlwei@ingenic.cn>");
2258 +MODULE_LICENSE("GPL");
2259 --- /dev/null
2260 +++ b/drivers/usb/gadget/jz4740_udc.h
2261 @@ -0,0 +1,101 @@
2262 +/*
2263 + * linux/drivers/usb/gadget/jz4740_udc.h
2264 + *
2265 + * Ingenic JZ4740 on-chip high speed USB device controller
2266 + *
2267 + * Copyright (C) 2006 Ingenic Semiconductor Inc.
2268 + * Author: <jlwei@ingenic.cn>
2269 + *
2270 + * This program is free software; you can redistribute it and/or modify
2271 + * it under the terms of the GNU General Public License as published by
2272 + * the Free Software Foundation; either version 2 of the License, or
2273 + * (at your option) any later version.
2274 + */
2275 +
2276 +#ifndef __USB_GADGET_JZ4740_H__
2277 +#define __USB_GADGET_JZ4740_H__
2278 +
2279 +/*-------------------------------------------------------------------------*/
2280 +
2281 +// Max packet size
2282 +#define EP0_MAXPACKETSIZE 64
2283 +#define EPBULK_MAXPACKETSIZE 512
2284 +#define EPINTR_MAXPACKETSIZE 64
2285 +
2286 +#define UDC_MAX_ENDPOINTS 4
2287 +
2288 +/*-------------------------------------------------------------------------*/
2289 +
2290 +enum ep_type {
2291 + ep_control, ep_bulk_in, ep_bulk_out, ep_interrupt
2292 +};
2293 +
2294 +struct jz4740_ep {
2295 + struct usb_ep ep;
2296 + struct jz4740_udc *dev;
2297 +
2298 + const struct usb_endpoint_descriptor *desc;
2299 +
2300 + uint8_t stopped;
2301 + uint8_t bEndpointAddress;
2302 + uint8_t bmAttributes;
2303 +
2304 + enum ep_type type;
2305 + size_t fifo;
2306 + uint32_t csr;
2307 +
2308 + uint32_t reg_addr;
2309 + struct list_head queue;
2310 +};
2311 +
2312 +struct jz4740_request {
2313 + struct usb_request req;
2314 + struct list_head queue;
2315 +};
2316 +
2317 +enum ep0state {
2318 + WAIT_FOR_SETUP, /* between STATUS ack and SETUP report */
2319 + DATA_STATE_XMIT, /* data tx stage */
2320 + DATA_STATE_NEED_ZLP, /* data tx zlp stage */
2321 + WAIT_FOR_OUT_STATUS, /* status stages */
2322 + DATA_STATE_RECV, /* data rx stage */
2323 +};
2324 +
2325 +/* For function binding with UDC Disable - Added by River */
2326 +typedef enum {
2327 + UDC_STATE_ENABLE = 0,
2328 + UDC_STATE_DISABLE,
2329 +}udc_state_t;
2330 +
2331 +struct jz4740_udc {
2332 + struct usb_gadget gadget;
2333 + struct usb_gadget_driver *driver;
2334 + struct device *dev;
2335 + spinlock_t lock;
2336 + unsigned long lock_flags;
2337 +
2338 + enum ep0state ep0state;
2339 + struct jz4740_ep ep[UDC_MAX_ENDPOINTS];
2340 +
2341 + udc_state_t state;
2342 +
2343 + struct resource *mem;
2344 + void __iomem *base;
2345 + int irq;
2346 +
2347 + struct clk *clk;
2348 +};
2349 +
2350 +#define ep_maxpacket(EP) ((EP)->ep.maxpacket)
2351 +
2352 +static inline bool ep_is_in(const struct jz4740_ep *ep)
2353 +{
2354 + return (ep->bEndpointAddress & USB_DIR_IN) == USB_DIR_IN;
2355 +}
2356 +
2357 +static inline uint8_t ep_index(const struct jz4740_ep *ep)
2358 +{
2359 + return ep->bEndpointAddress & 0xf;
2360 +}
2361 +
2362 +#endif /* __USB_GADGET_JZ4740_H__ */
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