both coldfire and etrax are broken and should use a newer gcc when they will be fixed
[openwrt/openwrt.git] / toolchain / gcc / patches / 4.3.5 / 410-fix_pr37436.patch
1 --- a/gcc/config/arm/arm.c
2 +++ b/gcc/config/arm/arm.c
3 @@ -3769,6 +3769,7 @@ arm_legitimate_address_p (enum machine_m
4 rtx xop1 = XEXP (x, 1);
5
6 return ((arm_address_register_rtx_p (xop0, strict_p)
7 + && GET_CODE(xop1) == CONST_INT
8 && arm_legitimate_index_p (mode, xop1, outer, strict_p))
9 || (arm_address_register_rtx_p (xop1, strict_p)
10 && arm_legitimate_index_p (mode, xop0, outer, strict_p)));
11 --- a/gcc/config/arm/arm.md
12 +++ b/gcc/config/arm/arm.md
13 @@ -4199,7 +4199,7 @@
14
15 (define_expand "extendqihi2"
16 [(set (match_dup 2)
17 - (ashift:SI (match_operand:QI 1 "general_operand" "")
18 + (ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "")
19 (const_int 24)))
20 (set (match_operand:HI 0 "s_register_operand" "")
21 (ashiftrt:SI (match_dup 2)
22 @@ -4224,7 +4224,7 @@
23
24 (define_insn "*arm_extendqihi_insn"
25 [(set (match_operand:HI 0 "s_register_operand" "=r")
26 - (sign_extend:HI (match_operand:QI 1 "memory_operand" "Uq")))]
27 + (sign_extend:HI (match_operand:QI 1 "arm_extendqisi_mem_op" "Uq")))]
28 "TARGET_ARM && arm_arch4"
29 "ldr%(sb%)\\t%0, %1"
30 [(set_attr "type" "load_byte")
31 @@ -4235,7 +4235,7 @@
32
33 (define_expand "extendqisi2"
34 [(set (match_dup 2)
35 - (ashift:SI (match_operand:QI 1 "general_operand" "")
36 + (ashift:SI (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "")
37 (const_int 24)))
38 (set (match_operand:SI 0 "s_register_operand" "")
39 (ashiftrt:SI (match_dup 2)
40 @@ -4267,7 +4267,7 @@
41
42 (define_insn "*arm_extendqisi"
43 [(set (match_operand:SI 0 "s_register_operand" "=r")
44 - (sign_extend:SI (match_operand:QI 1 "memory_operand" "Uq")))]
45 + (sign_extend:SI (match_operand:QI 1 "arm_extendqisi_mem_op" "Uq")))]
46 "TARGET_ARM && arm_arch4 && !arm_arch6"
47 "ldr%(sb%)\\t%0, %1"
48 [(set_attr "type" "load_byte")
49 @@ -4278,7 +4278,8 @@
50
51 (define_insn "*arm_extendqisi_v6"
52 [(set (match_operand:SI 0 "s_register_operand" "=r,r")
53 - (sign_extend:SI (match_operand:QI 1 "nonimmediate_operand" "r,Uq")))]
54 + (sign_extend:SI
55 + (match_operand:QI 1 "arm_reg_or_extendqisi_mem_op" "r,Uq")))]
56 "TARGET_ARM && arm_arch6"
57 "@
58 sxtb%?\\t%0, %1
59 --- a/gcc/config/arm/predicates.md
60 +++ b/gcc/config/arm/predicates.md
61 @@ -234,6 +234,10 @@
62 (match_test "arm_legitimate_address_p (mode, XEXP (op, 0), SIGN_EXTEND,
63 0)")))
64
65 +(define_special_predicate "arm_reg_or_extendqisi_mem_op"
66 + (ior (match_operand 0 "arm_extendqisi_mem_op")
67 + (match_operand 0 "s_register_operand")))
68 +
69 (define_predicate "power_of_two_operand"
70 (match_code "const_int")
71 {