ag71xx: fix wrong register definition issue

Documentation fix from QCA SDK.

Signed-off-by: Rosen Penev <rosenp@gmail.com>

diff --git a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
index 0773f1a5af0e524a4d6f6f99957a3eea264b4763..fca072a83a4d3b9fbc7074822188b1fa1820d06a 100644 (file)
--- a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
+++ b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx.h
@@ -310,11 +310,11 @@ ag71xx_ring_size_order(int size)
 #define FIFO_CFG4_MC           BIT(8)  /* Multicast Packet */
 #define FIFO_CFG4_BC           BIT(9)  /* Broadcast Packet */
 #define FIFO_CFG4_DR           BIT(10) /* Dribble */
-#define FIFO_CFG4_LE           BIT(11) /* Long Event */
-#define FIFO_CFG4_CF           BIT(12) /* Control Frame */
-#define FIFO_CFG4_PF           BIT(13) /* Pause Frame */
-#define FIFO_CFG4_UO           BIT(14) /* Unsupported Opcode */
-#define FIFO_CFG4_VT           BIT(15) /* VLAN tag detected */
+#define FIFO_CFG4_CF           BIT(11) /* Control Frame */
+#define FIFO_CFG4_PF           BIT(12) /* Pause Frame */
+#define FIFO_CFG4_UO           BIT(13) /* Unsupported Opcode */
+#define FIFO_CFG4_VT           BIT(14) /* VLAN tag detected */
+#define FIFO_CFG4_LE           BIT(15) /* Long Event */
 #define FIFO_CFG4_FT           BIT(16) /* Frame Truncated */
 #define FIFO_CFG4_UC           BIT(17) /* Unicast Packet */
 
@@ -322,20 +322,20 @@ ag71xx_ring_size_order(int size)
 #define FIFO_CFG5_DV           BIT(1)  /* RX_DV Event */
 #define FIFO_CFG5_FC           BIT(2)  /* False Carrier */
 #define FIFO_CFG5_CE           BIT(3)  /* Code Error */
-#define FIFO_CFG5_LM           BIT(4)  /* Length Mismatch */
-#define FIFO_CFG5_LO           BIT(5)  /* Length Out of Range */
-#define FIFO_CFG5_OK           BIT(6)  /* Packet is OK */
-#define FIFO_CFG5_MC           BIT(7)  /* Multicast Packet */
-#define FIFO_CFG5_BC           BIT(8)  /* Broadcast Packet */
-#define FIFO_CFG5_DR           BIT(9)  /* Dribble */
-#define FIFO_CFG5_CF           BIT(10) /* Control Frame */
-#define FIFO_CFG5_PF           BIT(11) /* Pause Frame */
-#define FIFO_CFG5_UO           BIT(12) /* Unsupported Opcode */
-#define FIFO_CFG5_VT           BIT(13) /* VLAN tag detected */
-#define FIFO_CFG5_LE           BIT(14) /* Long Event */
-#define FIFO_CFG5_FT           BIT(15) /* Frame Truncated */
-#define FIFO_CFG5_16           BIT(16) /* unknown */
-#define FIFO_CFG5_17           BIT(17) /* unknown */
+#define FIFO_CFG5_CR           BIT(4)  /* CRC error */
+#define FIFO_CFG5_LM           BIT(5)  /* Length Mismatch */
+#define FIFO_CFG5_LO           BIT(6)  /* Length out of range */
+#define FIFO_CFG5_OK           BIT(7)  /* Packet is OK */
+#define FIFO_CFG5_MC           BIT(8)  /* Multicast Packet */
+#define FIFO_CFG5_BC           BIT(9)  /* Broadcast Packet */
+#define FIFO_CFG5_DR           BIT(10) /* Dribble */
+#define FIFO_CFG5_CF           BIT(11) /* Control Frame */
+#define FIFO_CFG5_PF           BIT(12) /* Pause Frame */
+#define FIFO_CFG5_UO           BIT(13) /* Unsupported Opcode */
+#define FIFO_CFG5_VT           BIT(14) /* VLAN tag detected */
+#define FIFO_CFG5_LE           BIT(15) /* Long Event */
+#define FIFO_CFG5_FT           BIT(16) /* Frame Truncated */
+#define FIFO_CFG5_UC           BIT(17) /* Unicast Packet */
 #define FIFO_CFG5_SF           BIT(18) /* Short Frame */
 #define FIFO_CFG5_BM           BIT(19) /* Byte Mode */
 

diff --git a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
index 8f95210e0f8c370e23654603177a7d919056b087..8a5cd3bcde97ef6a4c79cd2952f044bb98d16b37 100644 (file)
--- a/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
+++ b/target/linux/ath79/files/drivers/net/ethernet/atheros/ag71xx/ag71xx_main.c
@@ -407,11 +407,11 @@ static void ag71xx_dma_reset(struct ag71xx *ag)
                         FIFO_CFG4_VT)
 
 #define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
-                        FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
-                        FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
-                        FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
-                        FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
-                        FIFO_CFG5_17 | FIFO_CFG5_SF)
+                        FIFO_CFG5_CE | FIFO_CFG5_LM | FIFO_CFG5_LO | \
+                        FIFO_CFG5_OK | FIFO_CFG5_MC | FIFO_CFG5_BC | \
+                        FIFO_CFG5_DR | FIFO_CFG5_CF | FIFO_CFG5_UO | \
+                        FIFO_CFG5_VT | FIFO_CFG5_LE | FIFO_CFG5_FT | \
+                        FIFO_CFG5_UC | FIFO_CFG5_SF)
 
 static void ag71xx_hw_stop(struct ag71xx *ag)
 {