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ar71xx: ag71xx: use base address value directly from the source
[openwrt/staging/chunkeey.git] / target / linux / ar71xx / files / drivers / net / ethernet / atheros / ag71xx / ag71xx_ar7240.c
1 /*
2 * Driver for the built-in ethernet switch of the Atheros AR7240 SoC
3 * Copyright (c) 2010 Gabor Juhos <juhosg@openwrt.org>
4 * Copyright (c) 2010 Felix Fietkau <nbd@nbd.name>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 */
11
12 #include <linux/etherdevice.h>
13 #include <linux/list.h>
14 #include <linux/netdevice.h>
15 #include <linux/phy.h>
16 #include <linux/mii.h>
17 #include <linux/bitops.h>
18 #include <linux/switch.h>
19 #include "ag71xx.h"
20
21 #define BITM(_count) (BIT(_count) - 1)
22 #define BITS(_shift, _count) (BITM(_count) << _shift)
23
24 #define AR7240_REG_MASK_CTRL 0x00
25 #define AR7240_MASK_CTRL_REVISION_M BITM(8)
26 #define AR7240_MASK_CTRL_VERSION_M BITM(8)
27 #define AR7240_MASK_CTRL_VERSION_S 8
28 #define AR7240_MASK_CTRL_VERSION_AR7240 0x01
29 #define AR7240_MASK_CTRL_VERSION_AR934X 0x02
30 #define AR7240_MASK_CTRL_SOFT_RESET BIT(31)
31
32 #define AR7240_REG_MAC_ADDR0 0x20
33 #define AR7240_REG_MAC_ADDR1 0x24
34
35 #define AR7240_REG_FLOOD_MASK 0x2c
36 #define AR7240_FLOOD_MASK_BROAD_TO_CPU BIT(26)
37
38 #define AR7240_REG_GLOBAL_CTRL 0x30
39 #define AR7240_GLOBAL_CTRL_MTU_M BITM(11)
40 #define AR9340_GLOBAL_CTRL_MTU_M BITM(14)
41
42 #define AR7240_REG_VTU 0x0040
43 #define AR7240_VTU_OP BITM(3)
44 #define AR7240_VTU_OP_NOOP 0x0
45 #define AR7240_VTU_OP_FLUSH 0x1
46 #define AR7240_VTU_OP_LOAD 0x2
47 #define AR7240_VTU_OP_PURGE 0x3
48 #define AR7240_VTU_OP_REMOVE_PORT 0x4
49 #define AR7240_VTU_ACTIVE BIT(3)
50 #define AR7240_VTU_FULL BIT(4)
51 #define AR7240_VTU_PORT BITS(8, 4)
52 #define AR7240_VTU_PORT_S 8
53 #define AR7240_VTU_VID BITS(16, 12)
54 #define AR7240_VTU_VID_S 16
55 #define AR7240_VTU_PRIO BITS(28, 3)
56 #define AR7240_VTU_PRIO_S 28
57 #define AR7240_VTU_PRIO_EN BIT(31)
58
59 #define AR7240_REG_VTU_DATA 0x0044
60 #define AR7240_VTUDATA_MEMBER BITS(0, 10)
61 #define AR7240_VTUDATA_VALID BIT(11)
62
63 #define AR7240_REG_ATU 0x50
64 #define AR7240_ATU_FLUSH_ALL 0x1
65
66 #define AR7240_REG_AT_CTRL 0x5c
67 #define AR7240_AT_CTRL_AGE_TIME BITS(0, 15)
68 #define AR7240_AT_CTRL_AGE_EN BIT(17)
69 #define AR7240_AT_CTRL_LEARN_CHANGE BIT(18)
70 #define AR7240_AT_CTRL_RESERVED BIT(19)
71 #define AR7240_AT_CTRL_ARP_EN BIT(20)
72
73 #define AR7240_REG_TAG_PRIORITY 0x70
74
75 #define AR7240_REG_SERVICE_TAG 0x74
76 #define AR7240_SERVICE_TAG_M BITM(16)
77
78 #define AR7240_REG_CPU_PORT 0x78
79 #define AR7240_MIRROR_PORT_S 4
80 #define AR7240_MIRROR_PORT_M BITM(4)
81 #define AR7240_CPU_PORT_EN BIT(8)
82
83 #define AR7240_REG_MIB_FUNCTION0 0x80
84 #define AR7240_MIB_TIMER_M BITM(16)
85 #define AR7240_MIB_AT_HALF_EN BIT(16)
86 #define AR7240_MIB_BUSY BIT(17)
87 #define AR7240_MIB_FUNC_S 24
88 #define AR7240_MIB_FUNC_M BITM(3)
89 #define AR7240_MIB_FUNC_NO_OP 0x0
90 #define AR7240_MIB_FUNC_FLUSH 0x1
91 #define AR7240_MIB_FUNC_CAPTURE 0x3
92
93 #define AR7240_REG_MDIO_CTRL 0x98
94 #define AR7240_MDIO_CTRL_DATA_M BITM(16)
95 #define AR7240_MDIO_CTRL_REG_ADDR_S 16
96 #define AR7240_MDIO_CTRL_PHY_ADDR_S 21
97 #define AR7240_MDIO_CTRL_CMD_WRITE 0
98 #define AR7240_MDIO_CTRL_CMD_READ BIT(27)
99 #define AR7240_MDIO_CTRL_MASTER_EN BIT(30)
100 #define AR7240_MDIO_CTRL_BUSY BIT(31)
101
102 #define AR7240_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
103
104 #define AR7240_REG_PORT_STATUS(_port) (AR7240_REG_PORT_BASE((_port)) + 0x00)
105 #define AR7240_PORT_STATUS_SPEED_S 0
106 #define AR7240_PORT_STATUS_SPEED_M BITM(2)
107 #define AR7240_PORT_STATUS_SPEED_10 0
108 #define AR7240_PORT_STATUS_SPEED_100 1
109 #define AR7240_PORT_STATUS_SPEED_1000 2
110 #define AR7240_PORT_STATUS_TXMAC BIT(2)
111 #define AR7240_PORT_STATUS_RXMAC BIT(3)
112 #define AR7240_PORT_STATUS_TXFLOW BIT(4)
113 #define AR7240_PORT_STATUS_RXFLOW BIT(5)
114 #define AR7240_PORT_STATUS_DUPLEX BIT(6)
115 #define AR7240_PORT_STATUS_LINK_UP BIT(8)
116 #define AR7240_PORT_STATUS_LINK_AUTO BIT(9)
117 #define AR7240_PORT_STATUS_LINK_PAUSE BIT(10)
118
119 #define AR7240_REG_PORT_CTRL(_port) (AR7240_REG_PORT_BASE((_port)) + 0x04)
120 #define AR7240_PORT_CTRL_STATE_M BITM(3)
121 #define AR7240_PORT_CTRL_STATE_DISABLED 0
122 #define AR7240_PORT_CTRL_STATE_BLOCK 1
123 #define AR7240_PORT_CTRL_STATE_LISTEN 2
124 #define AR7240_PORT_CTRL_STATE_LEARN 3
125 #define AR7240_PORT_CTRL_STATE_FORWARD 4
126 #define AR7240_PORT_CTRL_LEARN_LOCK BIT(7)
127 #define AR7240_PORT_CTRL_VLAN_MODE_S 8
128 #define AR7240_PORT_CTRL_VLAN_MODE_KEEP 0
129 #define AR7240_PORT_CTRL_VLAN_MODE_STRIP 1
130 #define AR7240_PORT_CTRL_VLAN_MODE_ADD 2
131 #define AR7240_PORT_CTRL_VLAN_MODE_DOUBLE_TAG 3
132 #define AR7240_PORT_CTRL_IGMP_SNOOP BIT(10)
133 #define AR7240_PORT_CTRL_HEADER BIT(11)
134 #define AR7240_PORT_CTRL_MAC_LOOP BIT(12)
135 #define AR7240_PORT_CTRL_SINGLE_VLAN BIT(13)
136 #define AR7240_PORT_CTRL_LEARN BIT(14)
137 #define AR7240_PORT_CTRL_DOUBLE_TAG BIT(15)
138 #define AR7240_PORT_CTRL_MIRROR_TX BIT(16)
139 #define AR7240_PORT_CTRL_MIRROR_RX BIT(17)
140
141 #define AR7240_REG_PORT_VLAN(_port) (AR7240_REG_PORT_BASE((_port)) + 0x08)
142
143 #define AR7240_PORT_VLAN_DEFAULT_ID_S 0
144 #define AR7240_PORT_VLAN_DEST_PORTS_S 16
145 #define AR7240_PORT_VLAN_MODE_S 30
146 #define AR7240_PORT_VLAN_MODE_PORT_ONLY 0
147 #define AR7240_PORT_VLAN_MODE_PORT_FALLBACK 1
148 #define AR7240_PORT_VLAN_MODE_VLAN_ONLY 2
149 #define AR7240_PORT_VLAN_MODE_SECURE 3
150
151
152 #define AR7240_REG_STATS_BASE(_port) (0x20000 + (_port) * 0x100)
153
154 #define AR7240_STATS_RXBROAD 0x00
155 #define AR7240_STATS_RXPAUSE 0x04
156 #define AR7240_STATS_RXMULTI 0x08
157 #define AR7240_STATS_RXFCSERR 0x0c
158 #define AR7240_STATS_RXALIGNERR 0x10
159 #define AR7240_STATS_RXRUNT 0x14
160 #define AR7240_STATS_RXFRAGMENT 0x18
161 #define AR7240_STATS_RX64BYTE 0x1c
162 #define AR7240_STATS_RX128BYTE 0x20
163 #define AR7240_STATS_RX256BYTE 0x24
164 #define AR7240_STATS_RX512BYTE 0x28
165 #define AR7240_STATS_RX1024BYTE 0x2c
166 #define AR7240_STATS_RX1518BYTE 0x30
167 #define AR7240_STATS_RXMAXBYTE 0x34
168 #define AR7240_STATS_RXTOOLONG 0x38
169 #define AR7240_STATS_RXGOODBYTE 0x3c
170 #define AR7240_STATS_RXBADBYTE 0x44
171 #define AR7240_STATS_RXOVERFLOW 0x4c
172 #define AR7240_STATS_FILTERED 0x50
173 #define AR7240_STATS_TXBROAD 0x54
174 #define AR7240_STATS_TXPAUSE 0x58
175 #define AR7240_STATS_TXMULTI 0x5c
176 #define AR7240_STATS_TXUNDERRUN 0x60
177 #define AR7240_STATS_TX64BYTE 0x64
178 #define AR7240_STATS_TX128BYTE 0x68
179 #define AR7240_STATS_TX256BYTE 0x6c
180 #define AR7240_STATS_TX512BYTE 0x70
181 #define AR7240_STATS_TX1024BYTE 0x74
182 #define AR7240_STATS_TX1518BYTE 0x78
183 #define AR7240_STATS_TXMAXBYTE 0x7c
184 #define AR7240_STATS_TXOVERSIZE 0x80
185 #define AR7240_STATS_TXBYTE 0x84
186 #define AR7240_STATS_TXCOLLISION 0x8c
187 #define AR7240_STATS_TXABORTCOL 0x90
188 #define AR7240_STATS_TXMULTICOL 0x94
189 #define AR7240_STATS_TXSINGLECOL 0x98
190 #define AR7240_STATS_TXEXCDEFER 0x9c
191 #define AR7240_STATS_TXDEFER 0xa0
192 #define AR7240_STATS_TXLATECOL 0xa4
193
194 #define AR7240_PORT_CPU 0
195 #define AR7240_NUM_PORTS 6
196 #define AR7240_NUM_PHYS 5
197
198 #define AR7240_PHY_ID1 0x004d
199 #define AR7240_PHY_ID2 0xd041
200
201 #define AR934X_PHY_ID1 0x004d
202 #define AR934X_PHY_ID2 0xd042
203
204 #define AR7240_MAX_VLANS 16
205
206 #define AR934X_REG_OPER_MODE0 0x04
207 #define AR934X_OPER_MODE0_MAC_GMII_EN BIT(6)
208 #define AR934X_OPER_MODE0_PHY_MII_EN BIT(10)
209
210 #define AR934X_REG_OPER_MODE1 0x08
211 #define AR934X_REG_OPER_MODE1_PHY4_MII_EN BIT(28)
212
213 #define AR934X_REG_FLOOD_MASK 0x2c
214 #define AR934X_FLOOD_MASK_MC_DP(_p) BIT(16 + (_p))
215 #define AR934X_FLOOD_MASK_BC_DP(_p) BIT(25 + (_p))
216
217 #define AR934X_REG_QM_CTRL 0x3c
218 #define AR934X_QM_CTRL_ARP_EN BIT(15)
219
220 #define AR934X_REG_AT_CTRL 0x5c
221 #define AR934X_AT_CTRL_AGE_TIME BITS(0, 15)
222 #define AR934X_AT_CTRL_AGE_EN BIT(17)
223 #define AR934X_AT_CTRL_LEARN_CHANGE BIT(18)
224
225 #define AR934X_MIB_ENABLE BIT(30)
226
227 #define AR934X_REG_PORT_BASE(_port) (0x100 + (_port) * 0x100)
228
229 #define AR934X_REG_PORT_VLAN1(_port) (AR934X_REG_PORT_BASE((_port)) + 0x08)
230 #define AR934X_PORT_VLAN1_DEFAULT_SVID_S 0
231 #define AR934X_PORT_VLAN1_FORCE_DEFAULT_VID_EN BIT(12)
232 #define AR934X_PORT_VLAN1_PORT_TLS_MODE BIT(13)
233 #define AR934X_PORT_VLAN1_PORT_VLAN_PROP_EN BIT(14)
234 #define AR934X_PORT_VLAN1_PORT_CLONE_EN BIT(15)
235 #define AR934X_PORT_VLAN1_DEFAULT_CVID_S 16
236 #define AR934X_PORT_VLAN1_FORCE_PORT_VLAN_EN BIT(28)
237 #define AR934X_PORT_VLAN1_ING_PORT_PRI_S 29
238
239 #define AR934X_REG_PORT_VLAN2(_port) (AR934X_REG_PORT_BASE((_port)) + 0x0c)
240 #define AR934X_PORT_VLAN2_PORT_VID_MEM_S 16
241 #define AR934X_PORT_VLAN2_8021Q_MODE_S 30
242 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_ONLY 0
243 #define AR934X_PORT_VLAN2_8021Q_MODE_PORT_FALLBACK 1
244 #define AR934X_PORT_VLAN2_8021Q_MODE_VLAN_ONLY 2
245 #define AR934X_PORT_VLAN2_8021Q_MODE_SECURE 3
246
247 #define sw_to_ar7240(_dev) container_of(_dev, struct ar7240sw, swdev)
248
249 struct ar7240sw_port_stat {
250 unsigned long rx_broadcast;
251 unsigned long rx_pause;
252 unsigned long rx_multicast;
253 unsigned long rx_fcs_error;
254 unsigned long rx_align_error;
255 unsigned long rx_runt;
256 unsigned long rx_fragments;
257 unsigned long rx_64byte;
258 unsigned long rx_128byte;
259 unsigned long rx_256byte;
260 unsigned long rx_512byte;
261 unsigned long rx_1024byte;
262 unsigned long rx_1518byte;
263 unsigned long rx_maxbyte;
264 unsigned long rx_toolong;
265 unsigned long rx_good_byte;
266 unsigned long rx_bad_byte;
267 unsigned long rx_overflow;
268 unsigned long filtered;
269
270 unsigned long tx_broadcast;
271 unsigned long tx_pause;
272 unsigned long tx_multicast;
273 unsigned long tx_underrun;
274 unsigned long tx_64byte;
275 unsigned long tx_128byte;
276 unsigned long tx_256byte;
277 unsigned long tx_512byte;
278 unsigned long tx_1024byte;
279 unsigned long tx_1518byte;
280 unsigned long tx_maxbyte;
281 unsigned long tx_oversize;
282 unsigned long tx_byte;
283 unsigned long tx_collision;
284 unsigned long tx_abortcol;
285 unsigned long tx_multicol;
286 unsigned long tx_singlecol;
287 unsigned long tx_excdefer;
288 unsigned long tx_defer;
289 unsigned long tx_xlatecol;
290 };
291
292 struct ar7240sw {
293 struct mii_bus *mii_bus;
294 struct ag71xx_switch_platform_data *swdata;
295 struct switch_dev swdev;
296 int num_ports;
297 u8 ver;
298 bool vlan;
299 u16 vlan_id[AR7240_MAX_VLANS];
300 u8 vlan_table[AR7240_MAX_VLANS];
301 u8 vlan_tagged;
302 u16 pvid[AR7240_NUM_PORTS];
303 char buf[80];
304
305 rwlock_t stats_lock;
306 struct ar7240sw_port_stat port_stats[AR7240_NUM_PORTS];
307 };
308
309 struct ar7240sw_hw_stat {
310 char string[ETH_GSTRING_LEN];
311 int sizeof_stat;
312 int reg;
313 };
314
315 static DEFINE_MUTEX(reg_mutex);
316
317 static inline int sw_is_ar7240(struct ar7240sw *as)
318 {
319 return as->ver == AR7240_MASK_CTRL_VERSION_AR7240;
320 }
321
322 static inline int sw_is_ar934x(struct ar7240sw *as)
323 {
324 return as->ver == AR7240_MASK_CTRL_VERSION_AR934X;
325 }
326
327 static inline u32 ar7240sw_port_mask(struct ar7240sw *as, int port)
328 {
329 return BIT(port);
330 }
331
332 static inline u32 ar7240sw_port_mask_all(struct ar7240sw *as)
333 {
334 return BIT(as->swdev.ports) - 1;
335 }
336
337 static inline u32 ar7240sw_port_mask_but(struct ar7240sw *as, int port)
338 {
339 return ar7240sw_port_mask_all(as) & ~BIT(port);
340 }
341
342 static inline u16 mk_phy_addr(u32 reg)
343 {
344 return 0x17 & ((reg >> 4) | 0x10);
345 }
346
347 static inline u16 mk_phy_reg(u32 reg)
348 {
349 return (reg << 1) & 0x1e;
350 }
351
352 static inline u16 mk_high_addr(u32 reg)
353 {
354 return (reg >> 7) & 0x1ff;
355 }
356
357 static u32 __ar7240sw_reg_read(struct mii_bus *mii, u32 reg)
358 {
359 unsigned long flags;
360 u16 phy_addr;
361 u16 phy_reg;
362 u32 hi, lo;
363
364 reg = (reg & 0xfffffffc) >> 2;
365 phy_addr = mk_phy_addr(reg);
366 phy_reg = mk_phy_reg(reg);
367
368 local_irq_save(flags);
369 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
370 lo = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg);
371 hi = (u32) ag71xx_mdio_mii_read(mii->priv, phy_addr, phy_reg + 1);
372 local_irq_restore(flags);
373
374 return (hi << 16) | lo;
375 }
376
377 static void __ar7240sw_reg_write(struct mii_bus *mii, u32 reg, u32 val)
378 {
379 unsigned long flags;
380 u16 phy_addr;
381 u16 phy_reg;
382
383 reg = (reg & 0xfffffffc) >> 2;
384 phy_addr = mk_phy_addr(reg);
385 phy_reg = mk_phy_reg(reg);
386
387 local_irq_save(flags);
388 ag71xx_mdio_mii_write(mii->priv, 0x1f, 0x10, mk_high_addr(reg));
389 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg + 1, (val >> 16));
390 ag71xx_mdio_mii_write(mii->priv, phy_addr, phy_reg, (val & 0xffff));
391 local_irq_restore(flags);
392 }
393
394 static u32 ar7240sw_reg_read(struct mii_bus *mii, u32 reg_addr)
395 {
396 u32 ret;
397
398 mutex_lock(&reg_mutex);
399 ret = __ar7240sw_reg_read(mii, reg_addr);
400 mutex_unlock(&reg_mutex);
401
402 return ret;
403 }
404
405 static void ar7240sw_reg_write(struct mii_bus *mii, u32 reg_addr, u32 reg_val)
406 {
407 mutex_lock(&reg_mutex);
408 __ar7240sw_reg_write(mii, reg_addr, reg_val);
409 mutex_unlock(&reg_mutex);
410 }
411
412 static u32 ar7240sw_reg_rmw(struct mii_bus *mii, u32 reg, u32 mask, u32 val)
413 {
414 u32 t;
415
416 mutex_lock(&reg_mutex);
417 t = __ar7240sw_reg_read(mii, reg);
418 t &= ~mask;
419 t |= val;
420 __ar7240sw_reg_write(mii, reg, t);
421 mutex_unlock(&reg_mutex);
422
423 return t;
424 }
425
426 static void ar7240sw_reg_set(struct mii_bus *mii, u32 reg, u32 val)
427 {
428 u32 t;
429
430 mutex_lock(&reg_mutex);
431 t = __ar7240sw_reg_read(mii, reg);
432 t |= val;
433 __ar7240sw_reg_write(mii, reg, t);
434 mutex_unlock(&reg_mutex);
435 }
436
437 static int __ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
438 unsigned timeout)
439 {
440 int i;
441
442 for (i = 0; i < timeout; i++) {
443 u32 t;
444
445 t = __ar7240sw_reg_read(mii, reg);
446 if ((t & mask) == val)
447 return 0;
448
449 usleep_range(1000, 2000);
450 }
451
452 return -ETIMEDOUT;
453 }
454
455 static int ar7240sw_reg_wait(struct mii_bus *mii, u32 reg, u32 mask, u32 val,
456 unsigned timeout)
457 {
458 int ret;
459
460 mutex_lock(&reg_mutex);
461 ret = __ar7240sw_reg_wait(mii, reg, mask, val, timeout);
462 mutex_unlock(&reg_mutex);
463 return ret;
464 }
465
466 u16 ar7240sw_phy_read(struct mii_bus *mii, unsigned phy_addr,
467 unsigned reg_addr)
468 {
469 u32 t, val = 0xffff;
470 int err;
471
472 if (phy_addr >= AR7240_NUM_PHYS)
473 return 0xffff;
474
475 mutex_lock(&reg_mutex);
476 t = (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
477 (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
478 AR7240_MDIO_CTRL_MASTER_EN |
479 AR7240_MDIO_CTRL_BUSY |
480 AR7240_MDIO_CTRL_CMD_READ;
481
482 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
483 err = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
484 AR7240_MDIO_CTRL_BUSY, 0, 5);
485 if (!err)
486 val = __ar7240sw_reg_read(mii, AR7240_REG_MDIO_CTRL);
487 mutex_unlock(&reg_mutex);
488
489 return val & AR7240_MDIO_CTRL_DATA_M;
490 }
491
492 int ar7240sw_phy_write(struct mii_bus *mii, unsigned phy_addr,
493 unsigned reg_addr, u16 reg_val)
494 {
495 u32 t;
496 int ret;
497
498 if (phy_addr >= AR7240_NUM_PHYS)
499 return -EINVAL;
500
501 mutex_lock(&reg_mutex);
502 t = (phy_addr << AR7240_MDIO_CTRL_PHY_ADDR_S) |
503 (reg_addr << AR7240_MDIO_CTRL_REG_ADDR_S) |
504 AR7240_MDIO_CTRL_MASTER_EN |
505 AR7240_MDIO_CTRL_BUSY |
506 AR7240_MDIO_CTRL_CMD_WRITE |
507 reg_val;
508
509 __ar7240sw_reg_write(mii, AR7240_REG_MDIO_CTRL, t);
510 ret = __ar7240sw_reg_wait(mii, AR7240_REG_MDIO_CTRL,
511 AR7240_MDIO_CTRL_BUSY, 0, 5);
512 mutex_unlock(&reg_mutex);
513
514 return ret;
515 }
516
517 static int ar7240sw_capture_stats(struct ar7240sw *as)
518 {
519 struct mii_bus *mii = as->mii_bus;
520 int port;
521 int ret;
522
523 write_lock(&as->stats_lock);
524
525 /* Capture the hardware statistics for all ports */
526 ar7240sw_reg_rmw(mii, AR7240_REG_MIB_FUNCTION0,
527 (AR7240_MIB_FUNC_M << AR7240_MIB_FUNC_S),
528 (AR7240_MIB_FUNC_CAPTURE << AR7240_MIB_FUNC_S));
529
530 /* Wait for the capturing to complete. */
531 ret = ar7240sw_reg_wait(mii, AR7240_REG_MIB_FUNCTION0,
532 AR7240_MIB_BUSY, 0, 10);
533
534 if (ret)
535 goto unlock;
536
537 for (port = 0; port < AR7240_NUM_PORTS; port++) {
538 unsigned int base;
539 struct ar7240sw_port_stat *stats;
540
541 base = AR7240_REG_STATS_BASE(port);
542 stats = &as->port_stats[port];
543
544 #define READ_STAT(_r) ar7240sw_reg_read(mii, base + AR7240_STATS_ ## _r)
545
546 stats->rx_good_byte += READ_STAT(RXGOODBYTE);
547 stats->tx_byte += READ_STAT(TXBYTE);
548
549 #undef READ_STAT
550 }
551
552 ret = 0;
553
554 unlock:
555 write_unlock(&as->stats_lock);
556 return ret;
557 }
558
559 static void ar7240sw_disable_port(struct ar7240sw *as, unsigned port)
560 {
561 ar7240sw_reg_write(as->mii_bus, AR7240_REG_PORT_CTRL(port),
562 AR7240_PORT_CTRL_STATE_DISABLED);
563 }
564
565 static void ar7240sw_setup(struct ar7240sw *as)
566 {
567 struct mii_bus *mii = as->mii_bus;
568
569 /* Enable CPU port, and disable mirror port */
570 ar7240sw_reg_write(mii, AR7240_REG_CPU_PORT,
571 AR7240_CPU_PORT_EN |
572 (15 << AR7240_MIRROR_PORT_S));
573
574 /* Setup TAG priority mapping */
575 ar7240sw_reg_write(mii, AR7240_REG_TAG_PRIORITY, 0xfa50);
576
577 if (sw_is_ar934x(as)) {
578 /* Enable aging, MAC replacing */
579 ar7240sw_reg_write(mii, AR934X_REG_AT_CTRL,
580 0x2b /* 5 min age time */ |
581 AR934X_AT_CTRL_AGE_EN |
582 AR934X_AT_CTRL_LEARN_CHANGE);
583 /* Enable ARP frame acknowledge */
584 ar7240sw_reg_set(mii, AR934X_REG_QM_CTRL,
585 AR934X_QM_CTRL_ARP_EN);
586 /* Enable Broadcast/Multicast frames transmitted to the CPU */
587 ar7240sw_reg_set(mii, AR934X_REG_FLOOD_MASK,
588 AR934X_FLOOD_MASK_BC_DP(0) |
589 AR934X_FLOOD_MASK_MC_DP(0));
590
591 /* setup MTU */
592 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL,
593 AR9340_GLOBAL_CTRL_MTU_M,
594 AR9340_GLOBAL_CTRL_MTU_M);
595
596 /* Enable MIB counters */
597 ar7240sw_reg_set(mii, AR7240_REG_MIB_FUNCTION0,
598 AR934X_MIB_ENABLE);
599
600 } else {
601 /* Enable ARP frame acknowledge, aging, MAC replacing */
602 ar7240sw_reg_write(mii, AR7240_REG_AT_CTRL,
603 AR7240_AT_CTRL_RESERVED |
604 0x2b /* 5 min age time */ |
605 AR7240_AT_CTRL_AGE_EN |
606 AR7240_AT_CTRL_ARP_EN |
607 AR7240_AT_CTRL_LEARN_CHANGE);
608 /* Enable Broadcast frames transmitted to the CPU */
609 ar7240sw_reg_set(mii, AR7240_REG_FLOOD_MASK,
610 AR7240_FLOOD_MASK_BROAD_TO_CPU);
611
612 /* setup MTU */
613 ar7240sw_reg_rmw(mii, AR7240_REG_GLOBAL_CTRL,
614 AR7240_GLOBAL_CTRL_MTU_M,
615 AR7240_GLOBAL_CTRL_MTU_M);
616 }
617
618 /* setup Service TAG */
619 ar7240sw_reg_rmw(mii, AR7240_REG_SERVICE_TAG, AR7240_SERVICE_TAG_M, 0);
620 }
621
622 /* inspired by phy_poll_reset in drivers/net/phy/phy_device.c */
623 static int
624 ar7240sw_phy_poll_reset(struct mii_bus *bus)
625 {
626 const unsigned int sleep_msecs = 20;
627 int ret, elapsed, i;
628
629 for (elapsed = sleep_msecs; elapsed <= 600;
630 elapsed += sleep_msecs) {
631 msleep(sleep_msecs);
632 for (i = 0; i < AR7240_NUM_PHYS; i++) {
633 ret = ar7240sw_phy_read(bus, i, MII_BMCR);
634 if (ret < 0)
635 return ret;
636 if (ret & BMCR_RESET)
637 break;
638 if (i == AR7240_NUM_PHYS - 1) {
639 usleep_range(1000, 2000);
640 return 0;
641 }
642 }
643 }
644 return -ETIMEDOUT;
645 }
646
647 static int ar7240sw_reset(struct ar7240sw *as)
648 {
649 struct mii_bus *mii = as->mii_bus;
650 int ret;
651 int i;
652
653 /* Set all ports to disabled state. */
654 for (i = 0; i < AR7240_NUM_PORTS; i++)
655 ar7240sw_disable_port(as, i);
656
657 /* Wait for transmit queues to drain. */
658 usleep_range(2000, 3000);
659
660 /* Reset the switch. */
661 ar7240sw_reg_write(mii, AR7240_REG_MASK_CTRL,
662 AR7240_MASK_CTRL_SOFT_RESET);
663
664 ret = ar7240sw_reg_wait(mii, AR7240_REG_MASK_CTRL,
665 AR7240_MASK_CTRL_SOFT_RESET, 0, 1000);
666
667 /* setup PHYs */
668 for (i = 0; i < AR7240_NUM_PHYS; i++) {
669 ar7240sw_phy_write(mii, i, MII_ADVERTISE,
670 ADVERTISE_ALL | ADVERTISE_PAUSE_CAP |
671 ADVERTISE_PAUSE_ASYM);
672 ar7240sw_phy_write(mii, i, MII_BMCR,
673 BMCR_RESET | BMCR_ANENABLE);
674 }
675 ret = ar7240sw_phy_poll_reset(mii);
676 if (ret)
677 return ret;
678
679 ar7240sw_setup(as);
680 return ret;
681 }
682
683 static void ar7240sw_setup_port(struct ar7240sw *as, unsigned port, u8 portmask)
684 {
685 struct mii_bus *mii = as->mii_bus;
686 u32 ctrl;
687 u32 vid, mode;
688
689 ctrl = AR7240_PORT_CTRL_STATE_FORWARD | AR7240_PORT_CTRL_LEARN |
690 AR7240_PORT_CTRL_SINGLE_VLAN;
691
692 if (port == AR7240_PORT_CPU) {
693 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
694 AR7240_PORT_STATUS_SPEED_1000 |
695 AR7240_PORT_STATUS_TXFLOW |
696 AR7240_PORT_STATUS_RXFLOW |
697 AR7240_PORT_STATUS_TXMAC |
698 AR7240_PORT_STATUS_RXMAC |
699 AR7240_PORT_STATUS_DUPLEX);
700 } else {
701 ar7240sw_reg_write(mii, AR7240_REG_PORT_STATUS(port),
702 AR7240_PORT_STATUS_LINK_AUTO);
703 }
704
705 /* Set the default VID for this port */
706 if (as->vlan) {
707 vid = as->vlan_id[as->pvid[port]];
708 mode = AR7240_PORT_VLAN_MODE_SECURE;
709 } else {
710 vid = port;
711 mode = AR7240_PORT_VLAN_MODE_PORT_ONLY;
712 }
713
714 if (as->vlan) {
715 if (as->vlan_tagged & BIT(port))
716 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_ADD <<
717 AR7240_PORT_CTRL_VLAN_MODE_S;
718 else
719 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_STRIP <<
720 AR7240_PORT_CTRL_VLAN_MODE_S;
721 } else {
722 ctrl |= AR7240_PORT_CTRL_VLAN_MODE_KEEP <<
723 AR7240_PORT_CTRL_VLAN_MODE_S;
724 }
725
726 if (!portmask) {
727 if (port == AR7240_PORT_CPU)
728 portmask = ar7240sw_port_mask_but(as, AR7240_PORT_CPU);
729 else
730 portmask = ar7240sw_port_mask(as, AR7240_PORT_CPU);
731 }
732
733 /* preserve mirror rx&tx flags */
734 ctrl |= ar7240sw_reg_read(mii, AR7240_REG_PORT_CTRL(port)) &
735 (AR7240_PORT_CTRL_MIRROR_RX | AR7240_PORT_CTRL_MIRROR_TX);
736
737 /* allow the port to talk to all other ports, but exclude its
738 * own ID to prevent frames from being reflected back to the
739 * port that they came from */
740 portmask &= ar7240sw_port_mask_but(as, port);
741
742 ar7240sw_reg_write(mii, AR7240_REG_PORT_CTRL(port), ctrl);
743 if (sw_is_ar934x(as)) {
744 u32 vlan1, vlan2;
745
746 vlan1 = (vid << AR934X_PORT_VLAN1_DEFAULT_CVID_S);
747 vlan2 = (portmask << AR934X_PORT_VLAN2_PORT_VID_MEM_S) |
748 (mode << AR934X_PORT_VLAN2_8021Q_MODE_S);
749 ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN1(port), vlan1);
750 ar7240sw_reg_write(mii, AR934X_REG_PORT_VLAN2(port), vlan2);
751 } else {
752 u32 vlan;
753
754 vlan = vid | (mode << AR7240_PORT_VLAN_MODE_S) |
755 (portmask << AR7240_PORT_VLAN_DEST_PORTS_S);
756
757 ar7240sw_reg_write(mii, AR7240_REG_PORT_VLAN(port), vlan);
758 }
759 }
760
761 static int ar7240_set_addr(struct ar7240sw *as, u8 *addr)
762 {
763 struct mii_bus *mii = as->mii_bus;
764 u32 t;
765
766 t = (addr[4] << 8) | addr[5];
767 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR0, t);
768
769 t = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
770 ar7240sw_reg_write(mii, AR7240_REG_MAC_ADDR1, t);
771
772 return 0;
773 }
774
775 static int
776 ar7240_set_vid(struct switch_dev *dev, const struct switch_attr *attr,
777 struct switch_val *val)
778 {
779 struct ar7240sw *as = sw_to_ar7240(dev);
780 as->vlan_id[val->port_vlan] = val->value.i;
781 return 0;
782 }
783
784 static int
785 ar7240_get_vid(struct switch_dev *dev, const struct switch_attr *attr,
786 struct switch_val *val)
787 {
788 struct ar7240sw *as = sw_to_ar7240(dev);
789 val->value.i = as->vlan_id[val->port_vlan];
790 return 0;
791 }
792
793 static int
794 ar7240_set_pvid(struct switch_dev *dev, int port, int vlan)
795 {
796 struct ar7240sw *as = sw_to_ar7240(dev);
797
798 /* make sure no invalid PVIDs get set */
799
800 if (vlan >= dev->vlans)
801 return -EINVAL;
802
803 as->pvid[port] = vlan;
804 return 0;
805 }
806
807 static int
808 ar7240_get_pvid(struct switch_dev *dev, int port, int *vlan)
809 {
810 struct ar7240sw *as = sw_to_ar7240(dev);
811 *vlan = as->pvid[port];
812 return 0;
813 }
814
815 static int
816 ar7240_get_ports(struct switch_dev *dev, struct switch_val *val)
817 {
818 struct ar7240sw *as = sw_to_ar7240(dev);
819 u8 ports = as->vlan_table[val->port_vlan];
820 int i;
821
822 val->len = 0;
823 for (i = 0; i < as->swdev.ports; i++) {
824 struct switch_port *p;
825
826 if (!(ports & (1 << i)))
827 continue;
828
829 p = &val->value.ports[val->len++];
830 p->id = i;
831 if (as->vlan_tagged & (1 << i))
832 p->flags = (1 << SWITCH_PORT_FLAG_TAGGED);
833 else
834 p->flags = 0;
835 }
836 return 0;
837 }
838
839 static int
840 ar7240_set_ports(struct switch_dev *dev, struct switch_val *val)
841 {
842 struct ar7240sw *as = sw_to_ar7240(dev);
843 u8 *vt = &as->vlan_table[val->port_vlan];
844 int i, j;
845
846 *vt = 0;
847 for (i = 0; i < val->len; i++) {
848 struct switch_port *p = &val->value.ports[i];
849
850 if (p->flags & (1 << SWITCH_PORT_FLAG_TAGGED))
851 as->vlan_tagged |= (1 << p->id);
852 else {
853 as->vlan_tagged &= ~(1 << p->id);
854 as->pvid[p->id] = val->port_vlan;
855
856 /* make sure that an untagged port does not
857 * appear in other vlans */
858 for (j = 0; j < AR7240_MAX_VLANS; j++) {
859 if (j == val->port_vlan)
860 continue;
861 as->vlan_table[j] &= ~(1 << p->id);
862 }
863 }
864
865 *vt |= 1 << p->id;
866 }
867 return 0;
868 }
869
870 static int
871 ar7240_set_vlan(struct switch_dev *dev, const struct switch_attr *attr,
872 struct switch_val *val)
873 {
874 struct ar7240sw *as = sw_to_ar7240(dev);
875 as->vlan = !!val->value.i;
876 return 0;
877 }
878
879 static int
880 ar7240_get_vlan(struct switch_dev *dev, const struct switch_attr *attr,
881 struct switch_val *val)
882 {
883 struct ar7240sw *as = sw_to_ar7240(dev);
884 val->value.i = as->vlan;
885 return 0;
886 }
887
888 static void
889 ar7240_vtu_op(struct ar7240sw *as, u32 op, u32 val)
890 {
891 struct mii_bus *mii = as->mii_bus;
892
893 if (ar7240sw_reg_wait(mii, AR7240_REG_VTU, AR7240_VTU_ACTIVE, 0, 5))
894 return;
895
896 if ((op & AR7240_VTU_OP) == AR7240_VTU_OP_LOAD) {
897 val &= AR7240_VTUDATA_MEMBER;
898 val |= AR7240_VTUDATA_VALID;
899 ar7240sw_reg_write(mii, AR7240_REG_VTU_DATA, val);
900 }
901 op |= AR7240_VTU_ACTIVE;
902 ar7240sw_reg_write(mii, AR7240_REG_VTU, op);
903 }
904
905 static int
906 ar7240_hw_apply(struct switch_dev *dev)
907 {
908 struct ar7240sw *as = sw_to_ar7240(dev);
909 u8 portmask[AR7240_NUM_PORTS];
910 int i, j;
911
912 /* flush all vlan translation unit entries */
913 ar7240_vtu_op(as, AR7240_VTU_OP_FLUSH, 0);
914
915 memset(portmask, 0, sizeof(portmask));
916 if (as->vlan) {
917 /* calculate the port destination masks and load vlans
918 * into the vlan translation unit */
919 for (j = 0; j < AR7240_MAX_VLANS; j++) {
920 u8 vp = as->vlan_table[j];
921
922 if (!vp)
923 continue;
924
925 for (i = 0; i < as->swdev.ports; i++) {
926 u8 mask = (1 << i);
927 if (vp & mask)
928 portmask[i] |= vp & ~mask;
929 }
930
931 ar7240_vtu_op(as,
932 AR7240_VTU_OP_LOAD |
933 (as->vlan_id[j] << AR7240_VTU_VID_S),
934 as->vlan_table[j]);
935 }
936 } else {
937 /* vlan disabled:
938 * isolate all ports, but connect them to the cpu port */
939 for (i = 0; i < as->swdev.ports; i++) {
940 if (i == AR7240_PORT_CPU)
941 continue;
942
943 portmask[i] = 1 << AR7240_PORT_CPU;
944 portmask[AR7240_PORT_CPU] |= (1 << i);
945 }
946 }
947
948 /* update the port destination mask registers and tag settings */
949 for (i = 0; i < as->swdev.ports; i++)
950 ar7240sw_setup_port(as, i, portmask[i]);
951
952 return 0;
953 }
954
955 static int
956 ar7240_reset_switch(struct switch_dev *dev)
957 {
958 struct ar7240sw *as = sw_to_ar7240(dev);
959 ar7240sw_reset(as);
960 return 0;
961 }
962
963 static int
964 ar7240_get_port_link(struct switch_dev *dev, int port,
965 struct switch_port_link *link)
966 {
967 struct ar7240sw *as = sw_to_ar7240(dev);
968 struct mii_bus *mii = as->mii_bus;
969 u32 status;
970
971 if (port >= AR7240_NUM_PORTS)
972 return -EINVAL;
973
974 status = ar7240sw_reg_read(mii, AR7240_REG_PORT_STATUS(port));
975 link->aneg = !!(status & AR7240_PORT_STATUS_LINK_AUTO);
976 if (link->aneg) {
977 link->link = !!(status & AR7240_PORT_STATUS_LINK_UP);
978 if (!link->link)
979 return 0;
980 } else {
981 link->link = true;
982 }
983
984 link->duplex = !!(status & AR7240_PORT_STATUS_DUPLEX);
985 link->tx_flow = !!(status & AR7240_PORT_STATUS_TXFLOW);
986 link->rx_flow = !!(status & AR7240_PORT_STATUS_RXFLOW);
987 switch (status & AR7240_PORT_STATUS_SPEED_M) {
988 case AR7240_PORT_STATUS_SPEED_10:
989 link->speed = SWITCH_PORT_SPEED_10;
990 break;
991 case AR7240_PORT_STATUS_SPEED_100:
992 link->speed = SWITCH_PORT_SPEED_100;
993 break;
994 case AR7240_PORT_STATUS_SPEED_1000:
995 link->speed = SWITCH_PORT_SPEED_1000;
996 break;
997 }
998
999 return 0;
1000 }
1001
1002 static int
1003 ar7240_get_port_stats(struct switch_dev *dev, int port,
1004 struct switch_port_stats *stats)
1005 {
1006 struct ar7240sw *as = sw_to_ar7240(dev);
1007
1008 if (port >= AR7240_NUM_PORTS)
1009 return -EINVAL;
1010
1011 ar7240sw_capture_stats(as);
1012
1013 read_lock(&as->stats_lock);
1014 stats->rx_bytes = as->port_stats[port].rx_good_byte;
1015 stats->tx_bytes = as->port_stats[port].tx_byte;
1016 read_unlock(&as->stats_lock);
1017
1018 return 0;
1019 }
1020
1021 static int
1022 ar7240_set_mirror_monitor_port(struct switch_dev *dev,
1023 const struct switch_attr *attr,
1024 struct switch_val *val)
1025 {
1026 struct ar7240sw *as = sw_to_ar7240(dev);
1027 struct mii_bus *mii = as->mii_bus;
1028
1029 int port = val->value.i;
1030
1031 if (port > 15)
1032 return -EINVAL;
1033
1034 ar7240sw_reg_rmw(mii, AR7240_REG_CPU_PORT,
1035 AR7240_MIRROR_PORT_M << AR7240_MIRROR_PORT_S,
1036 port << AR7240_MIRROR_PORT_S);
1037
1038 return 0;
1039 }
1040
1041 static int
1042 ar7240_get_mirror_monitor_port(struct switch_dev *dev,
1043 const struct switch_attr *attr,
1044 struct switch_val *val)
1045 {
1046 struct ar7240sw *as = sw_to_ar7240(dev);
1047 struct mii_bus *mii = as->mii_bus;
1048
1049 u32 ret;
1050
1051 ret = ar7240sw_reg_read(mii, AR7240_REG_CPU_PORT);
1052 val->value.i = (ret >> AR7240_MIRROR_PORT_S) & AR7240_MIRROR_PORT_M;
1053
1054 return 0;
1055 }
1056
1057 static int
1058 ar7240_set_mirror_rx(struct switch_dev *dev, const struct switch_attr *attr,
1059 struct switch_val *val)
1060 {
1061 struct ar7240sw *as = sw_to_ar7240(dev);
1062 struct mii_bus *mii = as->mii_bus;
1063
1064 int port = val->port_vlan;
1065
1066 if (port >= dev->ports)
1067 return -EINVAL;
1068
1069 if (val && val->value.i == 1)
1070 ar7240sw_reg_set(mii, AR7240_REG_PORT_CTRL(port),
1071 AR7240_PORT_CTRL_MIRROR_RX);
1072 else
1073 ar7240sw_reg_rmw(mii, AR7240_REG_PORT_CTRL(port),
1074 AR7240_PORT_CTRL_MIRROR_RX, 0);
1075
1076 return 0;
1077 }
1078
1079 static int
1080 ar7240_get_mirror_rx(struct switch_dev *dev, const struct switch_attr *attr,
1081 struct switch_val *val)
1082 {
1083 struct ar7240sw *as = sw_to_ar7240(dev);
1084 struct mii_bus *mii = as->mii_bus;
1085
1086 u32 ctrl;
1087
1088 int port = val->port_vlan;
1089
1090 if (port >= dev->ports)
1091 return -EINVAL;
1092
1093 ctrl = ar7240sw_reg_read(mii, AR7240_REG_PORT_CTRL(port));
1094
1095 if ((ctrl & AR7240_PORT_CTRL_MIRROR_RX) == AR7240_PORT_CTRL_MIRROR_RX)
1096 val->value.i = 1;
1097 else
1098 val->value.i = 0;
1099
1100 return 0;
1101 }
1102
1103 static int
1104 ar7240_set_mirror_tx(struct switch_dev *dev, const struct switch_attr *attr,
1105 struct switch_val *val)
1106 {
1107 struct ar7240sw *as = sw_to_ar7240(dev);
1108 struct mii_bus *mii = as->mii_bus;
1109
1110 int port = val->port_vlan;
1111
1112 if (port >= dev->ports)
1113 return -EINVAL;
1114
1115 if (val && val->value.i == 1)
1116 ar7240sw_reg_set(mii, AR7240_REG_PORT_CTRL(port),
1117 AR7240_PORT_CTRL_MIRROR_TX);
1118 else
1119 ar7240sw_reg_rmw(mii, AR7240_REG_PORT_CTRL(port),
1120 AR7240_PORT_CTRL_MIRROR_TX, 0);
1121
1122 return 0;
1123 }
1124
1125 static int
1126 ar7240_get_mirror_tx(struct switch_dev *dev, const struct switch_attr *attr,
1127 struct switch_val *val)
1128 {
1129 struct ar7240sw *as = sw_to_ar7240(dev);
1130 struct mii_bus *mii = as->mii_bus;
1131
1132 u32 ctrl;
1133
1134 int port = val->port_vlan;
1135
1136 if (port >= dev->ports)
1137 return -EINVAL;
1138
1139 ctrl = ar7240sw_reg_read(mii, AR7240_REG_PORT_CTRL(port));
1140
1141 if ((ctrl & AR7240_PORT_CTRL_MIRROR_TX) == AR7240_PORT_CTRL_MIRROR_TX)
1142 val->value.i = 1;
1143 else
1144 val->value.i = 0;
1145
1146 return 0;
1147 }
1148
1149 static struct switch_attr ar7240_globals[] = {
1150 {
1151 .type = SWITCH_TYPE_INT,
1152 .name = "enable_vlan",
1153 .description = "Enable VLAN mode",
1154 .set = ar7240_set_vlan,
1155 .get = ar7240_get_vlan,
1156 .max = 1
1157 },
1158 {
1159 .type = SWITCH_TYPE_INT,
1160 .name = "mirror_monitor_port",
1161 .description = "Mirror monitor port",
1162 .set = ar7240_set_mirror_monitor_port,
1163 .get = ar7240_get_mirror_monitor_port,
1164 .max = 15
1165 },
1166 };
1167
1168 static struct switch_attr ar7240_port[] = {
1169 {
1170 .type = SWITCH_TYPE_INT,
1171 .name = "enable_mirror_rx",
1172 .description = "Enable mirroring of RX packets",
1173 .set = ar7240_set_mirror_rx,
1174 .get = ar7240_get_mirror_rx,
1175 .max = 1
1176 },
1177 {
1178 .type = SWITCH_TYPE_INT,
1179 .name = "enable_mirror_tx",
1180 .description = "Enable mirroring of TX packets",
1181 .set = ar7240_set_mirror_tx,
1182 .get = ar7240_get_mirror_tx,
1183 .max = 1
1184 },
1185 };
1186
1187 static struct switch_attr ar7240_vlan[] = {
1188 {
1189 .type = SWITCH_TYPE_INT,
1190 .name = "vid",
1191 .description = "VLAN ID",
1192 .set = ar7240_set_vid,
1193 .get = ar7240_get_vid,
1194 .max = 4094,
1195 },
1196 };
1197
1198 static const struct switch_dev_ops ar7240_ops = {
1199 .attr_global = {
1200 .attr = ar7240_globals,
1201 .n_attr = ARRAY_SIZE(ar7240_globals),
1202 },
1203 .attr_port = {
1204 .attr = ar7240_port,
1205 .n_attr = ARRAY_SIZE(ar7240_port),
1206 },
1207 .attr_vlan = {
1208 .attr = ar7240_vlan,
1209 .n_attr = ARRAY_SIZE(ar7240_vlan),
1210 },
1211 .get_port_pvid = ar7240_get_pvid,
1212 .set_port_pvid = ar7240_set_pvid,
1213 .get_vlan_ports = ar7240_get_ports,
1214 .set_vlan_ports = ar7240_set_ports,
1215 .apply_config = ar7240_hw_apply,
1216 .reset_switch = ar7240_reset_switch,
1217 .get_port_link = ar7240_get_port_link,
1218 .get_port_stats = ar7240_get_port_stats,
1219 };
1220
1221 static struct ar7240sw *ar7240_probe(struct ag71xx *ag)
1222 {
1223 struct ag71xx_platform_data *pdata = ag71xx_get_pdata(ag);
1224 struct mii_bus *mii = ag->mii_bus;
1225 struct ar7240sw *as;
1226 struct switch_dev *swdev;
1227 u32 ctrl;
1228 u16 phy_id1;
1229 u16 phy_id2;
1230 int i;
1231
1232 phy_id1 = ar7240sw_phy_read(mii, 0, MII_PHYSID1);
1233 phy_id2 = ar7240sw_phy_read(mii, 0, MII_PHYSID2);
1234 if ((phy_id1 != AR7240_PHY_ID1 || phy_id2 != AR7240_PHY_ID2) &&
1235 (phy_id1 != AR934X_PHY_ID1 || phy_id2 != AR934X_PHY_ID2)) {
1236 pr_err("%s: unknown phy id '%04x:%04x'\n",
1237 dev_name(&mii->dev), phy_id1, phy_id2);
1238 return NULL;
1239 }
1240
1241 as = kzalloc(sizeof(*as), GFP_KERNEL);
1242 if (!as)
1243 return NULL;
1244
1245 as->mii_bus = mii;
1246 as->swdata = pdata->switch_data;
1247
1248 swdev = &as->swdev;
1249
1250 ctrl = ar7240sw_reg_read(mii, AR7240_REG_MASK_CTRL);
1251 as->ver = (ctrl >> AR7240_MASK_CTRL_VERSION_S) &
1252 AR7240_MASK_CTRL_VERSION_M;
1253
1254 if (sw_is_ar7240(as)) {
1255 swdev->name = "AR7240/AR9330 built-in switch";
1256 swdev->ports = AR7240_NUM_PORTS - 1;
1257 } else if (sw_is_ar934x(as)) {
1258 swdev->name = "AR934X built-in switch";
1259
1260 if (pdata->phy_if_mode == PHY_INTERFACE_MODE_GMII) {
1261 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
1262 AR934X_OPER_MODE0_MAC_GMII_EN);
1263 } else if (pdata->phy_if_mode == PHY_INTERFACE_MODE_MII) {
1264 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE0,
1265 AR934X_OPER_MODE0_PHY_MII_EN);
1266 } else {
1267 pr_err("%s: invalid PHY interface mode\n",
1268 dev_name(&mii->dev));
1269 goto err_free;
1270 }
1271
1272 if (as->swdata->phy4_mii_en) {
1273 ar7240sw_reg_set(mii, AR934X_REG_OPER_MODE1,
1274 AR934X_REG_OPER_MODE1_PHY4_MII_EN);
1275 swdev->ports = AR7240_NUM_PORTS - 1;
1276 } else {
1277 swdev->ports = AR7240_NUM_PORTS;
1278 }
1279 } else {
1280 pr_err("%s: unsupported chip, ctrl=%08x\n",
1281 dev_name(&mii->dev), ctrl);
1282 goto err_free;
1283 }
1284
1285 swdev->cpu_port = AR7240_PORT_CPU;
1286 swdev->vlans = AR7240_MAX_VLANS;
1287 swdev->ops = &ar7240_ops;
1288
1289 if (register_switch(&as->swdev, ag->dev) < 0)
1290 goto err_free;
1291
1292 pr_info("%s: Found an %s\n", dev_name(&mii->dev), swdev->name);
1293
1294 /* initialize defaults */
1295 for (i = 0; i < AR7240_MAX_VLANS; i++)
1296 as->vlan_id[i] = i;
1297
1298 as->vlan_table[0] = ar7240sw_port_mask_all(as);
1299
1300 return as;
1301
1302 err_free:
1303 kfree(as);
1304 return NULL;
1305 }
1306
1307 static void link_function(struct work_struct *work) {
1308 struct ag71xx *ag = container_of(work, struct ag71xx, link_work.work);
1309 struct ar7240sw *as = ag->phy_priv;
1310 unsigned long flags;
1311 u8 mask;
1312 int i;
1313 int status = 0;
1314
1315 mask = ~as->swdata->phy_poll_mask;
1316 for (i = 0; i < AR7240_NUM_PHYS; i++) {
1317 int link;
1318
1319 if (!(mask & BIT(i)))
1320 continue;
1321
1322 link = ar7240sw_phy_read(ag->mii_bus, i, MII_BMSR);
1323 if (link & BMSR_LSTATUS) {
1324 status = 1;
1325 break;
1326 }
1327 }
1328
1329 spin_lock_irqsave(&ag->lock, flags);
1330 if (status != ag->link) {
1331 ag->link = status;
1332 ag71xx_link_adjust(ag);
1333 }
1334 spin_unlock_irqrestore(&ag->lock, flags);
1335
1336 schedule_delayed_work(&ag->link_work, HZ / 2);
1337 }
1338
1339 void ag71xx_ar7240_start(struct ag71xx *ag)
1340 {
1341 struct ar7240sw *as = ag->phy_priv;
1342
1343 ar7240sw_reset(as);
1344
1345 ag->speed = SPEED_1000;
1346 ag->duplex = 1;
1347
1348 ar7240_set_addr(as, ag->dev->dev_addr);
1349 ar7240_hw_apply(&as->swdev);
1350
1351 schedule_delayed_work(&ag->link_work, HZ / 10);
1352 }
1353
1354 void ag71xx_ar7240_stop(struct ag71xx *ag)
1355 {
1356 cancel_delayed_work_sync(&ag->link_work);
1357 }
1358
1359 int ag71xx_ar7240_init(struct ag71xx *ag)
1360 {
1361 struct ar7240sw *as;
1362
1363 as = ar7240_probe(ag);
1364 if (!as)
1365 return -ENODEV;
1366
1367 ag->phy_priv = as;
1368 ar7240sw_reset(as);
1369
1370 rwlock_init(&as->stats_lock);
1371 INIT_DELAYED_WORK(&ag->link_work, link_function);
1372
1373 return 0;
1374 }
1375
1376 void ag71xx_ar7240_cleanup(struct ag71xx *ag)
1377 {
1378 struct ar7240sw *as = ag->phy_priv;
1379
1380 if (!as)
1381 return;
1382
1383 unregister_switch(&as->swdev);
1384 kfree(as);
1385 ag->phy_priv = NULL;
1386 }
Staging tree of Christian Lamparter