target/linux/bcm27xx/patches-5.10/950-0300-ARM-proc-v7-Force-misalignment-of-early-stmia.patch

   1 From 9e5b2debe12d4e840a7d3ec0cf22b215396ed46e Mon Sep 17 00:00:00 2001
   2 From: Phil Elwell <phil@raspberrypi.com>
   3 Date: Wed, 29 Jul 2020 13:47:55 +0100
   4 Subject: [PATCH] ARM: proc-v7: Force misalignment of early stmia
   5
   6 In an attempt to prevent the problem of CPUn not starting, explicitly
   7 misalign the scratch space used to save registers acros the cache
   8 invalidation.
   9
  10 Notes:
  11 At this stage in the boot process the core is running with its cache
  12 disabled. Before enabling the cache its contents must be explicitly
  13 invalidated, a process that requires quite a few registers that the
  14 caller must preserve. Evidence suggests that something is writing a
  15 block of zeroes over that space at a time when all other cores should
  16 be idle, possibly some kind of write-combiner, and the misalignment is
  17 designed to disrupt any write-coalescing.
  18
  19 In truth, I don't understand why this patch works, and when the failure
  20 is so random it is hard to be certain that this isn't just rolling the
  21 dice again. One interesting test would be to change the "addeq r12, #4"s
  22 to "addeq r12, #0"s determine see if the offset itself is significant or
  23 just the additional code.
  24
  25 See: https://github.com/Hexxeh/rpi-firmware/issues/232
  26
  27 Signed-off-by: Phil Elwell <phil@raspberrypi.com>
  28 ---
  29  arch/arm/mm/proc-v7.S | 6 +++++-
  30  1 file changed, 5 insertions(+), 1 deletion(-)
  31
  32 --- a/arch/arm/mm/proc-v7.S
  33 +++ b/arch/arm/mm/proc-v7.S
  34 @@ -287,6 +287,8 @@ __v7_ca17mp_setup:
  35         mov     r10, #0
  36  1:     adr     r0, __v7_setup_stack_ptr
  37         ldr     r12, [r0]
  38 +       tst     r12, #0x1f
  39 +       addeq   r12, r12, #4
  40         add     r12, r12, r0                    @ the local stack
  41         stmia   r12, {r1-r6, lr}                @ v7_invalidate_l1 touches r0-r6
  42         bl      v7_invalidate_l1
  43 @@ -474,6 +476,8 @@ __v7_setup:
  44         adr     r0, __v7_setup_stack_ptr
  45         ldr     r12, [r0]
  46         add     r12, r12, r0                    @ the local stack
  47 +       tst     r12, #0x1f
  48 +       addeq   r12, r12, #4
  49         stmia   r12, {r1-r6, lr}                @ v7_invalidate_l1 touches r0-r6
  50         bl      v7_invalidate_l1
  51         ldmia   r12, {r1-r6, lr}
  52 @@ -557,7 +561,7 @@ ENDPROC(__v7_setup)
  53         .bss
  54         .align  2
  55  __v7_setup_stack:
  56 -       .space  4 * 7                           @ 7 registers
  57 +       .space  4 * 8                           @ 7 registers + 1 spare
  58
  59         __INITDATA
  60