target/linux/bcm27xx/patches-5.10/950-0565-drm-vc4-Correct-pixel-order-for-DSI0.patch

   1 From 59938610a705283fef63447c7e777781358610e2 Mon Sep 17 00:00:00 2001
   2 From: Dave Stevenson <dave.stevenson@raspberrypi.com>
   3 Date: Thu, 11 Feb 2021 18:37:04 +0000
   4 Subject: [PATCH] drm/vc4: Correct pixel order for DSI0
   5
   6 For slightly unknown reasons, dsi0 takes a different pixel format
   7 to dsi1, and that has to be set in the pixel valve.
   8
   9 Amend the setup accordingly.
  10
  11 Signed-off-by: Dave Stevenson <dave.stevenson@raspberrypi.com>
  12 ---
  13  drivers/gpu/drm/vc4/vc4_crtc.c | 3 ++-
  14  1 file changed, 2 insertions(+), 1 deletion(-)
  15
  16 --- a/drivers/gpu/drm/vc4/vc4_crtc.c
  17 +++ b/drivers/gpu/drm/vc4/vc4_crtc.c
  18 @@ -319,7 +319,8 @@ static void vc4_crtc_config_pv(struct dr
  19         u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
  20         bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
  21                        vc4_encoder->type == VC4_ENCODER_TYPE_DSI1);
  22 -       u32 format = is_dsi ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
  23 +       bool is_dsi1 = vc4_encoder->type == VC4_ENCODER_TYPE_DSI1;
  24 +       u32 format = is_dsi1 ? PV_CONTROL_FORMAT_DSIV_24 : PV_CONTROL_FORMAT_24;
  25         u8 ppc = pv_data->pixels_per_clock;
  26         bool debug_dump_regs = false;
  27