target/linux/brcm2708/patches-4.19/950-0406-ASoC-tlv320aic32x4-Model-CODEC_CLKIN-in-CCF.patch

   1 From f0192af931c8aea25440c014b9a995a3bf1a5363 Mon Sep 17 00:00:00 2001
   2 From: Annaliese McDermond <nh6z@nh6z.net>
   3 Date: Thu, 21 Mar 2019 17:58:46 -0700
   4 Subject: [PATCH 406/703] ASoC: tlv320aic32x4: Model CODEC_CLKIN in CCF
   5
   6 commit fd2df3aeafa4b4cc468d58e147e0822967034b71 upstream.
   7
   8 Model and manage codec clock input as a component in the Core
   9 Clock Framework.  This should allow us to do some more complex
  10 clock management and power control.  Also, some of the
  11 on-board chip clocks can be exposed to the outside, and this
  12 change will make those clocks easier to consume by other
  13 parts of the kernel.
  14
  15 Signed-off-by: Annaliese McDermond <nh6z@nh6z.net>
  16 Signed-off-by: Mark Brown <broonie@kernel.org>
  17 ---
  18  sound/soc/codecs/tlv320aic32x4-clk.c | 34 ++++++++++++++++++++++++++++
  19  sound/soc/codecs/tlv320aic32x4.c     | 18 +++++++++++----
  20  2 files changed, 47 insertions(+), 5 deletions(-)
  21
  22 --- a/sound/soc/codecs/tlv320aic32x4-clk.c
  23 +++ b/sound/soc/codecs/tlv320aic32x4-clk.c
  24 @@ -265,6 +265,30 @@ static const struct clk_ops aic32x4_pll_
  25         .get_parent = clk_aic32x4_pll_get_parent,
  26  };
  27
  28 +static int clk_aic32x4_codec_clkin_set_parent(struct clk_hw *hw, u8 index)
  29 +{
  30 +       struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
  31 +
  32 +       return regmap_update_bits(mux->regmap,
  33 +               AIC32X4_CLKMUX,
  34 +               AIC32X4_CODEC_CLKIN_MASK, index << AIC32X4_CODEC_CLKIN_SHIFT);
  35 +}
  36 +
  37 +static u8 clk_aic32x4_codec_clkin_get_parent(struct clk_hw *hw)
  38 +{
  39 +       struct clk_aic32x4 *mux = to_clk_aic32x4(hw);
  40 +       unsigned int val;
  41 +
  42 +       regmap_read(mux->regmap, AIC32X4_CLKMUX, &val);
  43 +
  44 +       return (val & AIC32X4_CODEC_CLKIN_MASK) >> AIC32X4_CODEC_CLKIN_SHIFT;
  45 +}
  46 +
  47 +static const struct clk_ops aic32x4_codec_clkin_ops = {
  48 +       .set_parent = clk_aic32x4_codec_clkin_set_parent,
  49 +       .get_parent = clk_aic32x4_codec_clkin_get_parent,
  50 +};
  51 +
  52  static struct aic32x4_clkdesc aic32x4_clkdesc_array[] = {
  53         {
  54                 .name = "pll",
  55 @@ -274,6 +298,14 @@ static struct aic32x4_clkdesc aic32x4_cl
  56                 .ops = &aic32x4_pll_ops,
  57                 .reg = 0,
  58         },
  59 +       {
  60 +               .name = "codec_clkin",
  61 +               .parent_names =
  62 +                       (const char *[]) { "mclk", "bclk", "gpio", "pll" },
  63 +               .num_parents = 4,
  64 +               .ops = &aic32x4_codec_clkin_ops,
  65 +               .reg = 0,
  66 +       },
  67  };
  68
  69  static struct clk *aic32x4_register_clk(struct device *dev,
  70 @@ -314,6 +346,8 @@ int aic32x4_register_clocks(struct devic
  71          */
  72         aic32x4_clkdesc_array[0].parent_names =
  73                         (const char* []) { mclk_name, "bclk", "gpio", "din" };
  74 +       aic32x4_clkdesc_array[1].parent_names =
  75 +                       (const char *[]) { mclk_name, "bclk", "gpio", "pll" };
  76
  77         for (i = 0; i < ARRAY_SIZE(aic32x4_clkdesc_array); ++i)
  78                 aic32x4_register_clk(dev, &aic32x4_clkdesc_array[i]);
  79 --- a/sound/soc/codecs/tlv320aic32x4.c
  80 +++ b/sound/soc/codecs/tlv320aic32x4.c
  81 @@ -737,12 +737,9 @@ static int aic32x4_setup_clocks(struct s
  82
  83         aic32x4_set_processing_blocks(component, aic32x4_divs[i].r_block, aic32x4_divs[i].p_block);
  84
  85 -       /* PLL as CODEC_CLKIN */
  86 -       snd_soc_component_update_bits(component, AIC32X4_CLKMUX,
  87 -                       AIC32X4_CODEC_CLKIN_MASK,
  88 -                       AIC32X4_CODEC_CLKIN_PLL << AIC32X4_CODEC_CLKIN_SHIFT);
  89         /* DAC_MOD_CLK as BDIV_CLKIN */
  90 -       snd_soc_component_update_bits(component, AIC32X4_IFACE3, AIC32X4_BDIVCLK_MASK,
  91 +       snd_soc_component_update_bits(component, AIC32X4_IFACE3,
  92 +                               AIC32X4_BDIVCLK_MASK,
  93                                 AIC32X4_DACMOD2BCLK << AIC32X4_BDIVCLK_SHIFT);
  94
  95         /* NDAC divider value */
  96 @@ -989,6 +986,15 @@ static int aic32x4_component_probe(struc
  97  {
  98         struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
  99         u32 tmp_reg;
 100 +       int ret;
 101 +
 102 +       struct clk_bulk_data clocks[] = {
 103 +           { .id = "codec_clkin" },
 104 +       };
 105 +
 106 +       ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
 107 +       if (ret)
 108 +               return ret;
 109
 110         if (gpio_is_valid(aic32x4->rstn_gpio)) {
 111                 ndelay(10);
 112 @@ -1000,6 +1006,8 @@ static int aic32x4_component_probe(struc
 113         if (aic32x4->setup)
 114                 aic32x4_setup_gpios(component);
 115
 116 +       clk_set_parent(clocks[0].clk, clocks[1].clk);
 117 +
 118         /* Power platform configuration */
 119         if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
 120                 snd_soc_component_write(component, AIC32X4_MICBIAS,