target/linux/imx6/patches-4.19/001-ARM-dts-imx-Add-GW5907-board-support.patch

   1 From 125120298dc05bb55a8874f07aa3f4bb6056bfb3 Mon Sep 17 00:00:00 2001
   2 From: Robert Jones <rjones@gateworks.com>
   3 Date: Wed, 8 Jan 2020 07:44:21 -0800
   4 Subject: [PATCH 1/4] ARM: dts: imx: Add GW5907 board support
   5
   6 The Gateworks GW5907 is an IMX6 SoC based single board computer with:
   7  - IMX6Q or IMX6DL
   8  - 32bit DDR3 DRAM
   9  - FEC GbE Phy
  10  - bi-color front-panel LED
  11  - 256MB NAND boot device
  12  - Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
  13  - Digital IO expander (pca9555)
  14  - Joystick 12bit adc (ads1015)
  15
  16 Signed-off-by: Robert Jones <rjones@gateworks.com>
  17 Reviewed-by: Tim Harvey <tharvey@gateworks.com>
  18 Signed-off-by: Shawn Guo <shawnguo@kernel.org>
  19 ---
  20  arch/arm/boot/dts/Makefile            |   2 +
  21  arch/arm/boot/dts/imx6dl-gw5907.dts   |  14 ++
  22  arch/arm/boot/dts/imx6q-gw5907.dts    |  14 ++
  23  arch/arm/boot/dts/imx6qdl-gw5907.dtsi | 399 ++++++++++++++++++++++++++++++++++
  24  4 files changed, 429 insertions(+)
  25  create mode 100644 arch/arm/boot/dts/imx6dl-gw5907.dts
  26  create mode 100644 arch/arm/boot/dts/imx6q-gw5907.dts
  27  create mode 100644 arch/arm/boot/dts/imx6qdl-gw5907.dtsi
  28
  29 --- a/arch/arm/boot/dts/Makefile
  30 +++ b/arch/arm/boot/dts/Makefile
  31 @@ -404,6 +404,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
  32         imx6dl-gw560x.dtb \
  33         imx6dl-gw5903.dtb \
  34         imx6dl-gw5904.dtb \
  35 +       imx6dl-gw5907.dtb \
  36         imx6dl-hummingboard.dtb \
  37         imx6dl-hummingboard-emmc-som-v15.dtb \
  38         imx6dl-hummingboard-som-v15.dtb \
  39 @@ -471,6 +472,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
  40         imx6q-gw560x.dtb \
  41         imx6q-gw5903.dtb \
  42         imx6q-gw5904.dtb \
  43 +       imx6q-gw5907.dtb \
  44         imx6q-h100.dtb \
  45         imx6q-hummingboard.dtb \
  46         imx6q-hummingboard-emmc-som-v15.dtb \
  47 --- /dev/null
  48 +++ b/arch/arm/boot/dts/imx6dl-gw5907.dts
  49 @@ -0,0 +1,14 @@
  50 +// SPDX-License-Identifier: GPL-2.0
  51 +/*
  52 + * Copyright 2019 Gateworks Corporation
  53 + */
  54 +
  55 +/dts-v1/;
  56 +
  57 +#include "imx6dl.dtsi"
  58 +#include "imx6qdl-gw5907.dtsi"
  59 +
  60 +/ {
  61 +       model = "Gateworks Ventana i.MX6 DualLite/Solo GW5907";
  62 +       compatible = "gw,imx6dl-gw5907", "gw,ventana", "fsl,imx6dl";
  63 +};
  64 --- /dev/null
  65 +++ b/arch/arm/boot/dts/imx6q-gw5907.dts
  66 @@ -0,0 +1,14 @@
  67 +// SPDX-License-Identifier: GPL-2.0
  68 +/*
  69 + * Copyright 2019 Gateworks Corporation
  70 + */
  71 +
  72 +/dts-v1/;
  73 +
  74 +#include "imx6q.dtsi"
  75 +#include "imx6qdl-gw5907.dtsi"
  76 +
  77 +/ {
  78 +       model = "Gateworks Ventana i.MX6 Dual/Quad GW5907";
  79 +       compatible = "gw,imx6q-gw5907", "gw,ventana", "fsl,imx6q";
  80 +};
  81 --- /dev/null
  82 +++ b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi
  83 @@ -0,0 +1,399 @@
  84 +// SPDX-License-Identifier: GPL-2.0
  85 +/*
  86 + * Copyright 2019 Gateworks Corporation
  87 + */
  88 +
  89 +#include <dt-bindings/gpio/gpio.h>
  90 +
  91 +/ {
  92 +       /* these are used by bootloader for disabling nodes */
  93 +       aliases {
  94 +               led0 = &led0;
  95 +               led1 = &led1;
  96 +               nand = &gpmi;
  97 +               usb0 = &usbh1;
  98 +               usb1 = &usbotg;
  99 +       };
 100 +
 101 +       chosen {
 102 +               stdout-path = &uart2;
 103 +       };
 104 +
 105 +       leds {
 106 +               compatible = "gpio-leds";
 107 +               pinctrl-names = "default";
 108 +               pinctrl-0 = <&pinctrl_gpio_leds>;
 109 +
 110 +               led0: user1 {
 111 +                       label = "user1";
 112 +                       gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
 113 +                       default-state = "on";
 114 +                       linux,default-trigger = "heartbeat";
 115 +               };
 116 +
 117 +               led1: user2 {
 118 +                       label = "user2";
 119 +                       gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
 120 +                       default-state = "off";
 121 +               };
 122 +       };
 123 +
 124 +       memory@10000000 {
 125 +               device_type = "memory";
 126 +               reg = <0x10000000 0x20000000>;
 127 +       };
 128 +
 129 +       pps {
 130 +               compatible = "pps-gpio";
 131 +               pinctrl-names = "default";
 132 +               pinctrl-0 = <&pinctrl_pps>;
 133 +               gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
 134 +               status = "okay";
 135 +       };
 136 +
 137 +       reg_3p3v: regulator-3p3v {
 138 +               compatible = "regulator-fixed";
 139 +               regulator-name = "3P3V";
 140 +               regulator-min-microvolt = <3300000>;
 141 +               regulator-max-microvolt = <3300000>;
 142 +               regulator-always-on;
 143 +       };
 144 +
 145 +       reg_5p0v: regulator-5p0v {
 146 +               compatible = "regulator-fixed";
 147 +               regulator-name = "5P0V";
 148 +               regulator-min-microvolt = <5000000>;
 149 +               regulator-max-microvolt = <5000000>;
 150 +               regulator-always-on;
 151 +       };
 152 +
 153 +       reg_usb_otg_vbus: regulator-usb-otg-vbus {
 154 +               compatible = "regulator-fixed";
 155 +               regulator-name = "usb_otg_vbus";
 156 +               regulator-min-microvolt = <5000000>;
 157 +               regulator-max-microvolt = <5000000>;
 158 +               gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
 159 +               enable-active-high;
 160 +       };
 161 +};
 162 +
 163 +&fec {
 164 +       pinctrl-names = "default";
 165 +       pinctrl-0 = <&pinctrl_enet>;
 166 +       phy-mode = "rgmii-id";
 167 +       phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
 168 +       status = "okay";
 169 +};
 170 +
 171 +&gpmi {
 172 +       pinctrl-names = "default";
 173 +       pinctrl-0 = <&pinctrl_gpmi_nand>;
 174 +       status = "okay";
 175 +};
 176 +
 177 +&hdmi {
 178 +       ddc-i2c-bus = <&i2c3>;
 179 +       status = "okay";
 180 +};
 181 +
 182 +&i2c1 {
 183 +       clock-frequency = <100000>;
 184 +       pinctrl-names = "default";
 185 +       pinctrl-0 = <&pinctrl_i2c1>;
 186 +       status = "okay";
 187 +
 188 +       gpio@23 {
 189 +               compatible = "nxp,pca9555";
 190 +               reg = <0x23>;
 191 +               gpio-controller;
 192 +               #gpio-cells = <2>;
 193 +       };
 194 +
 195 +       eeprom@50 {
 196 +               compatible = "atmel,24c02";
 197 +               reg = <0x50>;
 198 +               pagesize = <16>;
 199 +       };
 200 +
 201 +       eeprom@51 {
 202 +               compatible = "atmel,24c02";
 203 +               reg = <0x51>;
 204 +               pagesize = <16>;
 205 +       };
 206 +
 207 +       eeprom@52 {
 208 +               compatible = "atmel,24c02";
 209 +               reg = <0x52>;
 210 +               pagesize = <16>;
 211 +       };
 212 +
 213 +       eeprom@53 {
 214 +               compatible = "atmel,24c02";
 215 +               reg = <0x53>;
 216 +               pagesize = <16>;
 217 +       };
 218 +
 219 +       rtc@68 {
 220 +               compatible = "dallas,ds1672";
 221 +               reg = <0x68>;
 222 +       };
 223 +};
 224 +
 225 +&i2c2 {
 226 +       clock-frequency = <100000>;
 227 +       pinctrl-names = "default";
 228 +       pinctrl-0 = <&pinctrl_i2c2>;
 229 +       status = "okay";
 230 +};
 231 +
 232 +&i2c3 {
 233 +       clock-frequency = <100000>;
 234 +       pinctrl-names = "default";
 235 +       pinctrl-0 = <&pinctrl_i2c3>;
 236 +       status = "okay";
 237 +
 238 +       gpio@20 {
 239 +               compatible = "nxp,pca9555";
 240 +               reg = <0x20>;
 241 +               gpio-controller;
 242 +               #gpio-cells = <2>;
 243 +       };
 244 +
 245 +       adc@48 {
 246 +               compatible = "ti,ads1015";
 247 +               reg = <0x48>;
 248 +               #address-cells = <1>;
 249 +               #size-cells = <0>;
 250 +
 251 +               channel@4 {
 252 +                       reg = <4>;
 253 +                       ti,gain = <0>;
 254 +                       ti,datarate = <5>;
 255 +               };
 256 +
 257 +               channel@5 {
 258 +                       reg = <5>;
 259 +                       ti,gain = <0>;
 260 +                       ti,datarate = <5>;
 261 +               };
 262 +
 263 +               channel@6 {
 264 +                       reg = <6>;
 265 +                       ti,gain = <0>;
 266 +                       ti,datarate = <5>;
 267 +               };
 268 +       };
 269 +};
 270 +
 271 +&pcie {
 272 +       pinctrl-names = "default";
 273 +       pinctrl-0 = <&pinctrl_pcie>;
 274 +       reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
 275 +       status = "okay";
 276 +};
 277 +
 278 +&pwm2 {
 279 +       pinctrl-names = "default";
 280 +       pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
 281 +       status = "disabled";
 282 +};
 283 +
 284 +&pwm3 {
 285 +       pinctrl-names = "default";
 286 +       pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
 287 +       status = "disabled";
 288 +};
 289 +
 290 +&pwm4 {
 291 +       pinctrl-names = "default";
 292 +       pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
 293 +       status = "disabled";
 294 +};
 295 +
 296 +&uart1 {
 297 +       pinctrl-names = "default";
 298 +       pinctrl-0 = <&pinctrl_uart1>;
 299 +       status = "okay";
 300 +};
 301 +
 302 +&uart2 {
 303 +       pinctrl-names = "default";
 304 +       pinctrl-0 = <&pinctrl_uart2>;
 305 +       status = "okay";
 306 +};
 307 +
 308 +&uart3 {
 309 +       pinctrl-names = "default";
 310 +       pinctrl-0 = <&pinctrl_uart3>;
 311 +       status = "okay";
 312 +};
 313 +
 314 +&uart5 {
 315 +       pinctrl-names = "default";
 316 +       pinctrl-0 = <&pinctrl_uart5>;
 317 +       status = "okay";
 318 +};
 319 +
 320 +&usbotg {
 321 +       vbus-supply = <&reg_usb_otg_vbus>;
 322 +       pinctrl-names = "default";
 323 +       pinctrl-0 = <&pinctrl_usbotg>;
 324 +       disable-over-current;
 325 +       status = "okay";
 326 +};
 327 +
 328 +&usbh1 {
 329 +       status = "okay";
 330 +};
 331 +
 332 +&wdog1 {
 333 +       pinctrl-names = "default";
 334 +       pinctrl-0 = <&pinctrl_wdog>;
 335 +       fsl,ext-reset-output;
 336 +};
 337 +
 338 +&iomuxc {
 339 +       pinctrl_enet: enetgrp {
 340 +               fsl,pins = <
 341 +                       MX6QDL_PAD_RGMII_RXC__RGMII_RXC         0x1b0b0
 342 +                       MX6QDL_PAD_RGMII_RD0__RGMII_RD0         0x1b0b0
 343 +                       MX6QDL_PAD_RGMII_RD1__RGMII_RD1         0x1b0b0
 344 +                       MX6QDL_PAD_RGMII_RD2__RGMII_RD2         0x1b0b0
 345 +                       MX6QDL_PAD_RGMII_RD3__RGMII_RD3         0x1b0b0
 346 +                       MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL   0x1b0b0
 347 +                       MX6QDL_PAD_RGMII_TXC__RGMII_TXC         0x1b0b0
 348 +                       MX6QDL_PAD_RGMII_TD0__RGMII_TD0         0x1b0b0
 349 +                       MX6QDL_PAD_RGMII_TD1__RGMII_TD1         0x1b0b0
 350 +                       MX6QDL_PAD_RGMII_TD2__RGMII_TD2         0x1b0b0
 351 +                       MX6QDL_PAD_RGMII_TD3__RGMII_TD3         0x1b0b0
 352 +                       MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL   0x1b0b0
 353 +                       MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK    0x1b0b0
 354 +                       MX6QDL_PAD_ENET_MDIO__ENET_MDIO         0x1b0b0
 355 +                       MX6QDL_PAD_ENET_MDC__ENET_MDC           0x1b0b0
 356 +                       MX6QDL_PAD_GPIO_16__ENET_REF_CLK        0x4001b0a8
 357 +                       MX6QDL_PAD_ENET_TXD0__GPIO1_IO30        0x1b0b0
 358 +               >;
 359 +       };
 360 +
 361 +       pinctrl_gpio_leds: gpioledsgrp {
 362 +               fsl,pins = <
 363 +                       MX6QDL_PAD_KEY_COL0__GPIO4_IO06         0x1b0b0
 364 +                       MX6QDL_PAD_KEY_ROW0__GPIO4_IO07         0x1b0b0
 365 +               >;
 366 +       };
 367 +
 368 +       pinctrl_gpmi_nand: gpminandgrp {
 369 +               fsl,pins = <
 370 +                       MX6QDL_PAD_NANDF_CLE__NAND_CLE          0xb0b1
 371 +                       MX6QDL_PAD_NANDF_ALE__NAND_ALE          0xb0b1
 372 +                       MX6QDL_PAD_NANDF_WP_B__NAND_WP_B        0xb0b1
 373 +                       MX6QDL_PAD_NANDF_RB0__NAND_READY_B      0xb000
 374 +                       MX6QDL_PAD_NANDF_CS0__NAND_CE0_B        0xb0b1
 375 +                       MX6QDL_PAD_SD4_CMD__NAND_RE_B           0xb0b1
 376 +                       MX6QDL_PAD_SD4_CLK__NAND_WE_B           0xb0b1
 377 +                       MX6QDL_PAD_NANDF_D0__NAND_DATA00        0xb0b1
 378 +                       MX6QDL_PAD_NANDF_D1__NAND_DATA01        0xb0b1
 379 +                       MX6QDL_PAD_NANDF_D2__NAND_DATA02        0xb0b1
 380 +                       MX6QDL_PAD_NANDF_D3__NAND_DATA03        0xb0b1
 381 +                       MX6QDL_PAD_NANDF_D4__NAND_DATA04        0xb0b1
 382 +                       MX6QDL_PAD_NANDF_D5__NAND_DATA05        0xb0b1
 383 +                       MX6QDL_PAD_NANDF_D6__NAND_DATA06        0xb0b1
 384 +                       MX6QDL_PAD_NANDF_D7__NAND_DATA07        0xb0b1
 385 +               >;
 386 +       };
 387 +
 388 +       pinctrl_i2c1: i2c1grp {
 389 +               fsl,pins = <
 390 +                       MX6QDL_PAD_EIM_D21__I2C1_SCL            0x4001b8b1
 391 +                       MX6QDL_PAD_EIM_D28__I2C1_SDA            0x4001b8b1
 392 +                       MX6QDL_PAD_GPIO_4__GPIO1_IO04           0x0001b0b0
 393 +               >;
 394 +       };
 395 +
 396 +       pinctrl_i2c2: i2c2grp {
 397 +               fsl,pins = <
 398 +                       MX6QDL_PAD_KEY_COL3__I2C2_SCL           0x4001b8b1
 399 +                       MX6QDL_PAD_KEY_ROW3__I2C2_SDA           0x4001b8b1
 400 +               >;
 401 +       };
 402 +
 403 +       pinctrl_i2c3: i2c3grp {
 404 +               fsl,pins = <
 405 +                       MX6QDL_PAD_GPIO_3__I2C3_SCL             0x4001b8b1
 406 +                       MX6QDL_PAD_GPIO_6__I2C3_SDA             0x4001b8b1
 407 +                       MX6QDL_PAD_GPIO_2__GPIO1_IO02           0x1b0b0
 408 +                       MX6QDL_PAD_GPIO_19__GPIO4_IO05          0x1b0b0
 409 +               >;
 410 +       };
 411 +
 412 +       pinctrl_pcie: pciegrp {
 413 +               fsl,pins = <
 414 +                       MX6QDL_PAD_GPIO_0__GPIO1_IO00           0x1b0b0
 415 +               >;
 416 +       };
 417 +
 418 +       pinctrl_pps: ppsgrp {
 419 +               fsl,pins = <
 420 +                       MX6QDL_PAD_ENET_RXD1__GPIO1_IO26        0x1b0b1
 421 +               >;
 422 +       };
 423 +
 424 +       pinctrl_pwm2: pwm2grp {
 425 +               fsl,pins = <
 426 +                       MX6QDL_PAD_SD1_DAT2__PWM2_OUT           0x1b0b1
 427 +               >;
 428 +       };
 429 +
 430 +       pinctrl_pwm3: pwm3grp {
 431 +               fsl,pins = <
 432 +                       MX6QDL_PAD_SD1_DAT1__PWM3_OUT           0x1b0b1
 433 +               >;
 434 +       };
 435 +
 436 +       pinctrl_pwm4: pwm4grp {
 437 +               fsl,pins = <
 438 +                       MX6QDL_PAD_SD1_CMD__PWM4_OUT            0x1b0b1
 439 +               >;
 440 +       };
 441 +
 442 +       pinctrl_uart1: uart1grp {
 443 +               fsl,pins = <
 444 +                       MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA      0x1b0b1
 445 +                       MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA      0x1b0b1
 446 +               >;
 447 +       };
 448 +
 449 +       pinctrl_uart2: uart2grp {
 450 +               fsl,pins = <
 451 +                       MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA      0x1b0b1
 452 +                       MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA      0x1b0b1
 453 +               >;
 454 +       };
 455 +
 456 +       pinctrl_uart3: uart3grp {
 457 +               fsl,pins = <
 458 +                       MX6QDL_PAD_EIM_D24__UART3_TX_DATA       0x1b0b1
 459 +                       MX6QDL_PAD_EIM_D25__UART3_RX_DATA       0x1b0b1
 460 +               >;
 461 +       };
 462 +
 463 +       pinctrl_uart5: uart5grp {
 464 +               fsl,pins = <
 465 +                       MX6QDL_PAD_KEY_COL1__UART5_TX_DATA      0x1b0b1
 466 +                       MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA      0x1b0b1
 467 +               >;
 468 +       };
 469 +
 470 +       pinctrl_usbotg: usbotggrp {
 471 +               fsl,pins = <
 472 +                       MX6QDL_PAD_GPIO_1__USB_OTG_ID           0x17059
 473 +                       MX6QDL_PAD_EIM_D22__GPIO3_IO22          0x1b0b0
 474 +               >;
 475 +       };
 476 +
 477 +       pinctrl_wdog: wdoggrp {
 478 +               fsl,pins = <
 479 +                       MX6QDL_PAD_DISP0_DAT8__WDOG1_B          0x1b0b0
 480 +               >;
 481 +       };
 482 +};