target/linux/ipq806x/files/arch/arm/boot/dts/qcom-ipq8065-rt4230w-rev6.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 #include "qcom-ipq8065.dtsi"
   4 #include <dt-bindings/input/input.h>
   5
   6 / {
   7         model = "Askey RT4230W REV6";
   8         compatible = "askey,rt4230w-rev6", "qcom,ipq8065", "qcom,ipq8064";
   9
  10         memory@0 {
  11                 reg = <0x42000000 0x3e000000>;
  12                 device_type = "memory";
  13         };
  14
  15         aliases {
  16                 led-boot = &ledctrl3;
  17                 led-failsafe = &ledctrl1;
  18                 led-running = &ledctrl2;
  19                 led-upgrade = &ledctrl3;
  20         };
  21
  22         chosen {
  23                 bootargs = "rootfstype=squashfs noinitrd";
  24         };
  25
  26         keys {
  27                 compatible = "gpio-keys";
  28                 pinctrl-0 = <&button_pins>;
  29                 pinctrl-names = "default";
  30
  31                 reset {
  32                         label = "reset";
  33                         gpios = <&qcom_pinmux 54 GPIO_ACTIVE_LOW>;
  34                         linux,code = <KEY_RESTART>;
  35                 };
  36
  37                 wps {
  38                         label = "wps";
  39                         gpios = <&qcom_pinmux 68 GPIO_ACTIVE_LOW>;
  40                         linux,code = <KEY_WPS_BUTTON>;
  41                 };
  42         };
  43
  44         leds {
  45                 compatible = "gpio-leds";
  46                 pinctrl-0 = <&led_pins>;
  47                 pinctrl-names = "default";
  48
  49                 ledctrl1: ledctrl1 {
  50                         label = "ledctrl1";
  51                         gpios = <&qcom_pinmux 22 GPIO_ACTIVE_HIGH>;
  52                 };
  53
  54                 ledctrl2: ledctrl2 {
  55                         label = "ledctrl2";
  56                         gpios = <&qcom_pinmux 23 GPIO_ACTIVE_HIGH>;
  57                 };
  58
  59                 ledctrl3: ledctrl3 {
  60                         label = "ledctrl3";
  61                         gpios = <&qcom_pinmux 24 GPIO_ACTIVE_HIGH>;
  62                 };
  63         };
  64 };
  65
  66 &qcom_pinmux {
  67         button_pins: button_pins {
  68                 mux {
  69                         pins = "gpio54", "gpio68";
  70                         function = "gpio";
  71                         drive-strength = <2>;
  72                         bias-pull-up;
  73                 };
  74         };
  75
  76         led_pins: led_pins {
  77                 mux {
  78                         pins = "gpio22", "gpio23", "gpio24";
  79                         function = "gpio";
  80                         drive-strength = <2>;
  81                         bias-pull-down;
  82                 };
  83         };
  84
  85         rgmii2_pins: rgmii2_pins {
  86                 mux {
  87                         pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31",
  88                                 "gpio51", "gpio52", "gpio59", "gpio60", "gpio61", "gpio62";
  89                         function = "rgmii2";
  90                         drive-strength = <8>;
  91                         bias-disable;
  92                 };
  93
  94                 tx {
  95                         pins = "gpio27", "gpio28", "gpio29", "gpio30", "gpio31", "gpio32";
  96                         input-disable;
  97                 };
  98         };
  99 };
 100
 101 &nand_controller {
 102         status = "okay";
 103
 104         pinctrl-0 = <&nand_pins>;
 105         pinctrl-names = "default";
 106
 107         nand@0 {
 108                 reg = <0>;
 109                 compatible = "qcom,nandcs";
 110
 111                 nand-ecc-strength = <4>;
 112                 nand-bus-width = <8>;
 113                 nand-ecc-step-size = <512>;
 114
 115                 partitions {
 116                         compatible = "fixed-partitions";
 117                         #address-cells = <1>;
 118                         #size-cells = <1>;
 119
 120                         partition@0 {
 121                                 label = "0:SBL1";
 122                                 reg = <0x0000000 0x0040000>;
 123                                 read-only;
 124                         };
 125                         partition@40000 {
 126                                 label = "0:MIBIB";
 127                                 reg = <0x0040000 0x0140000>;
 128                                 read-only;
 129                         };
 130                         partition@180000 {
 131                                 label = "0:SBL2";
 132                                 reg = <0x0180000 0x0140000>;
 133                                 read-only;
 134                         };
 135                         partition@2c0000 {
 136                                 label = "0:SBL3";
 137                                 reg = <0x02c0000 0x0280000>;
 138                                 read-only;
 139                         };
 140                         partition@540000 {
 141                                 label = "0:DDRCONFIG";
 142                                 reg = <0x0540000 0x0120000>;
 143                                 read-only;
 144                         };
 145                         partition@660000 {
 146                                 label = "0:SSD";
 147                                 reg = <0x0660000 0x0120000>;
 148                                 read-only;
 149                         };
 150                         partition@780000 {
 151                                 label = "0:TZ";
 152                                 reg = <0x0780000 0x0280000>;
 153                                 read-only;
 154                         };
 155                         partition@a00000 {
 156                                 label = "0:RPM";
 157                                 reg = <0x0a00000 0x0280000>;
 158                                 read-only;
 159                         };
 160                         partition@c80000 {
 161                                 label = "0:APPSBL";
 162                                 reg = <0x0c80000 0x0500000>;
 163                                 read-only;
 164                         };
 165                         partition@1180000 {
 166                                 label = "0:APPSBLENV";
 167                                 reg = <0x1180000 0x0080000>;
 168                         };
 169                         ART: partition@1200000 {
 170                                 label = "0:ART";
 171                                 reg = <0x1200000 0x0140000>;
 172                                 read-only;
 173                         };
 174                         partition@1340000 {
 175                                 label = "0:BOOTCONFIG";
 176                                 reg = <0x1340000 0x0060000>;
 177                                 read-only;
 178                         };
 179                         partition@13a0000 {
 180                                 label = "0:SBL2_1";
 181                                 reg = <0x13a0000 0x0140000>;
 182                                 read-only;
 183                         };
 184                         partition@14e0000 {
 185                                 label = "0:SBL3_1";
 186                                 reg = <0x14e0000 0x0280000>;
 187                                 read-only;
 188                         };
 189                         partition@1760000 {
 190                                 label = "0:DDRCONFIG_1";
 191                                 reg = <0x1760000 0x0120000>;
 192                                 read-only;
 193                         };
 194                         partition@1880000 {
 195                                 label = "0:SSD_1";
 196                                 reg = <0x1880000 0x0120000>;
 197                                 read-only;
 198                         };
 199                         partition@19a0000 {
 200                                 label = "0:TZ_1";
 201                                 reg = <0x19a0000 0x0280000>;
 202                                 read-only;
 203                         };
 204                         partition@1c20000 {
 205                                 label = "0:RPM_1";
 206                                 reg = <0x1c20000 0x0280000>;
 207                                 read-only;
 208                         };
 209                         partition@1ea0000 {
 210                                 label = "0:BOOTCONFIG1";
 211                                 reg = <0x1ea0000 0x0060000>;
 212                                 read-only;
 213                         };
 214                         partition@1f00000 {
 215                                 label = "0:APPSBL_1";
 216                                 reg = <0x1f00000 0x0500000>;
 217                                 read-only;
 218                         };
 219                         partition@2400000 {
 220                                 label = "ubi";
 221                                 reg = <0x2400000 0x1a000000>;
 222                         };
 223                 };
 224         };
 225 };
 226
 227 &mdio0 {
 228         status = "okay";
 229
 230         pinctrl-0 = <&mdio0_pins>;
 231         pinctrl-names = "default";
 232
 233         phy0: ethernet-phy@0 {
 234                 reg = <0x0>;
 235                 qca,ar8327-initvals = <
 236                         0x00004 0x7600000   /* PAD0_MODE */
 237                         0x00008 0x1000000   /* PAD5_MODE */
 238                         0x0000c 0x80        /* PAD6_MODE */
 239                         0x000e4 0xaa545     /* MAC_POWER_SEL */
 240                         0x000e0 0xc74164de  /* SGMII_CTRL */
 241                         0x0007c 0x4e        /* PORT0_STATUS */
 242                         0x00094 0x4e        /* PORT6_STATUS */
 243                         0x00050 0xcf02cf02  /* LED_CTRL_0 */
 244                         0x00054 0xc832c832  /* LED_CTRL_1 */
 245                         >;
 246         };
 247 };
 248
 249 &gmac0 {
 250         status = "okay";
 251         phy-mode = "rgmii";
 252         qcom,id = <0>;
 253
 254         mtd-mac-address = <&ART 0x0>;
 255
 256         pinctrl-0 = <&rgmii2_pins>;
 257         pinctrl-names = "default";
 258
 259         fixed-link {
 260                 speed = <1000>;
 261                 full-duplex;
 262         };
 263 };
 264
 265 &gmac1 {
 266         status = "okay";
 267         phy-mode = "sgmii";
 268         qcom,id = <1>;
 269
 270         mtd-mac-address = <&ART 0x6>;
 271
 272         fixed-link {
 273                 speed = <1000>;
 274                 full-duplex;
 275         };
 276 };
 277
 278 &adm_dma {
 279         status = "okay";
 280 };
 281
 282 &usb3_0 {
 283         status = "okay";
 284         clocks = <&gcc USB30_1_MASTER_CLK>;
 285 };
 286
 287 &usb3_1 {
 288         status = "okay";
 289         clocks = <&gcc USB30_0_MASTER_CLK>;
 290 };
 291
 292 &pcie0 {
 293         status = "okay";
 294         reset-gpio = <&qcom_pinmux 3 GPIO_ACTIVE_HIGH>;
 295         /delete-property/ perst-gpios;
 296 };
 297
 298 &pcie1 {
 299         status = "okay";
 300         reset-gpio = <&qcom_pinmux 48 GPIO_ACTIVE_HIGH>;
 301         /delete-property/ perst-gpios;
 302         force_gen1 = <1>;
 303 };