2 * Copyright 2017 Sean Wang <sean.wang@mediatek.com>
4 * SPDX-License-Identifier: (GPL-2.0+ OR MIT)
8 #include <dt-bindings/input/input.h>
9 #include "_mt7623.dtsi"
10 #include "mt6323.dtsi"
13 model = "Bananapi BPI-R2";
14 compatible = "bananapi,bpi-r2", "mediatek,mt7623";
21 stdout-path = "serial2:115200n8";
26 proc-supply = <&mt6323_vproc_reg>;
30 proc-supply = <&mt6323_vproc_reg>;
34 proc-supply = <&mt6323_vproc_reg>;
38 proc-supply = <&mt6323_vproc_reg>;
43 compatible = "gpio-keys";
44 pinctrl-names = "default";
45 pinctrl-0 = <&key_pins_a>;
50 gpios = <&pio 256 GPIO_ACTIVE_LOW>;
55 linux,code = <KEY_WPS_BUTTON>;
56 gpios = <&pio 257 GPIO_ACTIVE_HIGH>;
61 compatible = "gpio-leds";
62 pinctrl-names = "default";
63 pinctrl-0 = <&led_pins_a>;
66 label = "bpi-r2:pio:red";
67 gpios = <&pio 239 GPIO_ACTIVE_HIGH>;
68 default-state = "off";
72 label = "bpi-r2:pio:green";
73 gpios = <&pio 240 GPIO_ACTIVE_HIGH>;
74 default-state = "off";
78 label = "bpi-r2:pio:blue";
79 gpios = <&pio 241 GPIO_ACTIVE_HIGH>;
80 default-state = "off";
85 reg = <0 0x80000000 0 0x40000000>;
90 pinctrl-names = "default";
91 pinctrl-0 = <&cir_pins_a>;
102 compatible = "mediatek,eth-mac";
113 #address-cells = <1>;
116 compatible = "mediatek,mt7530";
117 #address-cells = <1>;
121 pinctrl-names = "default";
122 reset-gpios = <&pio 33 0>;
123 core-supply = <&mt6323_vpa_reg>;
124 io-supply = <&mt6323_vemc3v3_reg>;
127 #address-cells = <1>;
171 pinctrl-names = "default";
172 pinctrl-0 = <&i2c0_pins_a>;
177 pinctrl-names = "default";
178 pinctrl-0 = <&i2c1_pins_a>;
185 pinmux = <MT7623_PIN_46_IR_FUNC_IR>;
192 pinmux = <MT7623_PIN_75_SDA0_FUNC_SDA0>,
193 <MT7623_PIN_76_SCL0_FUNC_SCL0>;
200 pinmux = <MT7623_PIN_57_SDA1_FUNC_SDA1>,
201 <MT7623_PIN_58_SCL1_FUNC_SCL1>;
208 pinmux = <MT7623_PIN_49_I2S0_DATA_FUNC_I2S0_DATA>,
209 <MT7623_PIN_72_I2S0_DATA_IN_FUNC_I2S0_DATA_IN>,
210 <MT7623_PIN_73_I2S0_LRCK_FUNC_I2S0_LRCK>,
211 <MT7623_PIN_74_I2S0_BCK_FUNC_I2S0_BCK>,
212 <MT7623_PIN_126_I2S0_MCLK_FUNC_I2S0_MCLK>;
213 drive-strength = <MTK_DRIVE_12mA>;
220 pinmux = <MT7623_PIN_33_I2S1_DATA_FUNC_I2S1_DATA>,
221 <MT7623_PIN_34_I2S1_DATA_IN_FUNC_I2S1_DATA_IN>,
222 <MT7623_PIN_35_I2S1_BCK_FUNC_I2S1_BCK>,
223 <MT7623_PIN_36_I2S1_LRCK_FUNC_I2S1_LRCK>,
224 <MT7623_PIN_37_I2S1_MCLK_FUNC_I2S1_MCLK>;
225 drive-strength = <MTK_DRIVE_12mA>;
232 pinmux = <MT7623_PIN_256_GPIO256_FUNC_GPIO256>,
233 <MT7623_PIN_257_GPIO257_FUNC_GPIO257> ;
240 pinmux = <MT7623_PIN_239_EXT_SDIO0_FUNC_GPIO239>,
241 <MT7623_PIN_240_EXT_XCS_FUNC_GPIO240>,
242 <MT7623_PIN_241_EXT_SCK_FUNC_GPIO241>;
246 mmc0_pins_default: mmc0default {
248 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
249 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
250 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
251 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
252 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
253 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
254 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
255 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
256 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
262 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
267 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
272 mmc0_pins_uhs: mmc0 {
274 pinmux = <MT7623_PIN_111_MSDC0_DAT7_FUNC_MSDC0_DAT7>,
275 <MT7623_PIN_112_MSDC0_DAT6_FUNC_MSDC0_DAT6>,
276 <MT7623_PIN_113_MSDC0_DAT5_FUNC_MSDC0_DAT5>,
277 <MT7623_PIN_114_MSDC0_DAT4_FUNC_MSDC0_DAT4>,
278 <MT7623_PIN_118_MSDC0_DAT3_FUNC_MSDC0_DAT3>,
279 <MT7623_PIN_119_MSDC0_DAT2_FUNC_MSDC0_DAT2>,
280 <MT7623_PIN_120_MSDC0_DAT1_FUNC_MSDC0_DAT1>,
281 <MT7623_PIN_121_MSDC0_DAT0_FUNC_MSDC0_DAT0>,
282 <MT7623_PIN_116_MSDC0_CMD_FUNC_MSDC0_CMD>;
284 drive-strength = <MTK_DRIVE_2mA>;
285 bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
289 pinmux = <MT7623_PIN_117_MSDC0_CLK_FUNC_MSDC0_CLK>;
290 drive-strength = <MTK_DRIVE_2mA>;
291 bias-pull-down = <MTK_PUPD_SET_R1R0_01>;
295 pinmux = <MT7623_PIN_115_MSDC0_RSTB_FUNC_MSDC0_RSTB>;
300 mmc1_pins_default: mmc1default {
302 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
303 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
304 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
305 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
306 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
308 drive-strength = <MTK_DRIVE_4mA>;
309 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
313 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
315 drive-strength = <MTK_DRIVE_4mA>;
319 mmc1_pins_uhs: mmc1 {
321 pinmux = <MT7623_PIN_107_MSDC1_DAT0_FUNC_MSDC1_DAT0>,
322 <MT7623_PIN_108_MSDC1_DAT1_FUNC_MSDC1_DAT1>,
323 <MT7623_PIN_109_MSDC1_DAT2_FUNC_MSDC1_DAT2>,
324 <MT7623_PIN_110_MSDC1_DAT3_FUNC_MSDC1_DAT3>,
325 <MT7623_PIN_105_MSDC1_CMD_FUNC_MSDC1_CMD>;
327 drive-strength = <MTK_DRIVE_4mA>;
328 bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
332 pinmux = <MT7623_PIN_106_MSDC1_CLK_FUNC_MSDC1_CLK>;
333 drive-strength = <MTK_DRIVE_4mA>;
334 bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
340 pinmux = <MT7623_PIN_53_SPI0_CSN_FUNC_SPI0_CS>,
341 <MT7623_PIN_54_SPI0_CK_FUNC_SPI0_CK>,
342 <MT7623_PIN_55_SPI0_MI_FUNC_SPI0_MI>,
343 <MT7623_PIN_56_SPI0_MO_FUNC_SPI0_MO>;
350 pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,
351 <MT7623_PIN_204_PWM1_FUNC_PWM1>,
352 <MT7623_PIN_205_PWM2_FUNC_PWM2>,
353 <MT7623_PIN_206_PWM3_FUNC_PWM3>,
354 <MT7623_PIN_207_PWM4_FUNC_PWM4>;
358 uart0_pins_a: uart@0 {
360 pinmux = <MT7623_PIN_79_URXD0_FUNC_URXD0>,
361 <MT7623_PIN_80_UTXD0_FUNC_UTXD0>;
365 uart1_pins_a: uart@1 {
367 pinmux = <MT7623_PIN_81_URXD1_FUNC_URXD1>,
368 <MT7623_PIN_82_UTXD1_FUNC_UTXD1>;
374 pinctrl-names = "default";
375 pinctrl-0 = <&pwm_pins_a>;
382 compatible = "mediatek,mt6323-led";
383 #address-cells = <1>;
388 label = "bpi-r2:isink:green";
389 default-state = "off";
393 label = "bpi-r2:isink:red";
394 default-state = "off";
398 label = "bpi-r2:isink:blue";
399 default-state = "off";
406 pinctrl-names = "default";
407 pinctrl-0 = <&spi0_pins_a>;
412 pinctrl-names = "default";
413 pinctrl-0 = <&uart0_pins_a>;
426 pinctrl-names = "default";
427 pinctrl-0 = <&uart1_pins_a>;
436 vusb33-supply = <&mt6323_vusb_reg>;
441 vusb33-supply = <&mt6323_vusb_reg>;