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fix bcm47xx cache fixes
[openwrt/staging/dedeckeh.git] / openwrt / target / linux / linux-2.4 / patches / brcm / 003-bcm47xx_cache_fixes.patch
1 diff -urN linux.old/arch/mips/mm/tlbex-mips32.S linux.dev/arch/mips/mm/tlbex-mips32.S
2 --- linux.old/arch/mips/mm/tlbex-mips32.S 2005-05-28 17:42:03.000000000 +0200
3 +++ linux.dev/arch/mips/mm/tlbex-mips32.S 2005-05-28 21:48:55.000000000 +0200
4 @@ -90,6 +90,9 @@
5 .set noat
6 LEAF(except_vec0_r4000)
7 .set mips3
8 +#ifdef CONFIG_BCM4704
9 + nop
10 +#endif
11 #ifdef CONFIG_SMP
12 mfc0 k1, CP0_CONTEXT
13 la k0, pgd_current
14 diff -urN linux.old/arch/mips/mm/pg-r4k.c linux.dev/arch/mips/mm/pg-r4k.c
15 --- linux.old/arch/mips/mm/pg-r4k.c 2005-01-19 15:09:29.000000000 +0100
16 +++ linux.dev/arch/mips/mm/pg-r4k.c 2005-05-28 21:57:52.000000000 +0200
17 @@ -180,6 +180,7 @@
18
19 static inline void build_cdex_s(void)
20 {
21 +#if !defined(CONFIG_BCM4704) && !defined(CONFIG_BCM4710)
22 union mips_instruction mi;
23
24 if ((store_offset & (cpu_scache_line_size() - 1)))
25 @@ -192,10 +193,12 @@
26 mi.c_format.simmediate = store_offset;
27
28 emit_instruction(mi);
29 +#endif
30 }
31
32 static inline void build_cdex_p(void)
33 {
34 +#if !defined(CONFIG_BCM4704) && !defined(CONFIG_BCM4710)
35 union mips_instruction mi;
36
37 if (store_offset & (cpu_dcache_line_size() - 1))
38 @@ -218,6 +221,7 @@
39 mi.c_format.simmediate = store_offset;
40
41 emit_instruction(mi);
42 +#endif
43 }
44
45 static void __build_store_reg(int reg)
46 diff -urN linux.old/include/asm-mips/stackframe.h linux.dev/include/asm-mips/stackframe.h
47 --- linux.old/include/asm-mips/stackframe.h 2002-11-29 00:53:15.000000000 +0100
48 +++ linux.dev/include/asm-mips/stackframe.h 2005-05-28 21:53:03.000000000 +0200
49 @@ -172,6 +172,46 @@
50 rfe; \
51 .set pop
52
53 +#elif defined(CONFIG_BCM4710) || defined(CONFIG_BCM4704)
54 +
55 +#define RESTORE_SOME \
56 + .set push; \
57 + .set reorder; \
58 + mfc0 t0, CP0_STATUS; \
59 + .set pop; \
60 + ori t0, 0x1f; \
61 + xori t0, 0x1f; \
62 + mtc0 t0, CP0_STATUS; \
63 + li v1, 0xff00; \
64 + and t0, v1; \
65 + lw v0, PT_STATUS(sp); \
66 + nor v1, $0, v1; \
67 + and v0, v1; \
68 + or v0, t0; \
69 + ori v1, v0, ST0_IE; \
70 + xori v1, v1, ST0_IE; \
71 + mtc0 v1, CP0_STATUS; \
72 + mtc0 v0, CP0_STATUS; \
73 + lw v1, PT_EPC(sp); \
74 + mtc0 v1, CP0_EPC; \
75 + lw $31, PT_R31(sp); \
76 + lw $28, PT_R28(sp); \
77 + lw $25, PT_R25(sp); \
78 + lw $7, PT_R7(sp); \
79 + lw $6, PT_R6(sp); \
80 + lw $5, PT_R5(sp); \
81 + lw $4, PT_R4(sp); \
82 + lw $3, PT_R3(sp); \
83 + lw $2, PT_R2(sp)
84 +
85 +#define RESTORE_SP_AND_RET \
86 + lw sp, PT_R29(sp); \
87 + nop; \
88 + nop; \
89 + .set mips3; \
90 + eret; \
91 + .set mips0
92 +
93 #else
94
95 #define RESTORE_SOME \
96 diff -urN linux.old/arch/mips/mm/tlbex-r4k.S linux.dev/arch/mips/mm/tlbex-r4k.S
97 --- linux.old/arch/mips/mm/tlbex-r4k.S 2005-05-28 17:42:03.000000000 +0200
98 +++ linux.dev/arch/mips/mm/tlbex-r4k.S 2005-05-29 15:04:43.000000000 +0200
99 @@ -168,6 +168,9 @@
100 .set noat
101 LEAF(except_vec0_r4000)
102 .set mips3
103 +#ifdef CONFIG_BCM4704
104 + nop
105 +#endif
106 GET_PGD(k0, k1) # get pgd pointer
107 mfc0 k0, CP0_BADVADDR # Get faulting address
108 srl k0, k0, _PGDIR_SHIFT # get pgd only bits
109 diff -urN linux.old/arch/mips/kernel/entry.S linux.dev/arch/mips/kernel/entry.S
110 --- linux.old/arch/mips/kernel/entry.S 2003-08-25 13:44:40.000000000 +0200
111 +++ linux.dev/arch/mips/kernel/entry.S 2005-06-01 20:10:36.000000000 +0200
112 @@ -100,6 +100,10 @@
113 * and R4400 SC and MC versions.
114 */
115 NESTED(except_vec3_generic, 0, sp)
116 +#ifdef CONFIG_BCM4710
117 + nop
118 + nop
119 +#endif
120 #if R5432_CP0_INTERRUPT_WAR
121 mfc0 k0, CP0_INDEX
122 #endif
123 diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
124 --- linux.old/arch/mips/mm/c-r4k.c 2005-06-01 18:42:44.000000000 +0200
125 +++ linux.dev/arch/mips/mm/c-r4k.c 2005-06-01 18:49:07.000000000 +0200
126 @@ -14,6 +14,12 @@
127 #include <linux/mm.h>
128 #include <linux/bitops.h>
129
130 +#ifdef CONFIG_BCM4710
131 +#include "../bcm947xx/include/typedefs.h"
132 +#include "../bcm947xx/include/sbconfig.h"
133 +#include <asm/paccess.h>
134 +#endif
135 +
136 #include <asm/bcache.h>
137 #include <asm/bootinfo.h>
138 #include <asm/cacheops.h>
139 @@ -390,6 +396,11 @@
140 addr = start & ~(dc_lsize - 1);
141 aend = (end - 1) & ~(dc_lsize - 1);
142
143 +#ifdef CONFIG_BCM4710
144 + BCM4710_FILL_TLB(addr);
145 + BCM4710_FILL_TLB(aend);
146 +#endif
147 +
148 while (1) {
149 /* Hit_Writeback_Inv_D */
150 protected_writeback_dcache_line(addr);
151 @@ -405,6 +416,10 @@
152 else {
153 addr = start & ~(ic_lsize - 1);
154 aend = (end - 1) & ~(ic_lsize - 1);
155 +#ifdef CONFIG_BCM4710
156 + BCM4710_FILL_TLB(addr);
157 + BCM4710_FILL_TLB(aend);
158 +#endif
159 while (1) {
160 /* Hit_Invalidate_I */
161 protected_flush_icache_line(addr);
162 @@ -487,6 +502,10 @@
163
164 a = addr & ~(sc_lsize - 1);
165 end = (addr + size - 1) & ~(sc_lsize - 1);
166 +#ifdef CONFIG_BCM4710
167 + BCM4710_FILL_TLB(a);
168 + BCM4710_FILL_TLB(end);
169 +#endif
170 while (1) {
171 flush_scache_line(a); /* Hit_Writeback_Inv_SD */
172 if (a == end)
173 @@ -509,6 +528,10 @@
174 R4600_HIT_CACHEOP_WAR_IMPL;
175 a = addr & ~(dc_lsize - 1);
176 end = (addr + size - 1) & ~(dc_lsize - 1);
177 +#ifdef CONFIG_BCM4710
178 + BCM4710_FILL_TLB(a);
179 + BCM4710_FILL_TLB(end);
180 +#endif
181 while (1) {
182 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
183 if (a == end)
184 @@ -537,6 +560,10 @@
185
186 a = addr & ~(sc_lsize - 1);
187 end = (addr + size - 1) & ~(sc_lsize - 1);
188 +#ifdef CONFIG_BCM4710
189 + BCM4710_FILL_TLB(a);
190 + BCM4710_FILL_TLB(end);
191 +#endif
192 while (1) {
193 flush_scache_line(a); /* Hit_Writeback_Inv_SD */
194 if (a == end)
195 @@ -576,6 +603,10 @@
196 unsigned long ic_lsize = current_cpu_data.icache.linesz;
197 unsigned long dc_lsize = current_cpu_data.dcache.linesz;
198
199 +#ifdef CONFIG_BCM4710
200 + BCM4710_PROTECTED_FILL_TLB(addr);
201 + BCM4710_PROTECTED_FILL_TLB(addr + 4);
202 +#endif
203 R4600_HIT_CACHEOP_WAR_IMPL;
204 protected_writeback_dcache_line(addr & ~(dc_lsize - 1));
205 protected_flush_icache_line(addr & ~(ic_lsize - 1));
206 diff -urN linux.old/include/asm-mips/r4kcache.h linux.dev/include/asm-mips/r4kcache.h
207 --- linux.old/include/asm-mips/r4kcache.h 2005-06-01 18:42:43.000000000 +0200
208 +++ linux.dev/include/asm-mips/r4kcache.h 2005-06-01 19:07:11.000000000 +0200
209 @@ -15,6 +15,25 @@
210 #include <asm/asm.h>
211 #include <asm/cacheops.h>
212
213 +#ifdef CONFIG_BCM4710
214 +#define BCM4710_DUMMY_RREG() (((sbconfig_t *)(KSEG1ADDR(SB_ENUM_BASE + SBCONFIGOFF)))->sbimstate)
215 +
216 +#define BCM4710_FILL_TLB(addr) (*(volatile unsigned long *)(addr))
217 +#define BCM4710_PROTECTED_FILL_TLB(addr) ({ unsigned long x; get_dbe(x, (volatile unsigned long *)(addr)); })
218 +
219 +#define cache_op(op,addr) \
220 + BCM4710_DUMMY_RREG(); \
221 + __asm__ __volatile__( \
222 + " .set noreorder \n" \
223 + " .set mips3\n\t \n" \
224 + " cache %0, %1 \n" \
225 + " .set mips0 \n" \
226 + " .set reorder" \
227 + : \
228 + : "i" (op), "m" (*(unsigned char *)(addr)))
229 +
230 +#else
231 +
232 #define cache_op(op,addr) \
233 __asm__ __volatile__( \
234 " .set noreorder \n" \
235 @@ -24,6 +43,8 @@
236 " .set reorder" \
237 : \
238 : "i" (op), "m" (*(unsigned char *)(addr)))
239 +#endif
240 +
241
242 static inline void flush_icache_line_indexed(unsigned long addr)
243 {
244 @@ -32,6 +53,9 @@
245
246 static inline void flush_dcache_line_indexed(unsigned long addr)
247 {
248 +#ifdef CONFIG_BCM4710
249 + BCM4710_DUMMY_RREG();
250 +#endif
251 cache_op(Index_Writeback_Inv_D, addr);
252 }
253
254 @@ -47,6 +71,10 @@
255
256 static inline void flush_dcache_line(unsigned long addr)
257 {
258 +
259 +#ifdef CONFIG_BCM4710
260 + BCM4710_DUMMY_RREG();
261 +#endif
262 cache_op(Hit_Writeback_Inv_D, addr);
263 }
264
265 @@ -91,6 +119,9 @@
266 */
267 static inline void protected_writeback_dcache_line(unsigned long addr)
268 {
269 +#ifdef CONFIG_BCM4710
270 + BCM4710_DUMMY_RREG();
271 +#endif
272 __asm__ __volatile__(
273 ".set noreorder\n\t"
274 ".set mips3\n"
275 @@ -148,8 +179,12 @@
276 unsigned long ws, addr;
277
278 for (ws = 0; ws < ws_end; ws += ws_inc)
279 - for (addr = start; addr < end; addr += 0x200)
280 + for (addr = start; addr < end; addr += 0x200) {
281 +#ifdef CONFIG_BCM4710
282 + BCM4710_DUMMY_RREG();
283 +#endif
284 cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
285 + }
286 }
287
288 static inline void blast_dcache16_page(unsigned long page)
289 @@ -158,6 +193,9 @@
290 unsigned long end = start + PAGE_SIZE;
291
292 do {
293 +#ifdef CONFIG_BCM4710
294 + BCM4710_DUMMY_RREG();
295 +#endif
296 cache16_unroll32(start,Hit_Writeback_Inv_D);
297 start += 0x200;
298 } while (start < end);
299 @@ -173,8 +211,12 @@
300 unsigned long ws, addr;
301
302 for (ws = 0; ws < ws_end; ws += ws_inc)
303 - for (addr = start; addr < end; addr += 0x200)
304 + for (addr = start; addr < end; addr += 0x200) {
305 +#ifdef CONFIG_BCM4710
306 + BCM4710_DUMMY_RREG();
307 +#endif
308 cache16_unroll32(addr|ws,Index_Writeback_Inv_D);
309 + }
310 }
311
312 static inline void blast_icache16(void)
313 @@ -196,7 +238,13 @@
314 unsigned long start = page;
315 unsigned long end = start + PAGE_SIZE;
316
317 +#ifdef CONFIG_BCM4710
318 + BCM4710_FILL_TLB(start);
319 +#endif
320 do {
321 +#ifdef CONFIG_BCM4710
322 + BCM4710_DUMMY_RREG();
323 +#endif
324 cache16_unroll32(start,Hit_Invalidate_I);
325 start += 0x200;
326 } while (start < end);
327 @@ -291,8 +339,12 @@
328 unsigned long ws, addr;
329
330 for (ws = 0; ws < ws_end; ws += ws_inc)
331 - for (addr = start; addr < end; addr += 0x400)
332 + for (addr = start; addr < end; addr += 0x400) {
333 +#ifdef CONFIG_BCM4710
334 + BCM4710_DUMMY_RREG();
335 +#endif
336 cache32_unroll32(addr|ws,Index_Writeback_Inv_D);
337 + }
338 }
339
340 static inline void blast_dcache32_page(unsigned long page)
341 @@ -300,7 +352,13 @@
342 unsigned long start = page;
343 unsigned long end = start + PAGE_SIZE;
344
345 +#ifdef CONFIG_BCM4710
346 + __asm__ __volatile__("nop;nop;nop;nop");
347 +#endif
348 do {
349 +#ifdef CONFIG_BCM4710
350 + BCM4710_DUMMY_RREG();
351 +#endif
352 cache32_unroll32(start,Hit_Writeback_Inv_D);
353 start += 0x400;
354 } while (start < end);
355 @@ -339,6 +397,9 @@
356 unsigned long start = page;
357 unsigned long end = start + PAGE_SIZE;
358
359 +#ifdef CONFIG_BCM4710
360 + BCM4710_FILL_TLB(start);
361 +#endif
362 do {
363 cache32_unroll32(start,Hit_Invalidate_I);
364 start += 0x400;
365 diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
366 --- linux.old/arch/mips/mm/c-r4k.c 2005-06-01 18:49:07.000000000 +0200
367 +++ linux.dev/arch/mips/mm/c-r4k.c 2005-06-03 12:11:13.000000000 +0200
368 @@ -51,6 +51,7 @@
369 #define cpu_is_r4600_v1_x() ((read_c0_prid() & 0xfffffff0) == 0x2010)
370 #define cpu_is_r4600_v2_x() ((read_c0_prid() & 0xfffffff0) == 0x2020)
371
372 +#ifndef CONFIG_BCM4710
373 #define R4600_HIT_CACHEOP_WAR_IMPL \
374 do { \
375 if (R4600_V2_HIT_CACHEOP_WAR && cpu_is_r4600_v2_x()) \
376 @@ -58,11 +59,17 @@
377 if (R4600_V1_HIT_CACHEOP_WAR) \
378 __asm__ __volatile__("nop;nop;nop;nop"); \
379 } while (0)
380 +#else
381 +#define R4600_HIT_CACHEOP_WAR_IMPL
382 +#endif
383
384 static void (* r4k_blast_dcache_page)(unsigned long addr);
385
386 static inline void r4k_blast_dcache_page_dc32(unsigned long addr)
387 {
388 +#ifdef CONFIG_BCM4710
389 + BCM4710_FILL_TLB(addr);
390 +#endif
391 R4600_HIT_CACHEOP_WAR_IMPL;
392 blast_dcache32_page(addr);
393 }
394 @@ -581,6 +588,10 @@
395 R4600_HIT_CACHEOP_WAR_IMPL;
396 a = addr & ~(dc_lsize - 1);
397 end = (addr + size - 1) & ~(dc_lsize - 1);
398 +#ifdef CONFIG_BCM4710
399 + BCM4710_FILL_TLB(a);
400 + BCM4710_FILL_TLB(end);
401 +#endif
402 while (1) {
403 flush_dcache_line(a); /* Hit_Writeback_Inv_D */
404 if (a == end)
405 diff -urN linux.old/arch/mips/mm/c-r4k.c linux.dev/arch/mips/mm/c-r4k.c
406 --- linux.old/arch/mips/mm/c-r4k.c 2005-06-11 19:39:17.000000000 +0200
407 +++ linux.dev/arch/mips/mm/c-r4k.c 2005-06-11 19:54:48.000000000 +0200
408 @@ -1083,6 +1083,19 @@
409 static inline void coherency_setup(void)
410 {
411 change_c0_config(CONF_CM_CMASK, CONF_CM_DEFAULT);
412 +
413 +#if defined(CONFIG_BCM4310) || defined(CONFIG_BCM4704) || defined(CONFIG_BCM5365)
414 + if (BCM330X(current_cpu_data.processor_id)) {
415 + uint32 cm;
416 +
417 + cm = read_c0_diag();
418 + /* Enable icache */
419 + cm |= (1 << 31);
420 + /* Enable dcache */
421 + cm |= (1 << 30);
422 + write_c0_diag(cm);
423 + }
424 +#endif
425
426 /*
427 * c0_status.cu=0 specifies that updates by the sc instruction use
428 @@ -1104,6 +1117,42 @@
429
430 }
431
432 +#ifdef CONFIG_BCM4704
433 +static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
434 +{
435 + unsigned long ic_lsize = current_cpu_data.icache.linesz;
436 + int i;
437 + for (i = 0; i < nbytes; i += ic_lsize)
438 + fill_icache_line((addr + i));
439 +}
440 +
441 +/*
442 + * This must be run from the cache on 4704A0
443 + * so there are no mips core BIU ops in progress
444 + * when the PFC is enabled.
445 + */
446 +#define PFC_CR0 0xff400000 /* control reg 0 */
447 +#define PFC_CR1 0xff400004 /* control reg 1 */
448 +static void __init enable_pfc(u32 mode)
449 +{
450 + /* write range */
451 + *(volatile u32 *)PFC_CR1 = 0xffff0000;
452 +
453 + /* enable */
454 + *(volatile u32 *)PFC_CR0 = mode;
455 +}
456 +
457 +void check_enable_mips_pfc(int val)
458 +{
459 + /* enable prefetch cache */
460 + if (BCM330X(current_cpu_data.processor_id)
461 + && (read_c0_diag() & (1 << 29))) {
462 + mips32_icache_fill((unsigned long) &enable_pfc, 64);
463 + enable_pfc(val);
464 + }
465 +}
466 +#endif
467 +
468 void __init ld_mmu_r4xx0(void)
469 {
470 extern void build_clear_page(void);
471 @@ -1159,47 +1208,9 @@
472
473 build_clear_page();
474 build_copy_page();
475 -}
476 -
477 -#ifdef CONFIG_BCM4704
478 -static void __init mips32_icache_fill(unsigned long addr, uint nbytes)
479 -{
480 - unsigned long ic_lsize = current_cpu_data.icache.linesz;
481 - int i;
482 - for (i = 0; i < nbytes; i += ic_lsize)
483 - fill_icache_line((addr + i));
484 -}
485 -
486 -/*
487 - * This must be run from the cache on 4704A0
488 - * so there are no mips core BIU ops in progress
489 - * when the PFC is enabled.
490 - */
491 -#define PFC_CR0 0xff400000 /* control reg 0 */
492 -#define PFC_CR1 0xff400004 /* control reg 1 */
493 -static void __init enable_pfc(u32 mode)
494 -{
495 - /* write range */
496 - *(volatile u32 *)PFC_CR1 = 0xffff0000;
497 -
498 - /* enable */
499 - *(volatile u32 *)PFC_CR0 = mode;
500 -}
501 -#endif
502 -
503 -
504 -void check_enable_mips_pfc(int val)
505 -{
506 -
507 +
508 #ifdef CONFIG_BCM4704
509 - struct cpuinfo_mips *c = &current_cpu_data;
510 -
511 - /* enable prefetch cache */
512 - if (((c->processor_id & (PRID_COMP_MASK | PRID_IMP_MASK)) == PRID_IMP_BCM3302)
513 - && (read_c0_diag() & (1 << 29))) {
514 - mips32_icache_fill((unsigned long) &enable_pfc, 64);
515 - enable_pfc(val);
516 - }
517 + check_enable_mips_pfc(0x15);
518 #endif
519 }
520
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