target/linux/bmips/dts/bcm63268.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 /dts-v1/;
   4
   5 #include <dt-bindings/clock/bcm63268-clock.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/input/input.h>
   8 #include <dt-bindings/interrupt-controller/bcm63268-interrupt-controller.h>
   9 #include <dt-bindings/reset/bcm63268-reset.h>
  10 #include <dt-bindings/soc/bcm63268-pm.h>
  11
  12 / {
  13         #address-cells = <1>;
  14         #size-cells = <1>;
  15         compatible = "brcm,bcm63268";
  16
  17         aliases {
  18                 nflash = &nflash;
  19                 pinctrl = &pinctrl;
  20                 serial0 = &uart0;
  21                 serial1 = &uart1;
  22                 spi0 = &lsspi;
  23                 spi1 = &hsspi;
  24         };
  25
  26         chosen {
  27                 bootargs = "earlycon";
  28                 stdout-path = "serial0:115200n8";
  29         };
  30
  31         clocks {
  32                 periph_osc: periph-osc {
  33                         compatible = "fixed-clock";
  34
  35                         #clock-cells = <0>;
  36
  37                         clock-frequency = <50000000>;
  38                         clock-output-names = "periph";
  39                 };
  40
  41                 hsspi_osc: hsspi-osc {
  42                         compatible = "fixed-clock";
  43
  44                         #clock-cells = <0>;
  45
  46                         clock-frequency = <400000000>;
  47                         clock-output-names = "hsspi_osc";
  48                 };
  49         };
  50
  51         cpus {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54                 mips-hpt-frequency = <200000000>;
  55
  56                 cpu@0 {
  57                         compatible = "brcm,bmips4350", "mips,mips4Kc";
  58                         device_type = "cpu";
  59                         reg = <0>;
  60                 };
  61
  62                 cpu@1 {
  63                         compatible = "brcm,bmips4350", "mips,mips4Kc";
  64                         device_type = "cpu";
  65                         reg = <1>;
  66                 };
  67         };
  68
  69         cpu_intc: interrupt-controller {
  70                 #address-cells = <0>;
  71                 compatible = "mti,cpu-interrupt-controller";
  72
  73                 interrupt-controller;
  74                 #interrupt-cells = <1>;
  75         };
  76
  77         memory@0 {
  78                 device_type = "memory";
  79                 reg = <0 0>;
  80         };
  81
  82         ubus {
  83                 #address-cells = <1>;
  84                 #size-cells = <1>;
  85
  86                 compatible = "simple-bus";
  87                 ranges;
  88
  89                 periph_clk: clock-controller@10000004 {
  90                         compatible = "brcm,bcm63268-clocks";
  91                         reg = <0x10000004 0x4>;
  92                         #clock-cells = <1>;
  93                 };
  94
  95                 pll_cntl: syscon@10000008 {
  96                         compatible = "syscon", "simple-mfd";
  97                         reg = <0x10000008 0x4>;
  98                         native-endian;
  99
 100                         syscon-reboot {
 101                                 compatible = "syscon-reboot";
 102                                 offset = <0x0>;
 103                                 mask = <0x1>;
 104                         };
 105                 };
 106
 107                 periph_rst: reset-controller@10000010 {
 108                         compatible = "brcm,bcm6345-reset";
 109                         reg = <0x10000010 0x4>;
 110                         #reset-cells = <1>;
 111                 };
 112
 113                 ext_intc: interrupt-controller@10000018 {
 114                         #address-cells = <1>;
 115                         compatible = "brcm,bcm6345-ext-intc";
 116                         reg = <0x10000018 0x4>;
 117
 118                         interrupt-controller;
 119                         #interrupt-cells = <2>;
 120
 121                         interrupt-parent = <&periph_intc>;
 122                         interrupts = <BCM63268_IRQ_EXT0>,
 123                                      <BCM63268_IRQ_EXT1>,
 124                                      <BCM63268_IRQ_EXT2>,
 125                                      <BCM63268_IRQ_EXT3>;
 126                 };
 127
 128                 periph_intc: interrupt-controller@10000020 {
 129                         #address-cells = <1>;
 130                         compatible = "brcm,bcm6345-l1-intc";
 131                         reg = <0x10000020 0x20>,
 132                               <0x10000040 0x20>;
 133
 134                         interrupt-controller;
 135                         #interrupt-cells = <1>;
 136
 137                         interrupt-parent = <&cpu_intc>;
 138                         interrupts = <2>, <3>;
 139                 };
 140
 141                 wdt: watchdog@1000009c {
 142                         compatible = "brcm,bcm7038-wdt";
 143                         reg = <0x1000009c 0xc>;
 144
 145                         clocks = <&periph_osc>;
 146
 147                         timeout-sec = <30>;
 148                 };
 149
 150                 timer_clk: clock-controller@100000ac {
 151                         compatible = "brcm,bcm63268-timer-clocks";
 152                         reg = <0x100000ac 0x4>;
 153                         #clock-cells = <1>;
 154                         #reset-cells = <1>;
 155                 };
 156
 157                 gpio_cntl: syscon@100000c0 {
 158                         #address-cells = <1>;
 159                         #size-cells = <1>;
 160                         compatible = "brcm,bcm63268-gpio-sysctl",
 161                                      "syscon", "simple-mfd";
 162                         reg = <0x100000c0 0x80>;
 163                         ranges = <0 0x100000c0 0x80>;
 164                         native-endian;
 165
 166                         gpio: gpio@0 {
 167                                 compatible = "brcm,bcm63268-gpio";
 168                                 reg-names = "dirout", "dat";
 169                                 reg = <0x0 0x8>, <0x8 0x8>;
 170
 171                                 gpio-controller;
 172                                 gpio-ranges = <&pinctrl 0 0 52>;
 173                                 #gpio-cells = <2>;
 174                         };
 175
 176                         pinctrl: pinctrl@10 {
 177                                 compatible = "brcm,bcm63268-pinctrl";
 178                                 reg = <0x10 0x4>, <0x18 0x8>, <0x38 0x4>;
 179
 180                                 pinctrl_serial_led: serial_led-pins {
 181                                         pinctrl_serial_led_clk: serial_led_clk-pins {
 182                                                 function = "serial_led_clk";
 183                                                 pins = "gpio0";
 184                                         };
 185
 186                                         pinctrl_serial_led_data: serial_led_data-pins {
 187                                                 function = "serial_led_data";
 188                                                 pins = "gpio1";
 189                                         };
 190                                 };
 191
 192                                 pinctrl_hsspi_cs4: hsspi_cs4-pins {
 193                                         function = "hsspi_cs4";
 194                                         pins = "gpio16";
 195                                 };
 196
 197                                 pinctrl_hsspi_cs5: hsspi_cs5-pins {
 198                                         function = "hsspi_cs5";
 199                                         pins = "gpio17";
 200                                 };
 201
 202                                 pinctrl_hsspi_cs6: hsspi_cs6-pins {
 203                                         function = "hsspi_cs6";
 204                                         pins = "gpio8";
 205                                 };
 206
 207                                 pinctrl_hsspi_cs7: hsspi_cs7-pins {
 208                                         function = "hsspi_cs7";
 209                                         pins = "gpio9";
 210                                 };
 211
 212                                 pinctrl_adsl_spi: adsl_spi {
 213                                         pinctrl_adsl_spi_miso: adsl_spi_miso-pins {
 214                                                 function = "adsl_spi_miso";
 215                                                 pins = "gpio18";
 216                                         };
 217
 218                                         pinctrl_adsl_spi_mosi: adsl_spi_mosi-pins {
 219                                                 function = "adsl_spi_mosi";
 220                                                 pins = "gpio19";
 221                                         };
 222                                 };
 223
 224                                 pinctrl_vreq_clk: vreq_clk-pins {
 225                                         function = "vreq_clk";
 226                                         pins = "gpio22";
 227                                 };
 228
 229                                 pinctrl_pcie_clkreq_b: pcie_clkreq_b-pins {
 230                                         function = "pcie_clkreq_b";
 231                                         pins = "gpio23";
 232                                 };
 233
 234                                 pinctrl_robosw_led_clk: robosw_led_clk-pins {
 235                                         function = "robosw_led_clk";
 236                                         pins = "gpio30";
 237                                 };
 238
 239                                 pinctrl_robosw_led_data: robosw_led_data-pins {
 240                                         function = "robosw_led_data";
 241                                         pins = "gpio31";
 242                                 };
 243
 244                                 pinctrl_nand: nand-pins {
 245                                         function = "nand";
 246                                         group = "nand_grp";
 247                                 };
 248
 249                                 pinctrl_gpio35_alt: gpio35_alt-pins {
 250                                         function = "gpio35_alt";
 251                                         pin = "gpio35";
 252                                 };
 253
 254                                 pinctrl_dectpd: dectpd-pins {
 255                                         function = "dectpd";
 256                                         group = "dectpd_grp";
 257                                 };
 258
 259                                 pinctrl_vdsl_phy_override_0: vdsl_phy_override_0-pins {
 260                                         function = "vdsl_phy_override_0";
 261                                         group = "vdsl_phy_override_0_grp";
 262                                 };
 263
 264                                 pinctrl_vdsl_phy_override_1: vdsl_phy_override_1-pins {
 265                                         function = "vdsl_phy_override_1";
 266                                         group = "vdsl_phy_override_1_grp";
 267                                 };
 268
 269                                 pinctrl_vdsl_phy_override_2: vdsl_phy_override_2-pins {
 270                                         function = "vdsl_phy_override_2";
 271                                         group = "vdsl_phy_override_2_grp";
 272                                 };
 273
 274                                 pinctrl_vdsl_phy_override_3: vdsl_phy_override_3-pins {
 275                                         function = "vdsl_phy_override_3";
 276                                         group = "vdsl_phy_override_3_grp";
 277                                 };
 278
 279                                 pinctrl_dsl_gpio8: dsl_gpio8-pins {
 280                                         function = "dsl_gpio8";
 281                                         group = "dsl_gpio8";
 282                                 };
 283
 284                                 pinctrl_dsl_gpio9: dsl_gpio9-pins {
 285                                         function = "dsl_gpio9";
 286                                         group = "dsl_gpio9";
 287                                 };
 288                         };
 289                 };
 290
 291                 uart0: serial@10000180 {
 292                         compatible = "brcm,bcm6345-uart";
 293                         reg = <0x10000180 0x18>;
 294
 295                         interrupt-parent = <&periph_intc>;
 296                         interrupts = <BCM63268_IRQ_UART0>;
 297
 298                         clocks = <&periph_osc>;
 299                         clock-names = "periph";
 300
 301                         status = "disabled";
 302                 };
 303
 304                 uart1: serial@100001a0 {
 305                         compatible = "brcm,bcm6345-uart";
 306                         reg = <0x100001a0 0x18>;
 307
 308                         interrupt-parent = <&periph_intc>;
 309                         interrupts = <BCM63268_IRQ_UART1>;
 310
 311                         clocks = <&periph_osc>;
 312                         clock-names = "periph";
 313
 314                         status = "disabled";
 315                 };
 316
 317                 nflash: nand@10000200 {
 318                         #address-cells = <1>;
 319                         #size-cells = <0>;
 320                         compatible = "brcm,nand-bcm6368",
 321                                      "brcm,brcmnand-v4.0",
 322                                      "brcm,brcmnand";
 323                         reg = <0x10000200 0x180>,
 324                               <0x10000600 0x200>,
 325                               <0x100000b0 0x10>;
 326                         reg-names = "nand",
 327                                     "nand-cache",
 328                                     "nand-int-base";
 329
 330                         interrupt-parent = <&periph_intc>;
 331                         interrupts = <BCM63268_IRQ_NAND>;
 332
 333                         clocks = <&periph_clk BCM63268_CLK_NAND>;
 334                         clock-names = "nand";
 335
 336                         pinctrl-names = "default";
 337                         pinctrl-0 = <&pinctrl_nand>;
 338
 339                         status = "disabled";
 340                 };
 341
 342                 lsspi: spi@10000800 {
 343                         #address-cells = <1>;
 344                         #size-cells = <0>;
 345                         compatible = "brcm,bcm6358-spi";
 346                         reg = <0x10000800 0x70c>;
 347
 348                         interrupt-parent = <&periph_intc>;
 349                         interrupts = <BCM63268_IRQ_LSSPI>;
 350
 351                         clocks = <&periph_clk BCM63268_CLK_SPI>;
 352                         clock-names = "spi";
 353
 354                         resets = <&periph_rst BCM63268_RST_SPI>;
 355
 356                         status = "disabled";
 357                 };
 358
 359                 hsspi: spi@10001000 {
 360                         #address-cells = <1>;
 361                         #size-cells = <0>;
 362                         compatible = "brcm,bcm6328-hsspi";
 363                         reg = <0x10001000 0x600>;
 364
 365                         interrupt-parent = <&periph_intc>;
 366                         interrupts = <BCM63268_IRQ_HSSPI>;
 367
 368                         clocks = <&periph_clk BCM63268_CLK_HSSPI>,
 369                                  <&hsspi_osc>;
 370                         clock-names = "hsspi",
 371                                       "pll";
 372
 373                         resets = <&periph_rst BCM63268_RST_SPI>;
 374
 375                         status = "disabled";
 376                 };
 377
 378                 serdes_cntl: syscon@10001804 {
 379                         compatible = "syscon";
 380                         reg = <0x10001804 0x4>;
 381                         native-endian;
 382                 };
 383
 384                 periph_pwr: power-controller@1000184c {
 385                         compatible = "brcm,bcm63268-power-controller";
 386                         reg = <0x1000184c 0x4>;
 387                         #power-domain-cells = <1>;
 388                 };
 389
 390                 leds: led-controller@10001900 {
 391                         #address-cells = <1>;
 392                         #size-cells = <0>;
 393                         compatible = "brcm,bcm6328-leds";
 394                         reg = <0x10001900 0x24>;
 395
 396                         status = "disabled";
 397                 };
 398
 399                 ehci: usb@10002500 {
 400                         compatible = "brcm,bcm63268-ehci", "generic-ehci";
 401                         reg = <0x10002500 0x100>;
 402                         big-endian;
 403                         spurious-oc;
 404
 405                         interrupt-parent = <&periph_intc>;
 406                         interrupts = <BCM63268_IRQ_EHCI>;
 407
 408                         phys = <&usbh 0>;
 409                         phy-names = "usb";
 410
 411                         status = "disabled";
 412                 };
 413
 414                 ohci: usb@10002600 {
 415                         compatible = "brcm,bcm63268-ohci", "generic-ohci";
 416                         reg = <0x10002600 0x100>;
 417                         big-endian;
 418                         no-big-frame-no;
 419
 420                         interrupt-parent = <&periph_intc>;
 421                         interrupts = <BCM63268_IRQ_OHCI>;
 422
 423                         phys = <&usbh 0>;
 424                         phy-names = "usb";
 425
 426                         status = "disabled";
 427                 };
 428
 429                 usbh: usb-phy@10002700 {
 430                         compatible = "brcm,bcm63268-usbh-phy";
 431                         reg = <0x10002700 0x38>;
 432
 433                         #phy-cells = <1>;
 434
 435                         clocks = <&periph_clk BCM63268_CLK_USBH>,
 436                                  <&timer_clk BCM63268_TCLK_USB_REF>;
 437                         clock-names = "usbh",
 438                                       "usb_ref";
 439
 440                         power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_USBH>;
 441                         resets = <&periph_rst BCM63268_RST_USBH>;
 442
 443                         status = "disabled";
 444                 };
 445
 446                 random: rng@10002880 {
 447                         compatible = "brcm,bcm6368-rng";
 448                         reg = <0x10002880 0x14>;
 449
 450                         clocks = <&periph_clk BCM63268_CLK_IPSEC>;
 451                         clock-names = "ipsec";
 452
 453                         resets = <&periph_rst BCM63268_RST_IPSEC>;
 454
 455                         power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_IPSEC>;
 456                 };
 457
 458                 ethernet: ethernet@1000d800 {
 459                         compatible = "brcm,bcm63268-enetsw";
 460                         reg = <0x1000d800 0x80>,
 461                               <0x1000da00 0x80>,
 462                               <0x1000dc00 0x80>;
 463                         reg-names = "dma",
 464                                     "dma-channels",
 465                                     "dma-sram";
 466
 467                         interrupt-parent = <&periph_intc>;
 468                         interrupts = <BCM63268_IRQ_ENETSW_RX_DMA0>,
 469                                      <BCM63268_IRQ_ENETSW_TX_DMA0>;
 470                         interrupt-names = "rx",
 471                                           "tx";
 472
 473                         clocks = <&periph_clk BCM63268_CLK_GMAC>,
 474                                  <&periph_clk BCM63268_CLK_ROBOSW>,
 475                                  <&periph_clk BCM63268_CLK_ROBOSW250>,
 476                                  <&timer_clk BCM63268_TCLK_EPHY1>,
 477                                  <&timer_clk BCM63268_TCLK_EPHY2>,
 478                                  <&timer_clk BCM63268_TCLK_EPHY3>,
 479                                  <&timer_clk BCM63268_TCLK_GPHY1>;
 480
 481                         resets = <&periph_rst BCM63268_RST_ENETSW>,
 482                                  <&periph_rst BCM63268_RST_EPHY>,
 483                                  <&periph_rst BCM63268_RST_GPHY>;
 484
 485                         power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_ROBOSW>;
 486
 487                         dma-rx = <0>;
 488                         dma-tx = <1>;
 489
 490                         status = "disabled";
 491                 };
 492
 493                 pcie: pcie@106e0000 {
 494                         compatible = "brcm,bcm6328-pcie";
 495                         reg = <0x106e0000 0x10000>;
 496                         #address-cells = <3>;
 497                         #size-cells = <2>;
 498
 499                         device_type = "pci";
 500                         bus-range = <0x00 0x01>;
 501                         ranges = <0x2000000 0 0x11000000 0x11000000 0 0xf00000>;
 502                         linux,pci-probe-only = <1>;
 503
 504                         interrupt-parent = <&periph_intc>;
 505                         interrupts = <BCM63268_IRQ_PCIE_RC>;
 506
 507                         clocks = <&periph_clk BCM63268_CLK_PCIE>;
 508                         clock-names = "pcie";
 509
 510                         resets = <&periph_rst BCM63268_RST_PCIE>,
 511                                  <&periph_rst BCM63268_RST_PCIE_EXT>,
 512                                  <&periph_rst BCM63268_RST_PCIE_CORE>,
 513                                  <&periph_rst BCM63268_RST_PCIE_HARD>;
 514                         reset-names = "pcie",
 515                                       "pcie-ext",
 516                                       "pcie-core",
 517                                       "pcie-hard";
 518
 519                         power-domains = <&periph_pwr BCM63268_POWER_DOMAIN_PCIE>;
 520
 521                         brcm,serdes = <&serdes_cntl>;
 522
 523                         status = "disabled";
 524                 };
 525
 526                 switch0: switch@10700000 {
 527                         #address-cells = <1>;
 528                         #size-cells = <0>;
 529                         compatible = "brcm,bcm63268-switch";
 530                         reg = <0x10700000 0x8000>;
 531                         big-endian;
 532
 533                         ports {
 534                                 #address-cells = <1>;
 535                                 #size-cells = <0>;
 536
 537                                 port@8 {
 538                                         reg = <8>;
 539
 540                                         phy-mode = "internal";
 541                                         ethernet = <&ethernet>;
 542
 543                                         fixed-link {
 544                                                 speed = <1000>;
 545                                                 full-duplex;
 546                                         };
 547                                 };
 548                         };
 549                 };
 550
 551                 mdio: mdio@107000b0 {
 552                         #address-cells = <1>;
 553                         #size-cells = <0>;
 554                         compatible = "brcm,bcm6368-mdio-mux";
 555                         reg = <0x107000b0 0x8>;
 556
 557                         mdio_int: mdio@0 {
 558                                 #address-cells = <1>;
 559                                 #size-cells = <0>;
 560                                 reg = <0>;
 561
 562                                 phy1: ethernet-phy@1 {
 563                                         compatible = "ethernet-phy-ieee802.3-c22";
 564                                         reg = <1>;
 565                                 };
 566
 567                                 phy2: ethernet-phy@2 {
 568                                         compatible = "ethernet-phy-ieee802.3-c22";
 569                                         reg = <2>;
 570                                 };
 571
 572                                 phy3: ethernet-phy@3 {
 573                                         compatible = "ethernet-phy-ieee802.3-c22";
 574                                         reg = <3>;
 575                                 };
 576
 577                                 phy4: ethernet-phy@4 {
 578                                         compatible = "ethernet-phy-ieee802.3-c22";
 579                                         reg = <4>;
 580                                 };
 581                         };
 582
 583                         mdio_ext: mdio@1 {
 584                                 #address-cells = <1>;
 585                                 #size-cells = <0>;
 586                                 reg = <1>;
 587                         };
 588                 };
 589         };
 590 };