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ipq806x: fix wrong definition for tsense calib
[openwrt/staging/dedeckeh.git] / target / linux / ipq806x / files-4.19 / arch / arm / boot / dts / qcom-ipq8064.dtsi
1 /dts-v1/;
2
3 #include "skeleton.dtsi"
4 #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
5 #include <dt-bindings/mfd/qcom-rpm.h>
6 #include <dt-bindings/clock/qcom,rpmcc.h>
7 #include <dt-bindings/clock/qcom,lcc-ipq806x.h>
8 #include <dt-bindings/soc/qcom,gsbi.h>
9 #include <dt-bindings/reset/qcom,gcc-ipq806x.h>
10 #include <dt-bindings/interrupt-controller/arm-gic.h>
11 #include <dt-bindings/gpio/gpio.h>
12
13 / {
14 model = "Qualcomm IPQ8064";
15 compatible = "qcom,ipq8064";
16 interrupt-parent = <&intc>;
17
18 cpus {
19 #address-cells = <1>;
20 #size-cells = <0>;
21
22 cpu0: cpu@0 {
23 compatible = "qcom,krait";
24 enable-method = "qcom,kpss-acc-v1";
25 device_type = "cpu";
26 reg = <0>;
27 next-level-cache = <&L2>;
28 qcom,acc = <&acpu0_aux>;
29 qcom,saw = <&saw0>;
30 clocks = <&kraitcc 0>, <&kraitcc 4>;
31 clock-names = "cpu", "l2";
32 clock-latency = <100000>;
33 cpu-supply = <&smb208_s2a>;
34 operating-points-v2 = <&opp_table0>;
35 voltage-tolerance = <5>;
36 cooling-min-state = <0>;
37 cooling-max-state = <10>;
38 #cooling-cells = <2>;
39 cpu-idle-states = <&CPU_SPC>;
40 };
41
42 cpu1: cpu@1 {
43 compatible = "qcom,krait";
44 enable-method = "qcom,kpss-acc-v1";
45 device_type = "cpu";
46 reg = <1>;
47 next-level-cache = <&L2>;
48 qcom,acc = <&acpu1_aux>;
49 qcom,saw = <&saw1>;
50 clocks = <&kraitcc 1>, <&kraitcc 4>;
51 clock-names = "cpu", "l2";
52 clock-latency = <100000>;
53 cpu-supply = <&smb208_s2b>;
54 operating-points-v2 = <&opp_table0>;
55 voltage-tolerance = <5>;
56 cooling-min-state = <0>;
57 cooling-max-state = <10>;
58 #cooling-cells = <2>;
59 cpu-idle-states = <&CPU_SPC>;
60 };
61
62 L2: l2-cache {
63 compatible = "cache";
64 cache-level = <2>;
65 qcom,saw = <&saw_l2>;
66 };
67
68 qcom,l2 {
69 qcom,l2-rates = <384000000 1000000000 1200000000>;
70 };
71
72 idle-states {
73 CPU_SPC: spc {
74 compatible = "qcom,idle-state-spc",
75 "arm,idle-state";
76 status = "okay";
77 entry-latency-us = <400>;
78 exit-latency-us = <900>;
79 min-residency-us = <3000>;
80 };
81 };
82 };
83
84 opp_table0: opp_table0 {
85 compatible = "operating-points-v2-qcom-cpu";
86 nvmem-cells = <&speedbin_efuse>;
87
88 opp-384000000 {
89 opp-hz = /bits/ 64 <384000000>;
90 opp-microvolt-speed0-pvs0-v0 = <1000000>;
91 opp-microvolt-speed0-pvs1-v0 = <925000>;
92 opp-microvolt-speed0-pvs2-v0 = <875000>;
93 opp-microvolt-speed0-pvs3-v0 = <800000>;
94 opp-supported-hw = <0x1>;
95 clock-latency-ns = <100000>;
96 };
97
98 opp-600000000 {
99 opp-hz = /bits/ 64 <600000000>;
100 opp-microvolt-speed0-pvs0-v0 = <1050000>;
101 opp-microvolt-speed0-pvs1-v0 = <975000>;
102 opp-microvolt-speed0-pvs2-v0 = <925000>;
103 opp-microvolt-speed0-pvs3-v0 = <850000>;
104 opp-supported-hw = <0x1>;
105 clock-latency-ns = <100000>;
106 };
107
108 opp-800000000 {
109 opp-hz = /bits/ 64 <800000000>;
110 opp-microvolt-speed0-pvs0-v0 = <1100000>;
111 opp-microvolt-speed0-pvs1-v0 = <1025000>;
112 opp-microvolt-speed0-pvs2-v0 = <995000>;
113 opp-microvolt-speed0-pvs3-v0 = <900000>;
114 opp-supported-hw = <0x1>;
115 clock-latency-ns = <100000>;
116 };
117
118 opp-1000000000 {
119 opp-hz = /bits/ 64 <1000000000>;
120 opp-microvolt-speed0-pvs0-v0 = <1150000>;
121 opp-microvolt-speed0-pvs1-v0 = <1075000>;
122 opp-microvolt-speed0-pvs2-v0 = <1025000>;
123 opp-microvolt-speed0-pvs3-v0 = <950000>;
124 opp-supported-hw = <0x1>;
125 clock-latency-ns = <100000>;
126 };
127
128 opp-1200000000 {
129 opp-hz = /bits/ 64 <1200000000>;
130 opp-microvolt-speed0-pvs0-v0 = <1200000>;
131 opp-microvolt-speed0-pvs1-v0 = <1125000>;
132 opp-microvolt-speed0-pvs2-v0 = <1075000>;
133 opp-microvolt-speed0-pvs3-v0 = <1000000>;
134 opp-supported-hw = <0x1>;
135 clock-latency-ns = <100000>;
136 };
137
138 opp-1400000000 {
139 opp-hz = /bits/ 64 <1400000000>;
140 opp-microvolt-speed0-pvs0-v0 = <1250000>;
141 opp-microvolt-speed0-pvs1-v0 = <1175000>;
142 opp-microvolt-speed0-pvs2-v0 = <1125000>;
143 opp-microvolt-speed0-pvs3-v0 = <1050000>;
144 opp-supported-hw = <0x1>;
145 clock-latency-ns = <100000>;
146 };
147
148 };
149
150 thermal-zones {
151 tsens_tz_sensor0 {
152 polling-delay-passive = <0>;
153 polling-delay = <0>;
154 thermal-sensors = <&tsens 0>;
155
156 trips {
157 cpu-critical-hi {
158 temperature = <125000>;
159 hysteresis = <2000>;
160 type = "critical_high";
161 };
162
163 cpu-config-hi {
164 temperature = <105000>;
165 hysteresis = <2000>;
166 type = "configurable_hi";
167 };
168
169 cpu-config-lo {
170 temperature = <95000>;
171 hysteresis = <2000>;
172 type = "configurable_lo";
173 };
174
175 cpu-critical-low {
176 temperature = <0>;
177 hysteresis = <2000>;
178 type = "critical_low";
179 };
180 };
181 };
182
183 tsens_tz_sensor1 {
184 polling-delay-passive = <0>;
185 polling-delay = <0>;
186 thermal-sensors = <&tsens 1>;
187
188 trips {
189 cpu-critical-hi {
190 temperature = <125000>;
191 hysteresis = <2000>;
192 type = "critical_high";
193 };
194
195 cpu-config-hi {
196 temperature = <105000>;
197 hysteresis = <2000>;
198 type = "configurable_hi";
199 };
200
201 cpu-config-lo {
202 temperature = <95000>;
203 hysteresis = <2000>;
204 type = "configurable_lo";
205 };
206
207 cpu-critical-low {
208 temperature = <0>;
209 hysteresis = <2000>;
210 type = "critical_low";
211 };
212 };
213 };
214
215 tsens_tz_sensor2 {
216 polling-delay-passive = <0>;
217 polling-delay = <0>;
218 thermal-sensors = <&tsens 2>;
219
220 trips {
221 cpu-critical-hi {
222 temperature = <125000>;
223 hysteresis = <2000>;
224 type = "critical_high";
225 };
226
227 cpu-config-hi {
228 temperature = <105000>;
229 hysteresis = <2000>;
230 type = "configurable_hi";
231 };
232
233 cpu-config-lo {
234 temperature = <95000>;
235 hysteresis = <2000>;
236 type = "configurable_lo";
237 };
238
239 cpu-critical-low {
240 temperature = <0>;
241 hysteresis = <2000>;
242 type = "critical_low";
243 };
244 };
245 };
246
247 tsens_tz_sensor3 {
248 polling-delay-passive = <0>;
249 polling-delay = <0>;
250 thermal-sensors = <&tsens 3>;
251
252 trips {
253 cpu-critical-hi {
254 temperature = <125000>;
255 hysteresis = <2000>;
256 type = "critical_high";
257 };
258
259 cpu-config-hi {
260 temperature = <105000>;
261 hysteresis = <2000>;
262 type = "configurable_hi";
263 };
264
265 cpu-config-lo {
266 temperature = <95000>;
267 hysteresis = <2000>;
268 type = "configurable_lo";
269 };
270
271 cpu-critical-low {
272 temperature = <0>;
273 hysteresis = <2000>;
274 type = "critical_low";
275 };
276 };
277 };
278
279 tsens_tz_sensor4 {
280 polling-delay-passive = <0>;
281 polling-delay = <0>;
282 thermal-sensors = <&tsens 4>;
283
284 trips {
285 cpu-critical-hi {
286 temperature = <125000>;
287 hysteresis = <2000>;
288 type = "critical_high";
289 };
290
291 cpu-config-hi {
292 temperature = <105000>;
293 hysteresis = <2000>;
294 type = "configurable_hi";
295 };
296
297 cpu-config-lo {
298 temperature = <95000>;
299 hysteresis = <2000>;
300 type = "configurable_lo";
301 };
302
303 cpu-critical-low {
304 temperature = <0>;
305 hysteresis = <2000>;
306 type = "critical_low";
307 };
308 };
309 };
310
311 tsens_tz_sensor5 {
312 polling-delay-passive = <0>;
313 polling-delay = <0>;
314 thermal-sensors = <&tsens 5>;
315
316 trips {
317 cpu-critical-hi {
318 temperature = <125000>;
319 hysteresis = <2000>;
320 type = "critical_high";
321 };
322
323 cpu-config-hi {
324 temperature = <105000>;
325 hysteresis = <2000>;
326 type = "configurable_hi";
327 };
328
329 cpu-config-lo {
330 temperature = <95000>;
331 hysteresis = <2000>;
332 type = "configurable_lo";
333 };
334
335 cpu-critical-low {
336 temperature = <0>;
337 hysteresis = <2000>;
338 type = "critical_low";
339 };
340 };
341 };
342
343 tsens_tz_sensor6 {
344 polling-delay-passive = <0>;
345 polling-delay = <0>;
346 thermal-sensors = <&tsens 6>;
347
348 trips {
349 cpu-critical-hi {
350 temperature = <125000>;
351 hysteresis = <2000>;
352 type = "critical_high";
353 };
354
355 cpu-config-hi {
356 temperature = <105000>;
357 hysteresis = <2000>;
358 type = "configurable_hi";
359 };
360
361 cpu-config-lo {
362 temperature = <95000>;
363 hysteresis = <2000>;
364 type = "configurable_lo";
365 };
366
367 cpu-critical-low {
368 temperature = <0>;
369 hysteresis = <2000>;
370 type = "critical_low";
371 };
372 };
373 };
374
375 tsens_tz_sensor7 {
376 polling-delay-passive = <0>;
377 polling-delay = <0>;
378 thermal-sensors = <&tsens 7>;
379
380 trips {
381 cpu-critical-hi {
382 temperature = <125000>;
383 hysteresis = <2000>;
384 type = "critical_high";
385 };
386
387 cpu-config-hi {
388 temperature = <105000>;
389 hysteresis = <2000>;
390 type = "configurable_hi";
391 };
392
393 cpu-config-lo {
394 temperature = <95000>;
395 hysteresis = <2000>;
396 type = "configurable_lo";
397 };
398
399 cpu-critical-low {
400 temperature = <0>;
401 hysteresis = <2000>;
402 type = "critical_low";
403 };
404 };
405 };
406
407 tsens_tz_sensor8 {
408 polling-delay-passive = <0>;
409 polling-delay = <0>;
410 thermal-sensors = <&tsens 8>;
411
412 trips {
413 cpu-critical-hi {
414 temperature = <125000>;
415 hysteresis = <2000>;
416 type = "critical_high";
417 };
418
419 cpu-config-hi {
420 temperature = <105000>;
421 hysteresis = <2000>;
422 type = "configurable_hi";
423 };
424
425 cpu-config-lo {
426 temperature = <95000>;
427 hysteresis = <2000>;
428 type = "configurable_lo";
429 };
430
431 cpu-critical-low {
432 temperature = <0>;
433 hysteresis = <2000>;
434 type = "critical_low";
435 };
436 };
437 };
438
439 tsens_tz_sensor9 {
440 polling-delay-passive = <0>;
441 polling-delay = <0>;
442 thermal-sensors = <&tsens 9>;
443
444 trips {
445 cpu-critical-hi {
446 temperature = <125000>;
447 hysteresis = <2000>;
448 type = "critical_high";
449 };
450
451 cpu-config-hi {
452 temperature = <105000>;
453 hysteresis = <2000>;
454 type = "configurable_hi";
455 };
456
457 cpu-config-lo {
458 temperature = <95000>;
459 hysteresis = <2000>;
460 type = "configurable_lo";
461 };
462
463 cpu-critical-low {
464 temperature = <0>;
465 hysteresis = <2000>;
466 type = "critical_low";
467 };
468 };
469 };
470
471 tsens_tz_sensor10 {
472 polling-delay-passive = <0>;
473 polling-delay = <0>;
474 thermal-sensors = <&tsens 10>;
475
476 trips {
477 cpu-critical-hi {
478 temperature = <125000>;
479 hysteresis = <2000>;
480 type = "critical_high";
481 };
482
483 cpu-config-hi {
484 temperature = <105000>;
485 hysteresis = <2000>;
486 type = "configurable_hi";
487 };
488
489 cpu-config-lo {
490 temperature = <95000>;
491 hysteresis = <2000>;
492 type = "configurable_lo";
493 };
494
495 cpu-critical-low {
496 temperature = <0>;
497 hysteresis = <2000>;
498 type = "critical_low";
499 };
500 };
501 };
502 };
503
504 cpu-pmu {
505 compatible = "qcom,krait-pmu";
506 interrupts = <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
507 IRQ_TYPE_LEVEL_HIGH)>;
508 };
509
510 reserved-memory {
511 #address-cells = <1>;
512 #size-cells = <1>;
513 ranges;
514
515 nss@40000000 {
516 reg = <0x40000000 0x1000000>;
517 no-map;
518 };
519
520 smem: smem@41000000 {
521 reg = <0x41000000 0x200000>;
522 no-map;
523 };
524 };
525
526 clocks {
527 cxo_board {
528 compatible = "fixed-clock";
529 #clock-cells = <0>;
530 clock-frequency = <25000000>;
531 };
532
533 pxo_board {
534 compatible = "fixed-clock";
535 #clock-cells = <0>;
536 clock-frequency = <25000000>;
537 };
538
539 sleep_clk: sleep_clk {
540 compatible = "fixed-clock";
541 clock-frequency = <32768>;
542 #clock-cells = <0>;
543 };
544 };
545
546 firmware {
547 scm {
548 compatible = "qcom,scm-ipq806x";
549 };
550 };
551
552 soc: soc {
553 #address-cells = <1>;
554 #size-cells = <1>;
555 ranges;
556 compatible = "simple-bus";
557
558 lpass@28100000 {
559 compatible = "qcom,lpass-cpu";
560 status = "disabled";
561 clocks = <&lcc AHBIX_CLK>,
562 <&lcc MI2S_OSR_CLK>,
563 <&lcc MI2S_BIT_CLK>;
564 clock-names = "ahbix-clk",
565 "mi2s-osr-clk",
566 "mi2s-bit-clk";
567 interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
568 interrupt-names = "lpass-irq-lpaif";
569 reg = <0x28100000 0x10000>;
570 reg-names = "lpass-lpaif";
571 };
572
573 qfprom: qfprom@700000 {
574 compatible = "qcom,qfprom", "syscon";
575 reg = <0x700000 0x1000>;
576 #address-cells = <1>;
577 #size-cells = <1>;
578 status = "okay";
579 tsens_calib: calib@400 {
580 reg = <0x400 0xb>;
581 };
582 tsens_backup: backup@410 {
583 reg = <0x410 0xb>;
584 };
585 speedbin_efuse: speedbin@0c0 {
586 reg = <0x0c0 0x4>;
587 };
588 };
589
590 rpm@108000 {
591 compatible = "qcom,rpm-ipq8064";
592 reg = <0x108000 0x1000>;
593 qcom,ipc = <&l2cc 0x8 2>;
594
595 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
596 <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
597 <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
598 interrupt-names = "ack",
599 "err",
600 "wakeup";
601
602 clocks = <&gcc RPM_MSG_RAM_H_CLK>;
603 clock-names = "ram";
604
605 #address-cells = <1>;
606 #size-cells = <0>;
607
608 rpmcc: clock-controller {
609 compatible = "qcom,rpmcc-ipq806x", "qcom,rpmcc";
610 #clock-cells = <1>;
611 };
612
613 regulators {
614 compatible = "qcom,rpm-smb208-regulators";
615
616 smb208_s1a: s1a {
617 regulator-min-microvolt = <1050000>;
618 regulator-max-microvolt = <1150000>;
619
620 qcom,switch-mode-frequency = <1200000>;
621
622 };
623
624 smb208_s1b: s1b {
625 regulator-min-microvolt = <1050000>;
626 regulator-max-microvolt = <1150000>;
627
628 qcom,switch-mode-frequency = <1200000>;
629 };
630
631 smb208_s2a: s2a {
632 regulator-min-microvolt = < 800000>;
633 regulator-max-microvolt = <1250000>;
634
635 qcom,switch-mode-frequency = <1200000>;
636 };
637
638 smb208_s2b: s2b {
639 regulator-min-microvolt = < 800000>;
640 regulator-max-microvolt = <1250000>;
641
642 qcom,switch-mode-frequency = <1200000>;
643 };
644 };
645 };
646
647 rng@1a500000 {
648 compatible = "qcom,prng";
649 reg = <0x1a500000 0x200>;
650 clocks = <&gcc PRNG_CLK>;
651 clock-names = "core";
652 };
653
654 qcom_pinmux: pinmux@800000 {
655 compatible = "qcom,ipq8064-pinctrl";
656 reg = <0x800000 0x4000>;
657
658 gpio-controller;
659 #gpio-cells = <2>;
660 interrupt-controller;
661 #interrupt-cells = <2>;
662 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
663
664 pcie0_pins: pcie0_pinmux {
665 mux {
666 pins = "gpio3";
667 function = "pcie1_rst";
668 drive-strength = <12>;
669 bias-disable;
670 };
671 };
672
673 pcie1_pins: pcie1_pinmux {
674 mux {
675 pins = "gpio48";
676 function = "pcie2_rst";
677 drive-strength = <12>;
678 bias-disable;
679 };
680 };
681
682 pcie2_pins: pcie2_pinmux {
683 mux {
684 pins = "gpio63";
685 function = "pcie3_rst";
686 drive-strength = <12>;
687 bias-disable;
688 output-low;
689 };
690 };
691
692 spi_pins: spi_pins {
693 mux {
694 pins = "gpio18", "gpio19", "gpio21";
695 function = "gsbi5";
696 drive-strength = <10>;
697 bias-none;
698 };
699 };
700
701 leds_pins: leds_pins {
702 mux {
703 pins = "gpio7", "gpio8", "gpio9",
704 "gpio26", "gpio53";
705 function = "gpio";
706 drive-strength = <2>;
707 bias-pull-down;
708 output-low;
709 };
710 };
711
712 buttons_pins: buttons_pins {
713 mux {
714 pins = "gpio54";
715 drive-strength = <2>;
716 bias-pull-up;
717 };
718 };
719 };
720
721 intc: interrupt-controller@2000000 {
722 compatible = "qcom,msm-qgic2";
723 interrupt-controller;
724 #interrupt-cells = <3>;
725 reg = <0x02000000 0x1000>,
726 <0x02002000 0x1000>;
727 };
728
729 timer@200a000 {
730 compatible = "qcom,kpss-timer",
731 "qcom,kpss-wdt-ipq8064", "qcom,msm-timer";
732 interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(2) |
733 IRQ_TYPE_EDGE_RISING)>,
734 <GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(2) |
735 IRQ_TYPE_EDGE_RISING)>,
736 <GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(2) |
737 IRQ_TYPE_EDGE_RISING)>,
738 <GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(2) |
739 IRQ_TYPE_EDGE_RISING)>,
740 <GIC_PPI 5 (GIC_CPU_MASK_SIMPLE(2) |
741 IRQ_TYPE_EDGE_RISING)>;
742 reg = <0x0200a000 0x100>;
743 clock-frequency = <25000000>,
744 <32768>;
745 clocks = <&sleep_clk>;
746 clock-names = "sleep";
747 cpu-offset = <0x80000>;
748 };
749
750 acpu0_aux: clock-controller@2088000 {
751 compatible = "qcom,kpss-acc-v1";
752 reg = <0x02088000 0x1000>, <0x02008000 0x1000>;
753 clock-output-names = "acpu0_aux";
754 };
755
756 acpu1_aux: clock-controller@2098000 {
757 compatible = "qcom,kpss-acc-v1";
758 reg = <0x02098000 0x1000>, <0x02008000 0x1000>;
759 clock-output-names = "acpu1_aux";
760 };
761
762 l2cc: clock-controller@2011000 {
763 compatible = "qcom,kpss-gcc", "syscon";
764 reg = <0x2011000 0x1000>;
765 clock-output-names = "acpu_l2_aux";
766 };
767
768 kraitcc: clock-controller {
769 compatible = "qcom,krait-cc-v1";
770 #clock-cells = <1>;
771 };
772
773 saw0: regulator@2089000 {
774 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
775 reg = <0x02089000 0x1000>, <0x02009000 0x1000>;
776 regulator;
777 };
778
779 saw1: regulator@2099000 {
780 compatible = "qcom,saw2", "qcom,apq8064-saw2-v1.1-cpu", "syscon";
781 reg = <0x02099000 0x1000>, <0x02009000 0x1000>;
782 regulator;
783 };
784
785 saw_l2: regulator@02012000 {
786 compatible = "qcom,saw2", "syscon";
787 reg = <0x02012000 0x1000>;
788 regulator;
789 };
790
791 sic_non_secure: sic-non-secure@12100000 {
792 compatible = "syscon";
793 reg = <0x12100000 0x10000>;
794 };
795
796 gsbi2: gsbi@12480000 {
797 compatible = "qcom,gsbi-v1.0.0";
798 cell-index = <2>;
799 reg = <0x12480000 0x100>;
800 clocks = <&gcc GSBI2_H_CLK>;
801 clock-names = "iface";
802 #address-cells = <1>;
803 #size-cells = <1>;
804 ranges;
805 status = "disabled";
806
807 syscon-tcsr = <&tcsr>;
808
809 uart2: serial@12490000 {
810 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
811 reg = <0x12490000 0x1000>,
812 <0x12480000 0x1000>;
813 interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>;
814 clocks = <&gcc GSBI2_UART_CLK>, <&gcc GSBI2_H_CLK>;
815 clock-names = "core", "iface";
816 status = "disabled";
817 };
818
819 i2c@124a0000 {
820 compatible = "qcom,i2c-qup-v1.1.1";
821 reg = <0x124a0000 0x1000>;
822 interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>;
823
824 clocks = <&gcc GSBI2_QUP_CLK>, <&gcc GSBI2_H_CLK>;
825 clock-names = "core", "iface";
826 status = "disabled";
827
828 #address-cells = <1>;
829 #size-cells = <0>;
830 };
831
832 };
833
834 gsbi4: gsbi@16300000 {
835 compatible = "qcom,gsbi-v1.0.0";
836 cell-index = <4>;
837 reg = <0x16300000 0x100>;
838 clocks = <&gcc GSBI4_H_CLK>;
839 clock-names = "iface";
840 #address-cells = <1>;
841 #size-cells = <1>;
842 ranges;
843 status = "disabled";
844
845 syscon-tcsr = <&tcsr>;
846
847 gsbi4_serial: serial@16340000 {
848 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
849 reg = <0x16340000 0x1000>,
850 <0x16300000 0x1000>;
851 interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
852 clocks = <&gcc GSBI4_UART_CLK>, <&gcc GSBI4_H_CLK>;
853 clock-names = "core", "iface";
854 status = "disabled";
855 };
856
857 i2c@16380000 {
858 compatible = "qcom,i2c-qup-v1.1.1";
859 reg = <0x16380000 0x1000>;
860 interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
861
862 clocks = <&gcc GSBI4_QUP_CLK>, <&gcc GSBI4_H_CLK>;
863 clock-names = "core", "iface";
864 status = "disabled";
865
866 #address-cells = <1>;
867 #size-cells = <0>;
868 };
869 };
870
871 gsbi5: gsbi@1a200000 {
872 compatible = "qcom,gsbi-v1.0.0";
873 cell-index = <5>;
874 reg = <0x1a200000 0x100>;
875 clocks = <&gcc GSBI5_H_CLK>;
876 clock-names = "iface";
877 #address-cells = <1>;
878 #size-cells = <1>;
879 ranges;
880 status = "disabled";
881
882 syscon-tcsr = <&tcsr>;
883
884 uart5: serial@1a240000 {
885 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
886 reg = <0x1a240000 0x1000>,
887 <0x1a200000 0x1000>;
888 interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
889 clocks = <&gcc GSBI5_UART_CLK>, <&gcc GSBI5_H_CLK>;
890 clock-names = "core", "iface";
891 status = "disabled";
892 };
893
894 i2c@1a280000 {
895 compatible = "qcom,i2c-qup-v1.1.1";
896 reg = <0x1a280000 0x1000>;
897 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
898
899 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
900 clock-names = "core", "iface";
901 status = "disabled";
902
903 #address-cells = <1>;
904 #size-cells = <0>;
905 };
906
907 spi@1a280000 {
908 compatible = "qcom,spi-qup-v1.1.1";
909 reg = <0x1a280000 0x1000>;
910 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
911
912 clocks = <&gcc GSBI5_QUP_CLK>, <&gcc GSBI5_H_CLK>;
913 clock-names = "core", "iface";
914 status = "disabled";
915
916 #address-cells = <1>;
917 #size-cells = <0>;
918 };
919 };
920
921 gsbi7: gsbi@16600000 {
922 status = "disabled";
923 compatible = "qcom,gsbi-v1.0.0";
924 cell-index = <7>;
925 reg = <0x16600000 0x100>;
926 clocks = <&gcc GSBI7_H_CLK>;
927 clock-names = "iface";
928 #address-cells = <1>;
929 #size-cells = <1>;
930 ranges;
931 syscon-tcsr = <&tcsr>;
932
933 gsbi7_serial: serial@16640000 {
934 compatible = "qcom,msm-uartdm-v1.3", "qcom,msm-uartdm";
935 reg = <0x16640000 0x1000>,
936 <0x16600000 0x1000>;
937 interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
938 clocks = <&gcc GSBI7_UART_CLK>, <&gcc GSBI7_H_CLK>;
939 clock-names = "core", "iface";
940 status = "disabled";
941 };
942 };
943
944 sata_phy: sata-phy@1b400000 {
945 compatible = "qcom,ipq806x-sata-phy";
946 reg = <0x1b400000 0x200>;
947
948 clocks = <&gcc SATA_PHY_CFG_CLK>;
949 clock-names = "cfg";
950
951 #phy-cells = <0>;
952 status = "disabled";
953 };
954
955 sata: sata@29000000 {
956 compatible = "qcom,ipq806x-ahci", "generic-ahci";
957 reg = <0x29000000 0x180>;
958
959 ports-implemented = <0x1>;
960
961 interrupts = <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>;
962
963 clocks = <&gcc SFAB_SATA_S_H_CLK>,
964 <&gcc SATA_H_CLK>,
965 <&gcc SATA_A_CLK>,
966 <&gcc SATA_RXOOB_CLK>,
967 <&gcc SATA_PMALIVE_CLK>;
968 clock-names = "slave_face", "iface", "core",
969 "rxoob", "pmalive";
970
971 assigned-clocks = <&gcc SATA_RXOOB_CLK>, <&gcc SATA_PMALIVE_CLK>;
972 assigned-clock-rates = <100000000>, <100000000>;
973
974 phys = <&sata_phy>;
975 phy-names = "sata-phy";
976 status = "disabled";
977 };
978
979 qcom,ssbi@500000 {
980 compatible = "qcom,ssbi";
981 reg = <0x00500000 0x1000>;
982 qcom,controller-type = "pmic-arbiter";
983 };
984
985 gcc: clock-controller@900000 {
986 compatible = "qcom,gcc-ipq8064";
987 reg = <0x00900000 0x4000>;
988 #clock-cells = <1>;
989 #reset-cells = <1>;
990 #power-domain-cells = <1>;
991 };
992
993 tsens: thermal-sensor@900000 {
994 compatible = "qcom,ipq8064-tsens";
995 reg = <0x900000 0x3680>;
996 nvmem-cells = <&tsens_calib>, <&tsens_backup>;
997 nvmem-cell-names = "calib", "calib_backup";
998 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
999 #thermal-sensor-cells = <1>;
1000 };
1001
1002 tcsr: syscon@1a400000 {
1003 compatible = "qcom,tcsr-ipq8064", "syscon";
1004 reg = <0x1a400000 0x100>;
1005 };
1006
1007 lcc: clock-controller@28000000 {
1008 compatible = "qcom,lcc-ipq8064";
1009 reg = <0x28000000 0x1000>;
1010 #clock-cells = <1>;
1011 #reset-cells = <1>;
1012 };
1013
1014 sfpb_mutex_block: syscon@1200600 {
1015 compatible = "syscon";
1016 reg = <0x01200600 0x100>;
1017 };
1018
1019 hs_phy_0: hs_phy_0 {
1020 compatible = "qcom,dwc3-hs-usb-phy";
1021 regmap = <&usb3_0>;
1022 clocks = <&gcc USB30_0_UTMI_CLK>;
1023 clock-names = "ref";
1024 #phy-cells = <0>;
1025 };
1026
1027 ss_phy_0: ss_phy_0 {
1028 compatible = "qcom,dwc3-ss-usb-phy";
1029 regmap = <&usb3_0>;
1030 clocks = <&gcc USB30_0_MASTER_CLK>;
1031 clock-names = "ref";
1032 #phy-cells = <0>;
1033 };
1034
1035 usb3_0: usb3@110f8800 {
1036 compatible = "qcom,dwc3", "syscon";
1037 #address-cells = <1>;
1038 #size-cells = <1>;
1039 reg = <0x110f8800 0x8000>;
1040 clocks = <&gcc USB30_0_MASTER_CLK>;
1041 clock-names = "core";
1042
1043 ranges;
1044
1045 resets = <&gcc USB30_0_MASTER_RESET>;
1046 reset-names = "master";
1047
1048 status = "disabled";
1049
1050 dwc3_0: dwc3@11000000 {
1051 compatible = "snps,dwc3";
1052 reg = <0x11000000 0xcd00>;
1053 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
1054 phys = <&hs_phy_0>, <&ss_phy_0>;
1055 phy-names = "usb2-phy", "usb3-phy";
1056 dr_mode = "host";
1057 snps,dis_u3_susphy_quirk;
1058 };
1059 };
1060
1061 hs_phy_1: hs_phy_1 {
1062 compatible = "qcom,dwc3-hs-usb-phy";
1063 regmap = <&usb3_1>;
1064 clocks = <&gcc USB30_1_UTMI_CLK>;
1065 clock-names = "ref";
1066 #phy-cells = <0>;
1067 };
1068
1069 ss_phy_1: ss_phy_1 {
1070 compatible = "qcom,dwc3-ss-usb-phy";
1071 regmap = <&usb3_1>;
1072 clocks = <&gcc USB30_1_MASTER_CLK>;
1073 clock-names = "ref";
1074 #phy-cells = <0>;
1075 };
1076
1077 usb3_1: usb3@100f8800 {
1078 compatible = "qcom,dwc3", "syscon";
1079 #address-cells = <1>;
1080 #size-cells = <1>;
1081 reg = <0x100f8800 0x8000>;
1082 clocks = <&gcc USB30_1_MASTER_CLK>;
1083 clock-names = "core";
1084
1085 ranges;
1086
1087 resets = <&gcc USB30_1_MASTER_RESET>;
1088 reset-names = "master";
1089
1090 status = "disabled";
1091
1092 dwc3_1: dwc3@10000000 {
1093 compatible = "snps,dwc3";
1094 reg = <0x10000000 0xcd00>;
1095 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>;
1096 phys = <&hs_phy_1>, <&ss_phy_1>;
1097 phy-names = "usb2-phy", "usb3-phy";
1098 dr_mode = "host";
1099 snps,dis_u3_susphy_quirk;
1100 };
1101 };
1102
1103 pcie0: pci@1b500000 {
1104 compatible = "qcom,pcie-ipq8064";
1105 reg = <0x1b500000 0x1000
1106 0x1b502000 0x80
1107 0x1b600000 0x100
1108 0x0ff00000 0x100000>;
1109 reg-names = "dbi", "elbi", "parf", "config";
1110 device_type = "pci";
1111 linux,pci-domain = <0>;
1112 bus-range = <0x00 0xff>;
1113 num-lanes = <1>;
1114 #address-cells = <3>;
1115 #size-cells = <2>;
1116
1117 ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
1118 0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
1119
1120 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1121 interrupt-names = "msi";
1122 #interrupt-cells = <1>;
1123 interrupt-map-mask = <0 0 0 0x7>;
1124 interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1125 <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1126 <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1127 <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1128
1129 clocks = <&gcc PCIE_A_CLK>,
1130 <&gcc PCIE_H_CLK>,
1131 <&gcc PCIE_PHY_CLK>,
1132 <&gcc PCIE_AUX_CLK>,
1133 <&gcc PCIE_ALT_REF_CLK>;
1134 clock-names = "core", "iface", "phy", "aux", "ref";
1135
1136 assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
1137 assigned-clock-rates = <100000000>;
1138
1139 resets = <&gcc PCIE_ACLK_RESET>,
1140 <&gcc PCIE_HCLK_RESET>,
1141 <&gcc PCIE_POR_RESET>,
1142 <&gcc PCIE_PCI_RESET>,
1143 <&gcc PCIE_PHY_RESET>,
1144 <&gcc PCIE_EXT_RESET>;
1145 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1146
1147 pinctrl-0 = <&pcie0_pins>;
1148 pinctrl-names = "default";
1149
1150 perst-gpios = <&qcom_pinmux 3 GPIO_ACTIVE_LOW>;
1151
1152 phy-tx0-term-offset = <7>;
1153
1154 status = "disabled";
1155 };
1156
1157 pcie1: pci@1b700000 {
1158 compatible = "qcom,pcie-ipq8064";
1159 reg = <0x1b700000 0x1000
1160 0x1b702000 0x80
1161 0x1b800000 0x100
1162 0x31f00000 0x100000>;
1163 reg-names = "dbi", "elbi", "parf", "config";
1164 device_type = "pci";
1165 linux,pci-domain = <1>;
1166 bus-range = <0x00 0xff>;
1167 num-lanes = <1>;
1168 #address-cells = <3>;
1169 #size-cells = <2>;
1170
1171 ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
1172 0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
1173
1174 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
1175 interrupt-names = "msi";
1176 #interrupt-cells = <1>;
1177 interrupt-map-mask = <0 0 0 0x7>;
1178 interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1179 <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1180 <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1181 <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1182
1183 clocks = <&gcc PCIE_1_A_CLK>,
1184 <&gcc PCIE_1_H_CLK>,
1185 <&gcc PCIE_1_PHY_CLK>,
1186 <&gcc PCIE_1_AUX_CLK>,
1187 <&gcc PCIE_1_ALT_REF_CLK>;
1188 clock-names = "core", "iface", "phy", "aux", "ref";
1189
1190 assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
1191 assigned-clock-rates = <100000000>;
1192
1193 resets = <&gcc PCIE_1_ACLK_RESET>,
1194 <&gcc PCIE_1_HCLK_RESET>,
1195 <&gcc PCIE_1_POR_RESET>,
1196 <&gcc PCIE_1_PCI_RESET>,
1197 <&gcc PCIE_1_PHY_RESET>,
1198 <&gcc PCIE_1_EXT_RESET>;
1199 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1200
1201 pinctrl-0 = <&pcie1_pins>;
1202 pinctrl-names = "default";
1203
1204 perst-gpios = <&qcom_pinmux 48 GPIO_ACTIVE_LOW>;
1205
1206 phy-tx0-term-offset = <7>;
1207
1208 status = "disabled";
1209 };
1210
1211 pcie2: pci@1b900000 {
1212 compatible = "qcom,pcie-ipq8064";
1213 reg = <0x1b900000 0x1000
1214 0x1b902000 0x80
1215 0x1ba00000 0x100
1216 0x35f00000 0x100000>;
1217 reg-names = "dbi", "elbi", "parf", "config";
1218 device_type = "pci";
1219 linux,pci-domain = <2>;
1220 bus-range = <0x00 0xff>;
1221 num-lanes = <1>;
1222 #address-cells = <3>;
1223 #size-cells = <2>;
1224
1225 ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
1226 0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
1227
1228 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
1229 interrupt-names = "msi";
1230 #interrupt-cells = <1>;
1231 interrupt-map-mask = <0 0 0 0x7>;
1232 interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
1233 <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
1234 <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
1235 <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
1236
1237 clocks = <&gcc PCIE_2_A_CLK>,
1238 <&gcc PCIE_2_H_CLK>,
1239 <&gcc PCIE_2_PHY_CLK>,
1240 <&gcc PCIE_2_AUX_CLK>,
1241 <&gcc PCIE_2_ALT_REF_CLK>;
1242 clock-names = "core", "iface", "phy", "aux", "ref";
1243
1244 assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
1245 assigned-clock-rates = <100000000>;
1246
1247 resets = <&gcc PCIE_2_ACLK_RESET>,
1248 <&gcc PCIE_2_HCLK_RESET>,
1249 <&gcc PCIE_2_POR_RESET>,
1250 <&gcc PCIE_2_PCI_RESET>,
1251 <&gcc PCIE_2_PHY_RESET>,
1252 <&gcc PCIE_2_EXT_RESET>;
1253 reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
1254
1255 pinctrl-0 = <&pcie2_pins>;
1256 pinctrl-names = "default";
1257
1258 perst-gpios = <&qcom_pinmux 63 GPIO_ACTIVE_LOW>;
1259
1260 phy-tx0-term-offset = <7>;
1261
1262 status = "disabled";
1263 };
1264
1265 adm_dma: dma@18300000 {
1266 compatible = "qcom,adm";
1267 reg = <0x18300000 0x100000>;
1268 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
1269 #dma-cells = <1>;
1270
1271 clocks = <&gcc ADM0_CLK>, <&gcc ADM0_PBUS_CLK>;
1272 clock-names = "core", "iface";
1273
1274 resets = <&gcc ADM0_RESET>,
1275 <&gcc ADM0_PBUS_RESET>,
1276 <&gcc ADM0_C0_RESET>,
1277 <&gcc ADM0_C1_RESET>,
1278 <&gcc ADM0_C2_RESET>;
1279 reset-names = "clk", "pbus", "c0", "c1", "c2";
1280 qcom,ee = <0>;
1281
1282 status = "disabled";
1283 };
1284
1285 nand: nand@1ac00000 {
1286 compatible = "qcom,ipq806x-nand";
1287 reg = <0x1ac00000 0x800>;
1288
1289 clocks = <&gcc EBI2_CLK>,
1290 <&gcc EBI2_AON_CLK>;
1291 clock-names = "core", "aon";
1292
1293 dmas = <&adm_dma 3>;
1294 dma-names = "rxtx";
1295 qcom,cmd-crci = <15>;
1296 qcom,data-crci = <3>;
1297
1298 status = "disabled";
1299
1300 #address-cells = <1>;
1301 #size-cells = <0>;
1302 };
1303
1304 nss_common: syscon@03000000 {
1305 compatible = "syscon";
1306 reg = <0x03000000 0x0000FFFF>;
1307 };
1308
1309 qsgmii_csr: syscon@1bb00000 {
1310 compatible = "syscon";
1311 reg = <0x1bb00000 0x000001FF>;
1312 };
1313
1314 stmmac_axi_setup: stmmac-axi-config {
1315 snps,wr_osr_lmt = <7>;
1316 snps,rd_osr_lmt = <7>;
1317 snps,blen = <16 0 0 0 0 0 0>;
1318 };
1319
1320 gmac0: ethernet@37000000 {
1321 device_type = "network";
1322 compatible = "qcom,ipq806x-gmac";
1323 reg = <0x37000000 0x200000>;
1324 interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
1325 interrupt-names = "macirq";
1326
1327 snps,axi-config = <&stmmac_axi_setup>;
1328 snps,pbl = <32>;
1329 snps,aal = <1>;
1330
1331 qcom,nss-common = <&nss_common>;
1332 qcom,qsgmii-csr = <&qsgmii_csr>;
1333
1334 clocks = <&gcc GMAC_CORE1_CLK>;
1335 clock-names = "stmmaceth";
1336
1337 resets = <&gcc GMAC_CORE1_RESET>;
1338 reset-names = "stmmaceth";
1339
1340 status = "disabled";
1341 };
1342
1343 gmac1: ethernet@37200000 {
1344 device_type = "network";
1345 compatible = "qcom,ipq806x-gmac";
1346 reg = <0x37200000 0x200000>;
1347 interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
1348 interrupt-names = "macirq";
1349
1350 snps,axi-config = <&stmmac_axi_setup>;
1351 snps,pbl = <32>;
1352 snps,aal = <1>;
1353
1354 qcom,nss-common = <&nss_common>;
1355 qcom,qsgmii-csr = <&qsgmii_csr>;
1356
1357 clocks = <&gcc GMAC_CORE2_CLK>;
1358 clock-names = "stmmaceth";
1359
1360 resets = <&gcc GMAC_CORE2_RESET>;
1361 reset-names = "stmmaceth";
1362
1363 status = "disabled";
1364 };
1365
1366 gmac2: ethernet@37400000 {
1367 device_type = "network";
1368 compatible = "qcom,ipq806x-gmac";
1369 reg = <0x37400000 0x200000>;
1370 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
1371 interrupt-names = "macirq";
1372
1373 snps,axi-config = <&stmmac_axi_setup>;
1374 snps,pbl = <32>;
1375 snps,aal = <1>;
1376
1377 qcom,nss-common = <&nss_common>;
1378 qcom,qsgmii-csr = <&qsgmii_csr>;
1379
1380 clocks = <&gcc GMAC_CORE3_CLK>;
1381 clock-names = "stmmaceth";
1382
1383 resets = <&gcc GMAC_CORE3_RESET>;
1384 reset-names = "stmmaceth";
1385
1386 status = "disabled";
1387 };
1388
1389 gmac3: ethernet@37600000 {
1390 device_type = "network";
1391 compatible = "qcom,ipq806x-gmac";
1392 reg = <0x37600000 0x200000>;
1393 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
1394 interrupt-names = "macirq";
1395
1396 snps,axi-config = <&stmmac_axi_setup>;
1397 snps,pbl = <32>;
1398 snps,aal = <1>;
1399
1400 qcom,nss-common = <&nss_common>;
1401 qcom,qsgmii-csr = <&qsgmii_csr>;
1402
1403 clocks = <&gcc GMAC_CORE4_CLK>;
1404 clock-names = "stmmaceth";
1405
1406 resets = <&gcc GMAC_CORE4_RESET>;
1407 reset-names = "stmmaceth";
1408
1409 status = "disabled";
1410 };
1411
1412 /* Temporary fixed regulator */
1413 vsdcc_fixed: vsdcc-regulator {
1414 compatible = "regulator-fixed";
1415 regulator-name = "SDCC Power";
1416 regulator-min-microvolt = <3300000>;
1417 regulator-max-microvolt = <3300000>;
1418 regulator-always-on;
1419 };
1420
1421 sdcc1bam:dma@12402000 {
1422 compatible = "qcom,bam-v1.3.0";
1423 reg = <0x12402000 0x8000>;
1424 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1425 clocks = <&gcc SDC1_H_CLK>;
1426 clock-names = "bam_clk";
1427 #dma-cells = <1>;
1428 qcom,ee = <0>;
1429 };
1430
1431 sdcc3bam:dma@12182000 {
1432 compatible = "qcom,bam-v1.3.0";
1433 reg = <0x12182000 0x8000>;
1434 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
1435 clocks = <&gcc SDC3_H_CLK>;
1436 clock-names = "bam_clk";
1437 #dma-cells = <1>;
1438 qcom,ee = <0>;
1439 };
1440
1441 amba {
1442 compatible = "arm,amba-bus";
1443 #address-cells = <1>;
1444 #size-cells = <1>;
1445 ranges;
1446 sdcc1: sdcc@12400000 {
1447 status = "disabled";
1448 compatible = "arm,pl18x", "arm,primecell";
1449 arm,primecell-periphid = <0x00051180>;
1450 reg = <0x12400000 0x2000>;
1451 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1452 interrupt-names = "cmd_irq";
1453 clocks = <&gcc SDC1_CLK>, <&gcc SDC1_H_CLK>;
1454 clock-names = "mclk", "apb_pclk";
1455 bus-width = <8>;
1456 max-frequency = <96000000>;
1457 non-removable;
1458 cap-sd-highspeed;
1459 cap-mmc-highspeed;
1460 vmmc-supply = <&vsdcc_fixed>;
1461 dmas = <&sdcc1bam 2>, <&sdcc1bam 1>;
1462 dma-names = "tx", "rx";
1463 };
1464
1465 sdcc3: sdcc@12180000 {
1466 compatible = "arm,pl18x", "arm,primecell";
1467 arm,primecell-periphid = <0x00051180>;
1468 status = "disabled";
1469 reg = <0x12180000 0x2000>;
1470 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1471 interrupt-names = "cmd_irq";
1472 clocks = <&gcc SDC3_CLK>, <&gcc SDC3_H_CLK>;
1473 clock-names = "mclk", "apb_pclk";
1474 bus-width = <8>;
1475 cap-sd-highspeed;
1476 cap-mmc-highspeed;
1477 max-frequency = <192000000>;
1478 #mmc-ddr-1_8v;
1479 sd-uhs-sdr104;
1480 sd-uhs-ddr50;
1481 vqmmc-supply = <&vsdcc_fixed>;
1482 dmas = <&sdcc3bam 2>, <&sdcc3bam 1>;
1483 dma-names = "tx", "rx";
1484 };
1485 };
1486 };
1487
1488 sfpb_mutex: sfpb-mutex {
1489 compatible = "qcom,sfpb-mutex";
1490 syscon = <&sfpb_mutex_block 4 4>;
1491
1492 #hwlock-cells = <1>;
1493 };
1494
1495 smem {
1496 compatible = "qcom,smem";
1497 memory-region = <&smem>;
1498 hwlocks = <&sfpb_mutex 3>;
1499 };
1500 };
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