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[openwrt/staging/dedeckeh.git] / target / linux / layerscape / patches-4.14 / 824-ptp-support-layerscape.patch
1 From bba7af6efb0aad1d52ee5e7d80f9e2ab59d85e20 Mon Sep 17 00:00:00 2001
2 From: Biwen Li <biwen.li@nxp.com>
3 Date: Wed, 17 Apr 2019 18:58:52 +0800
4 Subject: [PATCH] ptp: support layerscape
5
6 This is an integrated patch of ptp for layerscape
7
8 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
9 Signed-off-by: Biwen Li <biwen.li@nxp.com>
10 Signed-off-by: David S. Miller <davem@davemloft.net>
11 Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
12 ---
13 drivers/net/ethernet/freescale/Makefile | 1 -
14 drivers/net/ethernet/freescale/gianfar_ptp.c | 572 ------------------
15 drivers/ptp/Makefile | 1 +
16 drivers/ptp/ptp_chardev.c | 4 +-
17 drivers/ptp/ptp_qoriq.c | 589 +++++++++++++++++++
18 include/linux/fsl/ptp_qoriq.h | 169 ++++++
19 6 files changed, 761 insertions(+), 575 deletions(-)
20 delete mode 100644 drivers/net/ethernet/freescale/gianfar_ptp.c
21 create mode 100644 drivers/ptp/ptp_qoriq.c
22 create mode 100644 include/linux/fsl/ptp_qoriq.h
23
24 --- a/drivers/net/ethernet/freescale/Makefile
25 +++ b/drivers/net/ethernet/freescale/Makefile
26 @@ -14,7 +14,6 @@ obj-$(CONFIG_FS_ENET) += fs_enet/
27 obj-$(CONFIG_FSL_PQ_MDIO) += fsl_pq_mdio.o
28 obj-$(CONFIG_FSL_XGMAC_MDIO) += xgmac_mdio.o
29 obj-$(CONFIG_GIANFAR) += gianfar_driver.o
30 -obj-$(CONFIG_PTP_1588_CLOCK_GIANFAR) += gianfar_ptp.o
31 gianfar_driver-objs := gianfar.o \
32 gianfar_ethtool.o
33 obj-$(CONFIG_UCC_GETH) += ucc_geth_driver.o
34 --- a/drivers/net/ethernet/freescale/gianfar_ptp.c
35 +++ /dev/null
36 @@ -1,572 +0,0 @@
37 -/*
38 - * PTP 1588 clock using the eTSEC
39 - *
40 - * Copyright (C) 2010 OMICRON electronics GmbH
41 - *
42 - * This program is free software; you can redistribute it and/or modify
43 - * it under the terms of the GNU General Public License as published by
44 - * the Free Software Foundation; either version 2 of the License, or
45 - * (at your option) any later version.
46 - *
47 - * This program is distributed in the hope that it will be useful,
48 - * but WITHOUT ANY WARRANTY; without even the implied warranty of
49 - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
50 - * GNU General Public License for more details.
51 - *
52 - * You should have received a copy of the GNU General Public License
53 - * along with this program; if not, write to the Free Software
54 - * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
55 - */
56 -
57 -#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
58 -
59 -#include <linux/device.h>
60 -#include <linux/hrtimer.h>
61 -#include <linux/interrupt.h>
62 -#include <linux/kernel.h>
63 -#include <linux/module.h>
64 -#include <linux/of.h>
65 -#include <linux/of_platform.h>
66 -#include <linux/timex.h>
67 -#include <linux/io.h>
68 -
69 -#include <linux/ptp_clock_kernel.h>
70 -
71 -#include "gianfar.h"
72 -
73 -/*
74 - * gianfar ptp registers
75 - * Generated by regen.tcl on Thu May 13 01:38:57 PM CEST 2010
76 - */
77 -struct gianfar_ptp_registers {
78 - u32 tmr_ctrl; /* Timer control register */
79 - u32 tmr_tevent; /* Timestamp event register */
80 - u32 tmr_temask; /* Timer event mask register */
81 - u32 tmr_pevent; /* Timestamp event register */
82 - u32 tmr_pemask; /* Timer event mask register */
83 - u32 tmr_stat; /* Timestamp status register */
84 - u32 tmr_cnt_h; /* Timer counter high register */
85 - u32 tmr_cnt_l; /* Timer counter low register */
86 - u32 tmr_add; /* Timer drift compensation addend register */
87 - u32 tmr_acc; /* Timer accumulator register */
88 - u32 tmr_prsc; /* Timer prescale */
89 - u8 res1[4];
90 - u32 tmroff_h; /* Timer offset high */
91 - u32 tmroff_l; /* Timer offset low */
92 - u8 res2[8];
93 - u32 tmr_alarm1_h; /* Timer alarm 1 high register */
94 - u32 tmr_alarm1_l; /* Timer alarm 1 high register */
95 - u32 tmr_alarm2_h; /* Timer alarm 2 high register */
96 - u32 tmr_alarm2_l; /* Timer alarm 2 high register */
97 - u8 res3[48];
98 - u32 tmr_fiper1; /* Timer fixed period interval */
99 - u32 tmr_fiper2; /* Timer fixed period interval */
100 - u32 tmr_fiper3; /* Timer fixed period interval */
101 - u8 res4[20];
102 - u32 tmr_etts1_h; /* Timestamp of general purpose external trigger */
103 - u32 tmr_etts1_l; /* Timestamp of general purpose external trigger */
104 - u32 tmr_etts2_h; /* Timestamp of general purpose external trigger */
105 - u32 tmr_etts2_l; /* Timestamp of general purpose external trigger */
106 -};
107 -
108 -/* Bit definitions for the TMR_CTRL register */
109 -#define ALM1P (1<<31) /* Alarm1 output polarity */
110 -#define ALM2P (1<<30) /* Alarm2 output polarity */
111 -#define FIPERST (1<<28) /* FIPER start indication */
112 -#define PP1L (1<<27) /* Fiper1 pulse loopback mode enabled. */
113 -#define PP2L (1<<26) /* Fiper2 pulse loopback mode enabled. */
114 -#define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */
115 -#define TCLK_PERIOD_MASK (0x3ff)
116 -#define RTPE (1<<15) /* Record Tx Timestamp to PAL Enable. */
117 -#define FRD (1<<14) /* FIPER Realignment Disable */
118 -#define ESFDP (1<<11) /* External Tx/Rx SFD Polarity. */
119 -#define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */
120 -#define ETEP2 (1<<9) /* External trigger 2 edge polarity */
121 -#define ETEP1 (1<<8) /* External trigger 1 edge polarity */
122 -#define COPH (1<<7) /* Generated clock output phase. */
123 -#define CIPH (1<<6) /* External oscillator input clock phase */
124 -#define TMSR (1<<5) /* Timer soft reset. */
125 -#define BYP (1<<3) /* Bypass drift compensated clock */
126 -#define TE (1<<2) /* 1588 timer enable. */
127 -#define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */
128 -#define CKSEL_MASK (0x3)
129 -
130 -/* Bit definitions for the TMR_TEVENT register */
131 -#define ETS2 (1<<25) /* External trigger 2 timestamp sampled */
132 -#define ETS1 (1<<24) /* External trigger 1 timestamp sampled */
133 -#define ALM2 (1<<17) /* Current time = alarm time register 2 */
134 -#define ALM1 (1<<16) /* Current time = alarm time register 1 */
135 -#define PP1 (1<<7) /* periodic pulse generated on FIPER1 */
136 -#define PP2 (1<<6) /* periodic pulse generated on FIPER2 */
137 -#define PP3 (1<<5) /* periodic pulse generated on FIPER3 */
138 -
139 -/* Bit definitions for the TMR_TEMASK register */
140 -#define ETS2EN (1<<25) /* External trigger 2 timestamp enable */
141 -#define ETS1EN (1<<24) /* External trigger 1 timestamp enable */
142 -#define ALM2EN (1<<17) /* Timer ALM2 event enable */
143 -#define ALM1EN (1<<16) /* Timer ALM1 event enable */
144 -#define PP1EN (1<<7) /* Periodic pulse event 1 enable */
145 -#define PP2EN (1<<6) /* Periodic pulse event 2 enable */
146 -
147 -/* Bit definitions for the TMR_PEVENT register */
148 -#define TXP2 (1<<9) /* PTP transmitted timestamp im TXTS2 */
149 -#define TXP1 (1<<8) /* PTP transmitted timestamp in TXTS1 */
150 -#define RXP (1<<0) /* PTP frame has been received */
151 -
152 -/* Bit definitions for the TMR_PEMASK register */
153 -#define TXP2EN (1<<9) /* Transmit PTP packet event 2 enable */
154 -#define TXP1EN (1<<8) /* Transmit PTP packet event 1 enable */
155 -#define RXPEN (1<<0) /* Receive PTP packet event enable */
156 -
157 -/* Bit definitions for the TMR_STAT register */
158 -#define STAT_VEC_SHIFT (0) /* Timer general purpose status vector */
159 -#define STAT_VEC_MASK (0x3f)
160 -
161 -/* Bit definitions for the TMR_PRSC register */
162 -#define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */
163 -#define PRSC_OCK_MASK (0xffff)
164 -
165 -
166 -#define DRIVER "gianfar_ptp"
167 -#define DEFAULT_CKSEL 1
168 -#define N_EXT_TS 2
169 -#define REG_SIZE sizeof(struct gianfar_ptp_registers)
170 -
171 -struct etsects {
172 - struct gianfar_ptp_registers __iomem *regs;
173 - spinlock_t lock; /* protects regs */
174 - struct ptp_clock *clock;
175 - struct ptp_clock_info caps;
176 - struct resource *rsrc;
177 - int irq;
178 - u64 alarm_interval; /* for periodic alarm */
179 - u64 alarm_value;
180 - u32 tclk_period; /* nanoseconds */
181 - u32 tmr_prsc;
182 - u32 tmr_add;
183 - u32 cksel;
184 - u32 tmr_fiper1;
185 - u32 tmr_fiper2;
186 -};
187 -
188 -/*
189 - * Register access functions
190 - */
191 -
192 -/* Caller must hold etsects->lock. */
193 -static u64 tmr_cnt_read(struct etsects *etsects)
194 -{
195 - u64 ns;
196 - u32 lo, hi;
197 -
198 - lo = gfar_read(&etsects->regs->tmr_cnt_l);
199 - hi = gfar_read(&etsects->regs->tmr_cnt_h);
200 - ns = ((u64) hi) << 32;
201 - ns |= lo;
202 - return ns;
203 -}
204 -
205 -/* Caller must hold etsects->lock. */
206 -static void tmr_cnt_write(struct etsects *etsects, u64 ns)
207 -{
208 - u32 hi = ns >> 32;
209 - u32 lo = ns & 0xffffffff;
210 -
211 - gfar_write(&etsects->regs->tmr_cnt_l, lo);
212 - gfar_write(&etsects->regs->tmr_cnt_h, hi);
213 -}
214 -
215 -/* Caller must hold etsects->lock. */
216 -static void set_alarm(struct etsects *etsects)
217 -{
218 - u64 ns;
219 - u32 lo, hi;
220 -
221 - ns = tmr_cnt_read(etsects) + 1500000000ULL;
222 - ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
223 - ns -= etsects->tclk_period;
224 - hi = ns >> 32;
225 - lo = ns & 0xffffffff;
226 - gfar_write(&etsects->regs->tmr_alarm1_l, lo);
227 - gfar_write(&etsects->regs->tmr_alarm1_h, hi);
228 -}
229 -
230 -/* Caller must hold etsects->lock. */
231 -static void set_fipers(struct etsects *etsects)
232 -{
233 - set_alarm(etsects);
234 - gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
235 - gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
236 -}
237 -
238 -/*
239 - * Interrupt service routine
240 - */
241 -
242 -static irqreturn_t isr(int irq, void *priv)
243 -{
244 - struct etsects *etsects = priv;
245 - struct ptp_clock_event event;
246 - u64 ns;
247 - u32 ack = 0, lo, hi, mask, val;
248 -
249 - val = gfar_read(&etsects->regs->tmr_tevent);
250 -
251 - if (val & ETS1) {
252 - ack |= ETS1;
253 - hi = gfar_read(&etsects->regs->tmr_etts1_h);
254 - lo = gfar_read(&etsects->regs->tmr_etts1_l);
255 - event.type = PTP_CLOCK_EXTTS;
256 - event.index = 0;
257 - event.timestamp = ((u64) hi) << 32;
258 - event.timestamp |= lo;
259 - ptp_clock_event(etsects->clock, &event);
260 - }
261 -
262 - if (val & ETS2) {
263 - ack |= ETS2;
264 - hi = gfar_read(&etsects->regs->tmr_etts2_h);
265 - lo = gfar_read(&etsects->regs->tmr_etts2_l);
266 - event.type = PTP_CLOCK_EXTTS;
267 - event.index = 1;
268 - event.timestamp = ((u64) hi) << 32;
269 - event.timestamp |= lo;
270 - ptp_clock_event(etsects->clock, &event);
271 - }
272 -
273 - if (val & ALM2) {
274 - ack |= ALM2;
275 - if (etsects->alarm_value) {
276 - event.type = PTP_CLOCK_ALARM;
277 - event.index = 0;
278 - event.timestamp = etsects->alarm_value;
279 - ptp_clock_event(etsects->clock, &event);
280 - }
281 - if (etsects->alarm_interval) {
282 - ns = etsects->alarm_value + etsects->alarm_interval;
283 - hi = ns >> 32;
284 - lo = ns & 0xffffffff;
285 - spin_lock(&etsects->lock);
286 - gfar_write(&etsects->regs->tmr_alarm2_l, lo);
287 - gfar_write(&etsects->regs->tmr_alarm2_h, hi);
288 - spin_unlock(&etsects->lock);
289 - etsects->alarm_value = ns;
290 - } else {
291 - gfar_write(&etsects->regs->tmr_tevent, ALM2);
292 - spin_lock(&etsects->lock);
293 - mask = gfar_read(&etsects->regs->tmr_temask);
294 - mask &= ~ALM2EN;
295 - gfar_write(&etsects->regs->tmr_temask, mask);
296 - spin_unlock(&etsects->lock);
297 - etsects->alarm_value = 0;
298 - etsects->alarm_interval = 0;
299 - }
300 - }
301 -
302 - if (val & PP1) {
303 - ack |= PP1;
304 - event.type = PTP_CLOCK_PPS;
305 - ptp_clock_event(etsects->clock, &event);
306 - }
307 -
308 - if (ack) {
309 - gfar_write(&etsects->regs->tmr_tevent, ack);
310 - return IRQ_HANDLED;
311 - } else
312 - return IRQ_NONE;
313 -}
314 -
315 -/*
316 - * PTP clock operations
317 - */
318 -
319 -static int ptp_gianfar_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
320 -{
321 - u64 adj, diff;
322 - u32 tmr_add;
323 - int neg_adj = 0;
324 - struct etsects *etsects = container_of(ptp, struct etsects, caps);
325 -
326 - if (scaled_ppm < 0) {
327 - neg_adj = 1;
328 - scaled_ppm = -scaled_ppm;
329 - }
330 - tmr_add = etsects->tmr_add;
331 - adj = tmr_add;
332 -
333 - /* calculate diff as adj*(scaled_ppm/65536)/1000000
334 - * and round() to the nearest integer
335 - */
336 - adj *= scaled_ppm;
337 - diff = div_u64(adj, 8000000);
338 - diff = (diff >> 13) + ((diff >> 12) & 1);
339 -
340 - tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
341 -
342 - gfar_write(&etsects->regs->tmr_add, tmr_add);
343 -
344 - return 0;
345 -}
346 -
347 -static int ptp_gianfar_adjtime(struct ptp_clock_info *ptp, s64 delta)
348 -{
349 - s64 now;
350 - unsigned long flags;
351 - struct etsects *etsects = container_of(ptp, struct etsects, caps);
352 -
353 - spin_lock_irqsave(&etsects->lock, flags);
354 -
355 - now = tmr_cnt_read(etsects);
356 - now += delta;
357 - tmr_cnt_write(etsects, now);
358 - set_fipers(etsects);
359 -
360 - spin_unlock_irqrestore(&etsects->lock, flags);
361 -
362 - return 0;
363 -}
364 -
365 -static int ptp_gianfar_gettime(struct ptp_clock_info *ptp,
366 - struct timespec64 *ts)
367 -{
368 - u64 ns;
369 - unsigned long flags;
370 - struct etsects *etsects = container_of(ptp, struct etsects, caps);
371 -
372 - spin_lock_irqsave(&etsects->lock, flags);
373 -
374 - ns = tmr_cnt_read(etsects);
375 -
376 - spin_unlock_irqrestore(&etsects->lock, flags);
377 -
378 - *ts = ns_to_timespec64(ns);
379 -
380 - return 0;
381 -}
382 -
383 -static int ptp_gianfar_settime(struct ptp_clock_info *ptp,
384 - const struct timespec64 *ts)
385 -{
386 - u64 ns;
387 - unsigned long flags;
388 - struct etsects *etsects = container_of(ptp, struct etsects, caps);
389 -
390 - ns = timespec64_to_ns(ts);
391 -
392 - spin_lock_irqsave(&etsects->lock, flags);
393 -
394 - tmr_cnt_write(etsects, ns);
395 - set_fipers(etsects);
396 -
397 - spin_unlock_irqrestore(&etsects->lock, flags);
398 -
399 - return 0;
400 -}
401 -
402 -static int ptp_gianfar_enable(struct ptp_clock_info *ptp,
403 - struct ptp_clock_request *rq, int on)
404 -{
405 - struct etsects *etsects = container_of(ptp, struct etsects, caps);
406 - unsigned long flags;
407 - u32 bit, mask;
408 -
409 - switch (rq->type) {
410 - case PTP_CLK_REQ_EXTTS:
411 - switch (rq->extts.index) {
412 - case 0:
413 - bit = ETS1EN;
414 - break;
415 - case 1:
416 - bit = ETS2EN;
417 - break;
418 - default:
419 - return -EINVAL;
420 - }
421 - spin_lock_irqsave(&etsects->lock, flags);
422 - mask = gfar_read(&etsects->regs->tmr_temask);
423 - if (on)
424 - mask |= bit;
425 - else
426 - mask &= ~bit;
427 - gfar_write(&etsects->regs->tmr_temask, mask);
428 - spin_unlock_irqrestore(&etsects->lock, flags);
429 - return 0;
430 -
431 - case PTP_CLK_REQ_PPS:
432 - spin_lock_irqsave(&etsects->lock, flags);
433 - mask = gfar_read(&etsects->regs->tmr_temask);
434 - if (on)
435 - mask |= PP1EN;
436 - else
437 - mask &= ~PP1EN;
438 - gfar_write(&etsects->regs->tmr_temask, mask);
439 - spin_unlock_irqrestore(&etsects->lock, flags);
440 - return 0;
441 -
442 - default:
443 - break;
444 - }
445 -
446 - return -EOPNOTSUPP;
447 -}
448 -
449 -static const struct ptp_clock_info ptp_gianfar_caps = {
450 - .owner = THIS_MODULE,
451 - .name = "gianfar clock",
452 - .max_adj = 512000,
453 - .n_alarm = 0,
454 - .n_ext_ts = N_EXT_TS,
455 - .n_per_out = 0,
456 - .n_pins = 0,
457 - .pps = 1,
458 - .adjfine = ptp_gianfar_adjfine,
459 - .adjtime = ptp_gianfar_adjtime,
460 - .gettime64 = ptp_gianfar_gettime,
461 - .settime64 = ptp_gianfar_settime,
462 - .enable = ptp_gianfar_enable,
463 -};
464 -
465 -static int gianfar_ptp_probe(struct platform_device *dev)
466 -{
467 - struct device_node *node = dev->dev.of_node;
468 - struct etsects *etsects;
469 - struct timespec64 now;
470 - int err = -ENOMEM;
471 - u32 tmr_ctrl;
472 - unsigned long flags;
473 -
474 - etsects = kzalloc(sizeof(*etsects), GFP_KERNEL);
475 - if (!etsects)
476 - goto no_memory;
477 -
478 - err = -ENODEV;
479 -
480 - etsects->caps = ptp_gianfar_caps;
481 -
482 - if (of_property_read_u32(node, "fsl,cksel", &etsects->cksel))
483 - etsects->cksel = DEFAULT_CKSEL;
484 -
485 - if (of_property_read_u32(node,
486 - "fsl,tclk-period", &etsects->tclk_period) ||
487 - of_property_read_u32(node,
488 - "fsl,tmr-prsc", &etsects->tmr_prsc) ||
489 - of_property_read_u32(node,
490 - "fsl,tmr-add", &etsects->tmr_add) ||
491 - of_property_read_u32(node,
492 - "fsl,tmr-fiper1", &etsects->tmr_fiper1) ||
493 - of_property_read_u32(node,
494 - "fsl,tmr-fiper2", &etsects->tmr_fiper2) ||
495 - of_property_read_u32(node,
496 - "fsl,max-adj", &etsects->caps.max_adj)) {
497 - pr_err("device tree node missing required elements\n");
498 - goto no_node;
499 - }
500 -
501 - etsects->irq = platform_get_irq(dev, 0);
502 -
503 - if (etsects->irq < 0) {
504 - pr_err("irq not in device tree\n");
505 - goto no_node;
506 - }
507 - if (request_irq(etsects->irq, isr, 0, DRIVER, etsects)) {
508 - pr_err("request_irq failed\n");
509 - goto no_node;
510 - }
511 -
512 - etsects->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
513 - if (!etsects->rsrc) {
514 - pr_err("no resource\n");
515 - goto no_resource;
516 - }
517 - if (request_resource(&iomem_resource, etsects->rsrc)) {
518 - pr_err("resource busy\n");
519 - goto no_resource;
520 - }
521 -
522 - spin_lock_init(&etsects->lock);
523 -
524 - etsects->regs = ioremap(etsects->rsrc->start,
525 - resource_size(etsects->rsrc));
526 - if (!etsects->regs) {
527 - pr_err("ioremap ptp registers failed\n");
528 - goto no_ioremap;
529 - }
530 - getnstimeofday64(&now);
531 - ptp_gianfar_settime(&etsects->caps, &now);
532 -
533 - tmr_ctrl =
534 - (etsects->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
535 - (etsects->cksel & CKSEL_MASK) << CKSEL_SHIFT;
536 -
537 - spin_lock_irqsave(&etsects->lock, flags);
538 -
539 - gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl);
540 - gfar_write(&etsects->regs->tmr_add, etsects->tmr_add);
541 - gfar_write(&etsects->regs->tmr_prsc, etsects->tmr_prsc);
542 - gfar_write(&etsects->regs->tmr_fiper1, etsects->tmr_fiper1);
543 - gfar_write(&etsects->regs->tmr_fiper2, etsects->tmr_fiper2);
544 - set_alarm(etsects);
545 - gfar_write(&etsects->regs->tmr_ctrl, tmr_ctrl|FIPERST|RTPE|TE|FRD);
546 -
547 - spin_unlock_irqrestore(&etsects->lock, flags);
548 -
549 - etsects->clock = ptp_clock_register(&etsects->caps, &dev->dev);
550 - if (IS_ERR(etsects->clock)) {
551 - err = PTR_ERR(etsects->clock);
552 - goto no_clock;
553 - }
554 - gfar_phc_index = ptp_clock_index(etsects->clock);
555 -
556 - platform_set_drvdata(dev, etsects);
557 -
558 - return 0;
559 -
560 -no_clock:
561 - iounmap(etsects->regs);
562 -no_ioremap:
563 - release_resource(etsects->rsrc);
564 -no_resource:
565 - free_irq(etsects->irq, etsects);
566 -no_node:
567 - kfree(etsects);
568 -no_memory:
569 - return err;
570 -}
571 -
572 -static int gianfar_ptp_remove(struct platform_device *dev)
573 -{
574 - struct etsects *etsects = platform_get_drvdata(dev);
575 -
576 - gfar_write(&etsects->regs->tmr_temask, 0);
577 - gfar_write(&etsects->regs->tmr_ctrl, 0);
578 -
579 - gfar_phc_index = -1;
580 - ptp_clock_unregister(etsects->clock);
581 - iounmap(etsects->regs);
582 - release_resource(etsects->rsrc);
583 - free_irq(etsects->irq, etsects);
584 - kfree(etsects);
585 -
586 - return 0;
587 -}
588 -
589 -static const struct of_device_id match_table[] = {
590 - { .compatible = "fsl,etsec-ptp" },
591 - {},
592 -};
593 -MODULE_DEVICE_TABLE(of, match_table);
594 -
595 -static struct platform_driver gianfar_ptp_driver = {
596 - .driver = {
597 - .name = "gianfar_ptp",
598 - .of_match_table = match_table,
599 - },
600 - .probe = gianfar_ptp_probe,
601 - .remove = gianfar_ptp_remove,
602 -};
603 -
604 -module_platform_driver(gianfar_ptp_driver);
605 -
606 -MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
607 -MODULE_DESCRIPTION("PTP clock using the eTSEC");
608 -MODULE_LICENSE("GPL");
609 --- a/drivers/ptp/Makefile
610 +++ b/drivers/ptp/Makefile
611 @@ -9,3 +9,4 @@ obj-$(CONFIG_PTP_1588_CLOCK_DTE) += ptp_
612 obj-$(CONFIG_PTP_1588_CLOCK_IXP46X) += ptp_ixp46x.o
613 obj-$(CONFIG_PTP_1588_CLOCK_PCH) += ptp_pch.o
614 obj-$(CONFIG_PTP_1588_CLOCK_KVM) += ptp_kvm.o
615 +obj-$(CONFIG_PTP_1588_CLOCK_QORIQ) += ptp_qoriq.o
616 --- a/drivers/ptp/ptp_chardev.c
617 +++ b/drivers/ptp/ptp_chardev.c
618 @@ -224,7 +224,7 @@ long ptp_ioctl(struct posix_clock *pc, u
619 }
620 pct = &sysoff->ts[0];
621 for (i = 0; i < sysoff->n_samples; i++) {
622 - getnstimeofday64(&ts);
623 + ktime_get_real_ts64(&ts);
624 pct->sec = ts.tv_sec;
625 pct->nsec = ts.tv_nsec;
626 pct++;
627 @@ -235,7 +235,7 @@ long ptp_ioctl(struct posix_clock *pc, u
628 pct->nsec = ts.tv_nsec;
629 pct++;
630 }
631 - getnstimeofday64(&ts);
632 + ktime_get_real_ts64(&ts);
633 pct->sec = ts.tv_sec;
634 pct->nsec = ts.tv_nsec;
635 if (copy_to_user((void __user *)arg, sysoff, sizeof(*sysoff)))
636 --- /dev/null
637 +++ b/drivers/ptp/ptp_qoriq.c
638 @@ -0,0 +1,589 @@
639 +/*
640 + * PTP 1588 clock for Freescale QorIQ 1588 timer
641 + *
642 + * Copyright (C) 2010 OMICRON electronics GmbH
643 + *
644 + * This program is free software; you can redistribute it and/or modify
645 + * it under the terms of the GNU General Public License as published by
646 + * the Free Software Foundation; either version 2 of the License, or
647 + * (at your option) any later version.
648 + *
649 + * This program is distributed in the hope that it will be useful,
650 + * but WITHOUT ANY WARRANTY; without even the implied warranty of
651 + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
652 + * GNU General Public License for more details.
653 + *
654 + * You should have received a copy of the GNU General Public License
655 + * along with this program; if not, write to the Free Software
656 + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
657 + */
658 +
659 +#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
660 +
661 +#include <linux/device.h>
662 +#include <linux/hrtimer.h>
663 +#include <linux/interrupt.h>
664 +#include <linux/kernel.h>
665 +#include <linux/module.h>
666 +#include <linux/of.h>
667 +#include <linux/of_platform.h>
668 +#include <linux/timex.h>
669 +#include <linux/slab.h>
670 +#include <linux/clk.h>
671 +
672 +#include <linux/fsl/ptp_qoriq.h>
673 +
674 +/*
675 + * Register access functions
676 + */
677 +
678 +/* Caller must hold qoriq_ptp->lock. */
679 +static u64 tmr_cnt_read(struct qoriq_ptp *qoriq_ptp)
680 +{
681 + struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
682 + u64 ns;
683 + u32 lo, hi;
684 +
685 + lo = qoriq_read(&regs->ctrl_regs->tmr_cnt_l);
686 + hi = qoriq_read(&regs->ctrl_regs->tmr_cnt_h);
687 + ns = ((u64) hi) << 32;
688 + ns |= lo;
689 + return ns;
690 +}
691 +
692 +/* Caller must hold qoriq_ptp->lock. */
693 +static void tmr_cnt_write(struct qoriq_ptp *qoriq_ptp, u64 ns)
694 +{
695 + struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
696 + u32 hi = ns >> 32;
697 + u32 lo = ns & 0xffffffff;
698 +
699 + qoriq_write(&regs->ctrl_regs->tmr_cnt_l, lo);
700 + qoriq_write(&regs->ctrl_regs->tmr_cnt_h, hi);
701 +}
702 +
703 +/* Caller must hold qoriq_ptp->lock. */
704 +static void set_alarm(struct qoriq_ptp *qoriq_ptp)
705 +{
706 + struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
707 + u64 ns;
708 + u32 lo, hi;
709 +
710 + ns = tmr_cnt_read(qoriq_ptp) + 1500000000ULL;
711 + ns = div_u64(ns, 1000000000UL) * 1000000000ULL;
712 + ns -= qoriq_ptp->tclk_period;
713 + hi = ns >> 32;
714 + lo = ns & 0xffffffff;
715 + qoriq_write(&regs->alarm_regs->tmr_alarm1_l, lo);
716 + qoriq_write(&regs->alarm_regs->tmr_alarm1_h, hi);
717 +}
718 +
719 +/* Caller must hold qoriq_ptp->lock. */
720 +static void set_fipers(struct qoriq_ptp *qoriq_ptp)
721 +{
722 + struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
723 +
724 + set_alarm(qoriq_ptp);
725 + qoriq_write(&regs->fiper_regs->tmr_fiper1, qoriq_ptp->tmr_fiper1);
726 + qoriq_write(&regs->fiper_regs->tmr_fiper2, qoriq_ptp->tmr_fiper2);
727 +}
728 +
729 +/*
730 + * Interrupt service routine
731 + */
732 +
733 +static irqreturn_t isr(int irq, void *priv)
734 +{
735 + struct qoriq_ptp *qoriq_ptp = priv;
736 + struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
737 + struct ptp_clock_event event;
738 + u64 ns;
739 + u32 ack = 0, lo, hi, mask, val;
740 +
741 + val = qoriq_read(&regs->ctrl_regs->tmr_tevent);
742 +
743 + if (val & ETS1) {
744 + ack |= ETS1;
745 + hi = qoriq_read(&regs->etts_regs->tmr_etts1_h);
746 + lo = qoriq_read(&regs->etts_regs->tmr_etts1_l);
747 + event.type = PTP_CLOCK_EXTTS;
748 + event.index = 0;
749 + event.timestamp = ((u64) hi) << 32;
750 + event.timestamp |= lo;
751 + ptp_clock_event(qoriq_ptp->clock, &event);
752 + }
753 +
754 + if (val & ETS2) {
755 + ack |= ETS2;
756 + hi = qoriq_read(&regs->etts_regs->tmr_etts2_h);
757 + lo = qoriq_read(&regs->etts_regs->tmr_etts2_l);
758 + event.type = PTP_CLOCK_EXTTS;
759 + event.index = 1;
760 + event.timestamp = ((u64) hi) << 32;
761 + event.timestamp |= lo;
762 + ptp_clock_event(qoriq_ptp->clock, &event);
763 + }
764 +
765 + if (val & ALM2) {
766 + ack |= ALM2;
767 + if (qoriq_ptp->alarm_value) {
768 + event.type = PTP_CLOCK_ALARM;
769 + event.index = 0;
770 + event.timestamp = qoriq_ptp->alarm_value;
771 + ptp_clock_event(qoriq_ptp->clock, &event);
772 + }
773 + if (qoriq_ptp->alarm_interval) {
774 + ns = qoriq_ptp->alarm_value + qoriq_ptp->alarm_interval;
775 + hi = ns >> 32;
776 + lo = ns & 0xffffffff;
777 + spin_lock(&qoriq_ptp->lock);
778 + qoriq_write(&regs->alarm_regs->tmr_alarm2_l, lo);
779 + qoriq_write(&regs->alarm_regs->tmr_alarm2_h, hi);
780 + spin_unlock(&qoriq_ptp->lock);
781 + qoriq_ptp->alarm_value = ns;
782 + } else {
783 + qoriq_write(&regs->ctrl_regs->tmr_tevent, ALM2);
784 + spin_lock(&qoriq_ptp->lock);
785 + mask = qoriq_read(&regs->ctrl_regs->tmr_temask);
786 + mask &= ~ALM2EN;
787 + qoriq_write(&regs->ctrl_regs->tmr_temask, mask);
788 + spin_unlock(&qoriq_ptp->lock);
789 + qoriq_ptp->alarm_value = 0;
790 + qoriq_ptp->alarm_interval = 0;
791 + }
792 + }
793 +
794 + if (val & PP1) {
795 + ack |= PP1;
796 + event.type = PTP_CLOCK_PPS;
797 + ptp_clock_event(qoriq_ptp->clock, &event);
798 + }
799 +
800 + if (ack) {
801 + qoriq_write(&regs->ctrl_regs->tmr_tevent, ack);
802 + return IRQ_HANDLED;
803 + } else
804 + return IRQ_NONE;
805 +}
806 +
807 +/*
808 + * PTP clock operations
809 + */
810 +
811 +static int ptp_qoriq_adjfine(struct ptp_clock_info *ptp, long scaled_ppm)
812 +{
813 + u64 adj, diff;
814 + u32 tmr_add;
815 + int neg_adj = 0;
816 + struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
817 + struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
818 +
819 + if (scaled_ppm < 0) {
820 + neg_adj = 1;
821 + scaled_ppm = -scaled_ppm;
822 + }
823 + tmr_add = qoriq_ptp->tmr_add;
824 + adj = tmr_add;
825 +
826 + /* calculate diff as adj*(scaled_ppm/65536)/1000000
827 + * and round() to the nearest integer
828 + */
829 + adj *= scaled_ppm;
830 + diff = div_u64(adj, 8000000);
831 + diff = (diff >> 13) + ((diff >> 12) & 1);
832 +
833 + tmr_add = neg_adj ? tmr_add - diff : tmr_add + diff;
834 +
835 + qoriq_write(&regs->ctrl_regs->tmr_add, tmr_add);
836 +
837 + return 0;
838 +}
839 +
840 +static int ptp_qoriq_adjtime(struct ptp_clock_info *ptp, s64 delta)
841 +{
842 + s64 now;
843 + unsigned long flags;
844 + struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
845 +
846 + spin_lock_irqsave(&qoriq_ptp->lock, flags);
847 +
848 + now = tmr_cnt_read(qoriq_ptp);
849 + now += delta;
850 + tmr_cnt_write(qoriq_ptp, now);
851 + set_fipers(qoriq_ptp);
852 +
853 + spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
854 +
855 + return 0;
856 +}
857 +
858 +static int ptp_qoriq_gettime(struct ptp_clock_info *ptp,
859 + struct timespec64 *ts)
860 +{
861 + u64 ns;
862 + unsigned long flags;
863 + struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
864 +
865 + spin_lock_irqsave(&qoriq_ptp->lock, flags);
866 +
867 + ns = tmr_cnt_read(qoriq_ptp);
868 +
869 + spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
870 +
871 + *ts = ns_to_timespec64(ns);
872 +
873 + return 0;
874 +}
875 +
876 +static int ptp_qoriq_settime(struct ptp_clock_info *ptp,
877 + const struct timespec64 *ts)
878 +{
879 + u64 ns;
880 + unsigned long flags;
881 + struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
882 +
883 + ns = timespec64_to_ns(ts);
884 +
885 + spin_lock_irqsave(&qoriq_ptp->lock, flags);
886 +
887 + tmr_cnt_write(qoriq_ptp, ns);
888 + set_fipers(qoriq_ptp);
889 +
890 + spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
891 +
892 + return 0;
893 +}
894 +
895 +static int ptp_qoriq_enable(struct ptp_clock_info *ptp,
896 + struct ptp_clock_request *rq, int on)
897 +{
898 + struct qoriq_ptp *qoriq_ptp = container_of(ptp, struct qoriq_ptp, caps);
899 + struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
900 + unsigned long flags;
901 + u32 bit, mask;
902 +
903 + switch (rq->type) {
904 + case PTP_CLK_REQ_EXTTS:
905 + switch (rq->extts.index) {
906 + case 0:
907 + bit = ETS1EN;
908 + break;
909 + case 1:
910 + bit = ETS2EN;
911 + break;
912 + default:
913 + return -EINVAL;
914 + }
915 + spin_lock_irqsave(&qoriq_ptp->lock, flags);
916 + mask = qoriq_read(&regs->ctrl_regs->tmr_temask);
917 + if (on)
918 + mask |= bit;
919 + else
920 + mask &= ~bit;
921 + qoriq_write(&regs->ctrl_regs->tmr_temask, mask);
922 + spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
923 + return 0;
924 +
925 + case PTP_CLK_REQ_PPS:
926 + spin_lock_irqsave(&qoriq_ptp->lock, flags);
927 + mask = qoriq_read(&regs->ctrl_regs->tmr_temask);
928 + if (on)
929 + mask |= PP1EN;
930 + else
931 + mask &= ~PP1EN;
932 + qoriq_write(&regs->ctrl_regs->tmr_temask, mask);
933 + spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
934 + return 0;
935 +
936 + default:
937 + break;
938 + }
939 +
940 + return -EOPNOTSUPP;
941 +}
942 +
943 +static const struct ptp_clock_info ptp_qoriq_caps = {
944 + .owner = THIS_MODULE,
945 + .name = "qoriq ptp clock",
946 + .max_adj = 512000,
947 + .n_alarm = 0,
948 + .n_ext_ts = N_EXT_TS,
949 + .n_per_out = 0,
950 + .n_pins = 0,
951 + .pps = 1,
952 + .adjfine = ptp_qoriq_adjfine,
953 + .adjtime = ptp_qoriq_adjtime,
954 + .gettime64 = ptp_qoriq_gettime,
955 + .settime64 = ptp_qoriq_settime,
956 + .enable = ptp_qoriq_enable,
957 +};
958 +
959 +/**
960 + * qoriq_ptp_nominal_freq - calculate nominal frequency according to
961 + * reference clock frequency
962 + *
963 + * @clk_src: reference clock frequency
964 + *
965 + * The nominal frequency is the desired clock frequency.
966 + * It should be less than the reference clock frequency.
967 + * It should be a factor of 1000MHz.
968 + *
969 + * Return the nominal frequency
970 + */
971 +static u32 qoriq_ptp_nominal_freq(u32 clk_src)
972 +{
973 + u32 remainder = 0;
974 +
975 + clk_src /= 1000000;
976 + remainder = clk_src % 100;
977 + if (remainder) {
978 + clk_src -= remainder;
979 + clk_src += 100;
980 + }
981 +
982 + do {
983 + clk_src -= 100;
984 +
985 + } while (1000 % clk_src);
986 +
987 + return clk_src * 1000000;
988 +}
989 +
990 +/**
991 + * qoriq_ptp_auto_config - calculate a set of default configurations
992 + *
993 + * @qoriq_ptp: pointer to qoriq_ptp
994 + * @node: pointer to device_node
995 + *
996 + * If below dts properties are not provided, this function will be
997 + * called to calculate a set of default configurations for them.
998 + * "fsl,tclk-period"
999 + * "fsl,tmr-prsc"
1000 + * "fsl,tmr-add"
1001 + * "fsl,tmr-fiper1"
1002 + * "fsl,tmr-fiper2"
1003 + * "fsl,max-adj"
1004 + *
1005 + * Return 0 if success
1006 + */
1007 +static int qoriq_ptp_auto_config(struct qoriq_ptp *qoriq_ptp,
1008 + struct device_node *node)
1009 +{
1010 + struct clk *clk;
1011 + u64 freq_comp;
1012 + u64 max_adj;
1013 + u32 nominal_freq;
1014 + u32 remainder = 0;
1015 + u32 clk_src = 0;
1016 +
1017 + qoriq_ptp->cksel = DEFAULT_CKSEL;
1018 +
1019 + clk = of_clk_get(node, 0);
1020 + if (!IS_ERR(clk)) {
1021 + clk_src = clk_get_rate(clk);
1022 + clk_put(clk);
1023 + }
1024 +
1025 + if (clk_src <= 100000000UL) {
1026 + pr_err("error reference clock value, or lower than 100MHz\n");
1027 + return -EINVAL;
1028 + }
1029 +
1030 + nominal_freq = qoriq_ptp_nominal_freq(clk_src);
1031 + if (!nominal_freq)
1032 + return -EINVAL;
1033 +
1034 + qoriq_ptp->tclk_period = 1000000000UL / nominal_freq;
1035 + qoriq_ptp->tmr_prsc = DEFAULT_TMR_PRSC;
1036 +
1037 + /* Calculate initial frequency compensation value for TMR_ADD register.
1038 + * freq_comp = ceil(2^32 / freq_ratio)
1039 + * freq_ratio = reference_clock_freq / nominal_freq
1040 + */
1041 + freq_comp = ((u64)1 << 32) * nominal_freq;
1042 + freq_comp = div_u64_rem(freq_comp, clk_src, &remainder);
1043 + if (remainder)
1044 + freq_comp++;
1045 +
1046 + qoriq_ptp->tmr_add = freq_comp;
1047 + qoriq_ptp->tmr_fiper1 = DEFAULT_FIPER1_PERIOD - qoriq_ptp->tclk_period;
1048 + qoriq_ptp->tmr_fiper2 = DEFAULT_FIPER2_PERIOD - qoriq_ptp->tclk_period;
1049 +
1050 + /* max_adj = 1000000000 * (freq_ratio - 1.0) - 1
1051 + * freq_ratio = reference_clock_freq / nominal_freq
1052 + */
1053 + max_adj = 1000000000ULL * (clk_src - nominal_freq);
1054 + max_adj = div_u64(max_adj, nominal_freq) - 1;
1055 + qoriq_ptp->caps.max_adj = max_adj;
1056 +
1057 + return 0;
1058 +}
1059 +
1060 +static int qoriq_ptp_probe(struct platform_device *dev)
1061 +{
1062 + struct device_node *node = dev->dev.of_node;
1063 + struct qoriq_ptp *qoriq_ptp;
1064 + struct qoriq_ptp_registers *regs;
1065 + struct timespec64 now;
1066 + int err = -ENOMEM;
1067 + u32 tmr_ctrl;
1068 + unsigned long flags;
1069 + void __iomem *base;
1070 +
1071 + qoriq_ptp = kzalloc(sizeof(*qoriq_ptp), GFP_KERNEL);
1072 + if (!qoriq_ptp)
1073 + goto no_memory;
1074 +
1075 + err = -EINVAL;
1076 +
1077 + qoriq_ptp->caps = ptp_qoriq_caps;
1078 +
1079 + if (of_property_read_u32(node, "fsl,cksel", &qoriq_ptp->cksel))
1080 + qoriq_ptp->cksel = DEFAULT_CKSEL;
1081 +
1082 + if (of_property_read_u32(node,
1083 + "fsl,tclk-period", &qoriq_ptp->tclk_period) ||
1084 + of_property_read_u32(node,
1085 + "fsl,tmr-prsc", &qoriq_ptp->tmr_prsc) ||
1086 + of_property_read_u32(node,
1087 + "fsl,tmr-add", &qoriq_ptp->tmr_add) ||
1088 + of_property_read_u32(node,
1089 + "fsl,tmr-fiper1", &qoriq_ptp->tmr_fiper1) ||
1090 + of_property_read_u32(node,
1091 + "fsl,tmr-fiper2", &qoriq_ptp->tmr_fiper2) ||
1092 + of_property_read_u32(node,
1093 + "fsl,max-adj", &qoriq_ptp->caps.max_adj)) {
1094 + pr_warn("device tree node missing required elements, try automatic configuration\n");
1095 +
1096 + if (qoriq_ptp_auto_config(qoriq_ptp, node))
1097 + goto no_config;
1098 + }
1099 +
1100 + err = -ENODEV;
1101 +
1102 + qoriq_ptp->irq = platform_get_irq(dev, 0);
1103 +
1104 + if (qoriq_ptp->irq < 0) {
1105 + pr_err("irq not in device tree\n");
1106 + goto no_node;
1107 + }
1108 + if (request_irq(qoriq_ptp->irq, isr, IRQF_SHARED, DRIVER, qoriq_ptp)) {
1109 + pr_err("request_irq failed\n");
1110 + goto no_node;
1111 + }
1112 +
1113 + qoriq_ptp->rsrc = platform_get_resource(dev, IORESOURCE_MEM, 0);
1114 + if (!qoriq_ptp->rsrc) {
1115 + pr_err("no resource\n");
1116 + goto no_resource;
1117 + }
1118 + if (request_resource(&iomem_resource, qoriq_ptp->rsrc)) {
1119 + pr_err("resource busy\n");
1120 + goto no_resource;
1121 + }
1122 +
1123 + spin_lock_init(&qoriq_ptp->lock);
1124 +
1125 + base = ioremap(qoriq_ptp->rsrc->start,
1126 + resource_size(qoriq_ptp->rsrc));
1127 + if (!base) {
1128 + pr_err("ioremap ptp registers failed\n");
1129 + goto no_ioremap;
1130 + }
1131 +
1132 + qoriq_ptp->base = base;
1133 +
1134 + if (of_device_is_compatible(node, "fsl,fman-ptp-timer")) {
1135 + qoriq_ptp->regs.ctrl_regs = base + FMAN_CTRL_REGS_OFFSET;
1136 + qoriq_ptp->regs.alarm_regs = base + FMAN_ALARM_REGS_OFFSET;
1137 + qoriq_ptp->regs.fiper_regs = base + FMAN_FIPER_REGS_OFFSET;
1138 + qoriq_ptp->regs.etts_regs = base + FMAN_ETTS_REGS_OFFSET;
1139 + } else {
1140 + qoriq_ptp->regs.ctrl_regs = base + CTRL_REGS_OFFSET;
1141 + qoriq_ptp->regs.alarm_regs = base + ALARM_REGS_OFFSET;
1142 + qoriq_ptp->regs.fiper_regs = base + FIPER_REGS_OFFSET;
1143 + qoriq_ptp->regs.etts_regs = base + ETTS_REGS_OFFSET;
1144 + }
1145 +
1146 + ktime_get_real_ts64(&now);
1147 + ptp_qoriq_settime(&qoriq_ptp->caps, &now);
1148 +
1149 + tmr_ctrl =
1150 + (qoriq_ptp->tclk_period & TCLK_PERIOD_MASK) << TCLK_PERIOD_SHIFT |
1151 + (qoriq_ptp->cksel & CKSEL_MASK) << CKSEL_SHIFT;
1152 +
1153 + spin_lock_irqsave(&qoriq_ptp->lock, flags);
1154 +
1155 + regs = &qoriq_ptp->regs;
1156 + qoriq_write(&regs->ctrl_regs->tmr_ctrl, tmr_ctrl);
1157 + qoriq_write(&regs->ctrl_regs->tmr_add, qoriq_ptp->tmr_add);
1158 + qoriq_write(&regs->ctrl_regs->tmr_prsc, qoriq_ptp->tmr_prsc);
1159 + qoriq_write(&regs->fiper_regs->tmr_fiper1, qoriq_ptp->tmr_fiper1);
1160 + qoriq_write(&regs->fiper_regs->tmr_fiper2, qoriq_ptp->tmr_fiper2);
1161 + set_alarm(qoriq_ptp);
1162 + qoriq_write(&regs->ctrl_regs->tmr_ctrl, tmr_ctrl|FIPERST|RTPE|TE|FRD);
1163 +
1164 + spin_unlock_irqrestore(&qoriq_ptp->lock, flags);
1165 +
1166 + qoriq_ptp->clock = ptp_clock_register(&qoriq_ptp->caps, &dev->dev);
1167 + if (IS_ERR(qoriq_ptp->clock)) {
1168 + err = PTR_ERR(qoriq_ptp->clock);
1169 + goto no_clock;
1170 + }
1171 + qoriq_ptp->phc_index = ptp_clock_index(qoriq_ptp->clock);
1172 +
1173 + platform_set_drvdata(dev, qoriq_ptp);
1174 +
1175 + return 0;
1176 +
1177 +no_clock:
1178 + iounmap(qoriq_ptp->base);
1179 +no_ioremap:
1180 + release_resource(qoriq_ptp->rsrc);
1181 +no_resource:
1182 + free_irq(qoriq_ptp->irq, qoriq_ptp);
1183 +no_config:
1184 +no_node:
1185 + kfree(qoriq_ptp);
1186 +no_memory:
1187 + return err;
1188 +}
1189 +
1190 +static int qoriq_ptp_remove(struct platform_device *dev)
1191 +{
1192 + struct qoriq_ptp *qoriq_ptp = platform_get_drvdata(dev);
1193 + struct qoriq_ptp_registers *regs = &qoriq_ptp->regs;
1194 +
1195 + qoriq_write(&regs->ctrl_regs->tmr_temask, 0);
1196 + qoriq_write(&regs->ctrl_regs->tmr_ctrl, 0);
1197 +
1198 + ptp_clock_unregister(qoriq_ptp->clock);
1199 + iounmap(qoriq_ptp->base);
1200 + release_resource(qoriq_ptp->rsrc);
1201 + free_irq(qoriq_ptp->irq, qoriq_ptp);
1202 + kfree(qoriq_ptp);
1203 +
1204 + return 0;
1205 +}
1206 +
1207 +static const struct of_device_id match_table[] = {
1208 + { .compatible = "fsl,etsec-ptp" },
1209 + { .compatible = "fsl,fman-ptp-timer" },
1210 + {},
1211 +};
1212 +MODULE_DEVICE_TABLE(of, match_table);
1213 +
1214 +static struct platform_driver qoriq_ptp_driver = {
1215 + .driver = {
1216 + .name = "ptp_qoriq",
1217 + .of_match_table = match_table,
1218 + },
1219 + .probe = qoriq_ptp_probe,
1220 + .remove = qoriq_ptp_remove,
1221 +};
1222 +
1223 +module_platform_driver(qoriq_ptp_driver);
1224 +
1225 +MODULE_AUTHOR("Richard Cochran <richardcochran@gmail.com>");
1226 +MODULE_DESCRIPTION("PTP clock for Freescale QorIQ 1588 timer");
1227 +MODULE_LICENSE("GPL");
1228 --- /dev/null
1229 +++ b/include/linux/fsl/ptp_qoriq.h
1230 @@ -0,0 +1,169 @@
1231 +// SPDX-License-Identifier: GPL-2.0
1232 +/*
1233 + * Copyright (C) 2010 OMICRON electronics GmbH
1234 + * Copyright 2018 NXP
1235 + */
1236 +#ifndef __PTP_QORIQ_H__
1237 +#define __PTP_QORIQ_H__
1238 +
1239 +#include <linux/io.h>
1240 +#include <linux/ptp_clock_kernel.h>
1241 +
1242 +/*
1243 + * qoriq ptp registers
1244 + */
1245 +struct ctrl_regs {
1246 + u32 tmr_ctrl; /* Timer control register */
1247 + u32 tmr_tevent; /* Timestamp event register */
1248 + u32 tmr_temask; /* Timer event mask register */
1249 + u32 tmr_pevent; /* Timestamp event register */
1250 + u32 tmr_pemask; /* Timer event mask register */
1251 + u32 tmr_stat; /* Timestamp status register */
1252 + u32 tmr_cnt_h; /* Timer counter high register */
1253 + u32 tmr_cnt_l; /* Timer counter low register */
1254 + u32 tmr_add; /* Timer drift compensation addend register */
1255 + u32 tmr_acc; /* Timer accumulator register */
1256 + u32 tmr_prsc; /* Timer prescale */
1257 + u8 res1[4];
1258 + u32 tmroff_h; /* Timer offset high */
1259 + u32 tmroff_l; /* Timer offset low */
1260 +};
1261 +
1262 +struct alarm_regs {
1263 + u32 tmr_alarm1_h; /* Timer alarm 1 high register */
1264 + u32 tmr_alarm1_l; /* Timer alarm 1 high register */
1265 + u32 tmr_alarm2_h; /* Timer alarm 2 high register */
1266 + u32 tmr_alarm2_l; /* Timer alarm 2 high register */
1267 +};
1268 +
1269 +struct fiper_regs {
1270 + u32 tmr_fiper1; /* Timer fixed period interval */
1271 + u32 tmr_fiper2; /* Timer fixed period interval */
1272 + u32 tmr_fiper3; /* Timer fixed period interval */
1273 +};
1274 +
1275 +struct etts_regs {
1276 + u32 tmr_etts1_h; /* Timestamp of general purpose external trigger */
1277 + u32 tmr_etts1_l; /* Timestamp of general purpose external trigger */
1278 + u32 tmr_etts2_h; /* Timestamp of general purpose external trigger */
1279 + u32 tmr_etts2_l; /* Timestamp of general purpose external trigger */
1280 +};
1281 +
1282 +struct qoriq_ptp_registers {
1283 + struct ctrl_regs __iomem *ctrl_regs;
1284 + struct alarm_regs __iomem *alarm_regs;
1285 + struct fiper_regs __iomem *fiper_regs;
1286 + struct etts_regs __iomem *etts_regs;
1287 +};
1288 +
1289 +/* Offset definitions for the four register groups */
1290 +#define CTRL_REGS_OFFSET 0x0
1291 +#define ALARM_REGS_OFFSET 0x40
1292 +#define FIPER_REGS_OFFSET 0x80
1293 +#define ETTS_REGS_OFFSET 0xa0
1294 +
1295 +#define FMAN_CTRL_REGS_OFFSET 0x80
1296 +#define FMAN_ALARM_REGS_OFFSET 0xb8
1297 +#define FMAN_FIPER_REGS_OFFSET 0xd0
1298 +#define FMAN_ETTS_REGS_OFFSET 0xe0
1299 +
1300 +
1301 +/* Bit definitions for the TMR_CTRL register */
1302 +#define ALM1P (1<<31) /* Alarm1 output polarity */
1303 +#define ALM2P (1<<30) /* Alarm2 output polarity */
1304 +#define FIPERST (1<<28) /* FIPER start indication */
1305 +#define PP1L (1<<27) /* Fiper1 pulse loopback mode enabled. */
1306 +#define PP2L (1<<26) /* Fiper2 pulse loopback mode enabled. */
1307 +#define TCLK_PERIOD_SHIFT (16) /* 1588 timer reference clock period. */
1308 +#define TCLK_PERIOD_MASK (0x3ff)
1309 +#define RTPE (1<<15) /* Record Tx Timestamp to PAL Enable. */
1310 +#define FRD (1<<14) /* FIPER Realignment Disable */
1311 +#define ESFDP (1<<11) /* External Tx/Rx SFD Polarity. */
1312 +#define ESFDE (1<<10) /* External Tx/Rx SFD Enable. */
1313 +#define ETEP2 (1<<9) /* External trigger 2 edge polarity */
1314 +#define ETEP1 (1<<8) /* External trigger 1 edge polarity */
1315 +#define COPH (1<<7) /* Generated clock output phase. */
1316 +#define CIPH (1<<6) /* External oscillator input clock phase */
1317 +#define TMSR (1<<5) /* Timer soft reset. */
1318 +#define BYP (1<<3) /* Bypass drift compensated clock */
1319 +#define TE (1<<2) /* 1588 timer enable. */
1320 +#define CKSEL_SHIFT (0) /* 1588 Timer reference clock source */
1321 +#define CKSEL_MASK (0x3)
1322 +
1323 +/* Bit definitions for the TMR_TEVENT register */
1324 +#define ETS2 (1<<25) /* External trigger 2 timestamp sampled */
1325 +#define ETS1 (1<<24) /* External trigger 1 timestamp sampled */
1326 +#define ALM2 (1<<17) /* Current time = alarm time register 2 */
1327 +#define ALM1 (1<<16) /* Current time = alarm time register 1 */
1328 +#define PP1 (1<<7) /* periodic pulse generated on FIPER1 */
1329 +#define PP2 (1<<6) /* periodic pulse generated on FIPER2 */
1330 +#define PP3 (1<<5) /* periodic pulse generated on FIPER3 */
1331 +
1332 +/* Bit definitions for the TMR_TEMASK register */
1333 +#define ETS2EN (1<<25) /* External trigger 2 timestamp enable */
1334 +#define ETS1EN (1<<24) /* External trigger 1 timestamp enable */
1335 +#define ALM2EN (1<<17) /* Timer ALM2 event enable */
1336 +#define ALM1EN (1<<16) /* Timer ALM1 event enable */
1337 +#define PP1EN (1<<7) /* Periodic pulse event 1 enable */
1338 +#define PP2EN (1<<6) /* Periodic pulse event 2 enable */
1339 +
1340 +/* Bit definitions for the TMR_PEVENT register */
1341 +#define TXP2 (1<<9) /* PTP transmitted timestamp im TXTS2 */
1342 +#define TXP1 (1<<8) /* PTP transmitted timestamp in TXTS1 */
1343 +#define RXP (1<<0) /* PTP frame has been received */
1344 +
1345 +/* Bit definitions for the TMR_PEMASK register */
1346 +#define TXP2EN (1<<9) /* Transmit PTP packet event 2 enable */
1347 +#define TXP1EN (1<<8) /* Transmit PTP packet event 1 enable */
1348 +#define RXPEN (1<<0) /* Receive PTP packet event enable */
1349 +
1350 +/* Bit definitions for the TMR_STAT register */
1351 +#define STAT_VEC_SHIFT (0) /* Timer general purpose status vector */
1352 +#define STAT_VEC_MASK (0x3f)
1353 +
1354 +/* Bit definitions for the TMR_PRSC register */
1355 +#define PRSC_OCK_SHIFT (0) /* Output clock division/prescale factor. */
1356 +#define PRSC_OCK_MASK (0xffff)
1357 +
1358 +
1359 +#define DRIVER "ptp_qoriq"
1360 +#define N_EXT_TS 2
1361 +
1362 +#define DEFAULT_CKSEL 1
1363 +#define DEFAULT_TMR_PRSC 2
1364 +#define DEFAULT_FIPER1_PERIOD 1000000000
1365 +#define DEFAULT_FIPER2_PERIOD 100000
1366 +
1367 +struct qoriq_ptp {
1368 + void __iomem *base;
1369 + struct qoriq_ptp_registers regs;
1370 + spinlock_t lock; /* protects regs */
1371 + struct ptp_clock *clock;
1372 + struct ptp_clock_info caps;
1373 + struct resource *rsrc;
1374 + int irq;
1375 + int phc_index;
1376 + u64 alarm_interval; /* for periodic alarm */
1377 + u64 alarm_value;
1378 + u32 tclk_period; /* nanoseconds */
1379 + u32 tmr_prsc;
1380 + u32 tmr_add;
1381 + u32 cksel;
1382 + u32 tmr_fiper1;
1383 + u32 tmr_fiper2;
1384 +};
1385 +
1386 +static inline u32 qoriq_read(unsigned __iomem *addr)
1387 +{
1388 + u32 val;
1389 +
1390 + val = ioread32be(addr);
1391 + return val;
1392 +}
1393 +
1394 +static inline void qoriq_write(unsigned __iomem *addr, u32 val)
1395 +{
1396 + iowrite32be(val, addr);
1397 +}
1398 +
1399 +#endif
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