ramips/mt7620: Name DTS files based on scheme
[openwrt/staging/dedeckeh.git] / target / linux / ramips / dts / mt7620a_head-weblink_hdrm200.dts
1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
2 /dts-v1/;
3
4 #include "mt7620a.dtsi"
5
6 #include <dt-bindings/gpio/gpio.h>
7 #include <dt-bindings/input/input.h>
8
9 / {
10 compatible = "head-weblink,hdrm200", "ralink,mt7620a-soc";
11 model = "Head Weblink HDRM200";
12
13 aliases {
14 led-boot = &led_system;
15 led-failsafe = &led_system;
16 led-running = &led_system;
17 led-upgrade = &led_system;
18 };
19
20 chosen {
21 bootargs = "console=ttyS1,57600";
22 };
23
24 leds {
25 compatible = "gpio-leds";
26
27 rssi {
28 label = "hdrm200:red:rssi";
29 gpios = <&gpio0 19 GPIO_ACTIVE_LOW>;
30 };
31
32 led_system: system {
33 label = "hdrm200:green:system";
34 gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
35 };
36
37 air {
38 label = "hdrm200:green:wifi";
39 gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
40 };
41 };
42
43 keys {
44 compatible = "gpio-keys-polled";
45 poll-interval = <20>;
46
47 wps {
48 label = "wps";
49 gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
50 linux,code = <KEY_WPS_BUTTON>;
51 };
52
53 reset {
54 label = "reset";
55 gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
56 linux,code = <KEY_RESTART>;
57 };
58 };
59 };
60
61 &spi0 {
62 status = "okay";
63
64 flash@0 {
65 compatible = "jedec,spi-nor";
66 reg = <0>;
67 spi-max-frequency = <10000000>;
68
69 partitions {
70 compatible = "fixed-partitions";
71 #address-cells = <1>;
72 #size-cells = <1>;
73
74 partition@0 {
75 label = "u-boot";
76 reg = <0x0 0x30000>;
77 read-only;
78 };
79
80 partition@30000 {
81 label = "u-boot-env";
82 reg = <0x30000 0x10000>;
83 read-only;
84 };
85
86 factory: partition@40000 {
87 label = "factory";
88 reg = <0x40000 0x10000>;
89 read-only;
90 };
91
92 firmware: partition@50000 {
93 compatible = "denx,uimage";
94 label = "firmware";
95 reg = <0x50000 0xfb0000>;
96 };
97 };
98 };
99 };
100
101 &gpio0 {
102 status = "okay";
103 };
104
105 &gpio1 {
106 status = "okay";
107 };
108
109 &gpio3 {
110 status = "okay";
111 };
112
113 &sdhci {
114 status = "okay";
115 };
116
117 &ehci {
118 status = "okay";
119 };
120
121 &ohci {
122 status = "okay";
123 };
124
125 &ethernet {
126 status = "okay";
127
128 mtd-mac-address = <&factory 0x4>;
129 pinctrl-names = "default";
130 pinctrl-0 = <&rgmii1_pins &rgmii2_pins &mdio_pins>;
131
132 port@4 {
133 status = "okay";
134 phy-handle = <&phy4>;
135 phy-mode = "rgmii";
136 };
137
138 port@5 {
139 status = "okay";
140 phy-handle = <&phy5>;
141 phy-mode = "rgmii";
142 };
143
144 mdio-bus {
145 status = "okay";
146
147 phy4: ethernet-phy@4 {
148 reg = <4>;
149 phy-mode = "rgmii";
150 };
151
152 phy5: ethernet-phy@5 {
153 reg = <5>;
154 phy-mode = "rgmii";
155 };
156 };
157 };
158
159 &wmac {
160 ralink,mtd-eeprom = <&factory 0>;
161 };
162
163 &pinctrl {
164 state_default: pinctrl0 {
165 default {
166 ralink,group = "i2c", "uartf", "pa", "spi refclk",
167 "wled";
168 ralink,function = "gpio";
169 };
170 };
171 };
172
173 &pcie {
174 status = "okay";
175 };
176
177 &pcie0 {
178 wifi@0,0 {
179 compatible = "mediatek,mt76";
180 reg = <0x0000 0 0 0 0>;
181 mediatek,mtd-eeprom = <&factory 0x8000>;
182 ieee80211-freq-limit = <5000000 6000000>;
183 };
184 };
185
186 &uart {
187 status = "okay";
188 };