--- /dev/null
+/*
+ * setup.S Copyright (C) 1991, 1992 Linus Torvalds
+ *
+ * setup.s is responsible for getting the system data from the BIOS,
+ * and putting them into the appropriate places in system memory.
+ * both setup.s and system has been loaded by the bootblock.
+ *
+ * This code asks the bios for memory/disk/other parameters, and
+ * puts them in a "safe" place: 0x90000-0x901FF, ie where the
+ * boot-block used to be. It is then up to the protected mode
+ * system to read them from there before the area is overwritten
+ * for buffer-blocks.
+ *
+ * Move PS/2 aux init code to psaux.c
+ * (troyer@saifr00.cfsat.Honeywell.COM) 03Oct92
+ *
+ * some changes and additional features by Christoph Niemann,
+ * March 1993/June 1994 (Christoph.Niemann@linux.org)
+ *
+ * add APM BIOS checking by Stephen Rothwell, May 1994
+ * (sfr@canb.auug.org.au)
+ *
+ * High load stuff, initrd support and position independency
+ * by Hans Lermen & Werner Almesberger, February 1996
+ * <lermen@elserv.ffm.fgan.de>, <almesber@lrc.epfl.ch>
+ *
+ * Video handling moved to video.S by Martin Mares, March 1996
+ * <mj@k332.feld.cvut.cz>
+ *
+ * Extended memory detection scheme retwiddled by orc@pell.chi.il.us (david
+ * parsons) to avoid loadlin confusion, July 1997
+ *
+ * Transcribed from Intel (as86) -> AT&T (gas) by Chris Noe, May 1999.
+ * <stiker@northlink.com>
+ *
+ * Fix to work around buggy BIOSes which don't use carry bit correctly
+ * and/or report extended memory in CX/DX for e801h memory size detection
+ * call. As a result the kernel got wrong figures. The int15/e801h docs
+ * from Ralf Brown interrupt list seem to indicate AX/BX should be used
+ * anyway. So to avoid breaking many machines (presumably there was a reason
+ * to orginally use CX/DX instead of AX/BX), we do a kludge to see
+ * if CX/DX have been changed in the e801 call and if so use AX/BX .
+ * Michael Miller, April 2001 <michaelm@mjmm.org>
+ *
+ * New A20 code ported from SYSLINUX by H. Peter Anvin. AMD Elan bugfixes
+ * by Robert Schwebel, December 2001 <robert@schwebel.de>
+ */
+
+#include <asm/segment.h>
+#include <linux/utsrelease.h>
+#include <linux/compile.h>
+#include <asm/boot.h>
+#include <asm/e820.h>
+#include <asm/page.h>
+#include <asm/setup.h>
+
+/* Signature words to ensure LILO loaded us right */
+#define SIG1 0xAA55
+#define SIG2 0x5A5A
+
+INITSEG = DEF_INITSEG # 0x9000, we move boot here, out of the way
+SYSSEG = DEF_SYSSEG # 0x1000, system loaded at 0x10000 (65536).
+SETUPSEG = DEF_SETUPSEG # 0x9020, this is the current segment
+ # ... and the former contents of CS
+
+DELTA_INITSEG = SETUPSEG - INITSEG # 0x0020
+
+.code16
+.globl begtext, begdata, begbss, endtext, enddata, endbss
+
+.text
+begtext:
+.data
+begdata:
+.bss
+begbss:
+.text
+
+start:
+ jmp trampoline
+
+# This is the setup header, and it must start at %cs:2 (old 0x9020:2)
+
+ .ascii "HdrS" # header signature
+ .word 0x0206 # header version number (>= 0x0105)
+ # or else old loadlin-1.5 will fail)
+realmode_swtch: .word 0, 0 # default_switch, SETUPSEG
+start_sys_seg: .word SYSSEG
+ .word kernel_version # pointing to kernel version string
+ # above section of header is compatible
+ # with loadlin-1.5 (header v1.5). Don't
+ # change it.
+
+type_of_loader: .byte 0 # = 0, old one (LILO, Loadlin,
+ # Bootlin, SYSLX, bootsect...)
+ # See Documentation/i386/boot.txt for
+ # assigned ids
+
+# flags, unused bits must be zero (RFU) bit within loadflags
+loadflags:
+LOADED_HIGH = 1 # If set, the kernel is loaded high
+CAN_USE_HEAP = 0x80 # If set, the loader also has set
+ # heap_end_ptr to tell how much
+ # space behind setup.S can be used for
+ # heap purposes.
+ # Only the loader knows what is free
+#ifndef __BIG_KERNEL__
+ .byte 0
+#else
+ .byte LOADED_HIGH
+#endif
+
+setup_move_size: .word 0x8000 # size to move, when setup is not
+ # loaded at 0x90000. We will move setup
+ # to 0x90000 then just before jumping
+ # into the kernel. However, only the
+ # loader knows how much data behind
+ # us also needs to be loaded.
+
+code32_start: # here loaders can put a different
+ # start address for 32-bit code.
+#ifndef __BIG_KERNEL__
+ .long 0x1000 # 0x1000 = default for zImage
+#else
+ .long 0x100000 # 0x100000 = default for big kernel
+#endif
+
+ramdisk_image: .long 0 # address of loaded ramdisk image
+ # Here the loader puts the 32-bit
+ # address where it loaded the image.
+ # This only will be read by the kernel.
+
+ramdisk_size: .long 0 # its size in bytes
+
+bootsect_kludge:
+ .long 0 # obsolete
+
+heap_end_ptr: .word modelist+1024 # (Header version 0x0201 or later)
+ # space from here (exclusive) down to
+ # end of setup code can be used by setup
+ # for local heap purposes.
+
+pad1: .word 0
+cmd_line_ptr: .long 0 # (Header version 0x0202 or later)
+ # If nonzero, a 32-bit pointer
+ # to the kernel command line.
+ # The command line should be
+ # located between the start of
+ # setup and the end of low
+ # memory (0xa0000), or it may
+ # get overwritten before it
+ # gets read. If this field is
+ # used, there is no longer
+ # anything magical about the
+ # 0x90000 segment; the setup
+ # can be located anywhere in
+ # low memory 0x10000 or higher.
+
+ramdisk_max: .long (-__PAGE_OFFSET-(512 << 20)-1) & 0x7fffffff
+ # (Header version 0x0203 or later)
+ # The highest safe address for
+ # the contents of an initrd
+
+kernel_alignment: .long CONFIG_PHYSICAL_ALIGN #physical addr alignment
+ #required for protected mode
+ #kernel
+#ifdef CONFIG_RELOCATABLE
+relocatable_kernel: .byte 1
+#else
+relocatable_kernel: .byte 0
+#endif
+pad2: .byte 0
+pad3: .word 0
+
+cmdline_size: .long COMMAND_LINE_SIZE-1 #length of the command line,
+ #added with boot protocol
+ #version 2.06
+
+trampoline: call start_of_setup
+ .align 16
+ # The offset at this point is 0x240
+ .space (0xeff-0x240+1) # E820 & EDD space (ending at 0xeff)
+# End of setup header #####################################################
+
+start_of_setup:
+# Bootlin depends on this being done early
+ movw $0x01500, %ax
+ movb $0x81, %dl
+ int $0x13
+
+#ifdef SAFE_RESET_DISK_CONTROLLER
+# Reset the disk controller.
+ movw $0x0000, %ax
+ movb $0x80, %dl
+ int $0x13
+#endif
+
+# Set %ds = %cs, we know that SETUPSEG = %cs at this point
+ movw %cs, %ax # aka SETUPSEG
+ movw %ax, %ds
+# Check signature at end of setup
+ cmpw $SIG1, setup_sig1
+ jne bad_sig
+
+ cmpw $SIG2, setup_sig2
+ jne bad_sig
+
+ jmp good_sig1
+
+# Routine to print asciiz string at ds:si
+prtstr:
+ lodsb
+ andb %al, %al
+ jz fin
+
+ call prtchr
+ jmp prtstr
+
+fin: ret
+
+# Space printing
+prtsp2: call prtspc # Print double space
+prtspc: movb $0x20, %al # Print single space (note: fall-thru)
+
+# Part of above routine, this one just prints ascii al
+prtchr: pushw %ax
+ pushw %cx
+ movw $7,%bx
+ movw $0x01, %cx
+ movb $0x0e, %ah
+ int $0x10
+ popw %cx
+ popw %ax
+ ret
+
+beep: movb $0x07, %al
+ jmp prtchr
+
+no_sig_mess: .string "No setup signature found ..."
+
+good_sig1:
+ jmp good_sig
+
+# We now have to find the rest of the setup code/data
+bad_sig:
+ movw %cs, %ax # SETUPSEG
+ subw $DELTA_INITSEG, %ax # INITSEG
+ movw %ax, %ds
+ xorb %bh, %bh
+ movb (497), %bl # get setup sect from bootsect
+ subw $4, %bx # LILO loads 4 sectors of setup
+ shlw $8, %bx # convert to words (1sect=2^8 words)
+ movw %bx, %cx
+ shrw $3, %bx # convert to segment
+ addw $SYSSEG, %bx
+ movw %bx, %cs:start_sys_seg
+# Move rest of setup code/data to here
+ movw $2048, %di # four sectors loaded by LILO
+ subw %si, %si
+ pushw %cs
+ popw %es
+ movw $SYSSEG, %ax
+ movw %ax, %ds
+ rep
+ movsw
+ movw %cs, %ax # aka SETUPSEG
+ movw %ax, %ds
+ cmpw $SIG1, setup_sig1
+ jne no_sig
+
+ cmpw $SIG2, setup_sig2
+ jne no_sig
+
+ jmp good_sig
+
+no_sig:
+ lea no_sig_mess, %si
+ call prtstr
+
+no_sig_loop:
+ hlt
+ jmp no_sig_loop
+
+good_sig:
+ movw %cs, %ax # aka SETUPSEG
+ subw $DELTA_INITSEG, %ax # aka INITSEG
+ movw %ax, %ds
+# Check if an old loader tries to load a big-kernel
+ testb $LOADED_HIGH, %cs:loadflags # Do we have a big kernel?
+ jz loader_ok # No, no danger for old loaders.
+
+ cmpb $0, %cs:type_of_loader # Do we have a loader that
+ # can deal with us?
+ jnz loader_ok # Yes, continue.
+
+ pushw %cs # No, we have an old loader,
+ popw %ds # die.
+ lea loader_panic_mess, %si
+ call prtstr
+
+ jmp no_sig_loop
+
+loader_panic_mess: .string "Wrong loader, giving up..."
+
+# check minimum cpuid
+# we do this here because it is the last place we can actually
+# show a user visible error message. Later the video modus
+# might be already messed up.
+loader_ok:
+ call verify_cpu
+ testl %eax,%eax
+ jz cpu_ok
+ movw %cs,%ax # aka SETUPSEG
+ movw %ax,%ds
+ lea cpu_panic_mess,%si
+ call prtstr
+1: jmp 1b
+
+cpu_panic_mess:
+ .asciz "PANIC: CPU too old for this kernel."
+
+#include "../kernel/verify_cpu.S"
+
+cpu_ok:
+# Get memory size (extended mem, kB)
+
+ xorl %eax, %eax
+ movl %eax, (0x1e0)
+#ifndef STANDARD_MEMORY_BIOS_CALL
+ movb %al, (E820NR)
+# Try three different memory detection schemes. First, try
+# e820h, which lets us assemble a memory map, then try e801h,
+# which returns a 32-bit memory size, and finally 88h, which
+# returns 0-64m
+
+# method E820H:
+# the memory map from hell. e820h returns memory classified into
+# a whole bunch of different types, and allows memory holes and
+# everything. We scan through this memory map and build a list
+# of the first 32 memory areas, which we return at [E820MAP].
+# This is documented at http://www.acpi.info/, in the ACPI 2.0 specification.
+
+#define SMAP 0x534d4150
+
+meme820:
+ xorl %ebx, %ebx # continuation counter
+ movw $E820MAP, %di # point into the whitelist
+ # so we can have the bios
+ # directly write into it.
+
+jmpe820:
+ movl $0x0000e820, %eax # e820, upper word zeroed
+ movl $SMAP, %edx # ascii 'SMAP'
+ movl $20, %ecx # size of the e820rec
+ pushw %ds # data record.
+ popw %es
+ int $0x15 # make the call
+ jc bail820 # fall to e801 if it fails
+
+ cmpl $SMAP, %eax # check the return is `SMAP'
+ jne bail820 # fall to e801 if it fails
+
+# cmpl $1, 16(%di) # is this usable memory?
+# jne again820
+
+ # If this is usable memory, we save it by simply advancing %di by
+ # sizeof(e820rec).
+ #
+good820:
+ movb (E820NR), %al # up to 128 entries
+ cmpb $E820MAX, %al
+ jae bail820
+
+ incb (E820NR)
+ movw %di, %ax
+ addw $20, %ax
+ movw %ax, %di
+again820:
+ cmpl $0, %ebx # check to see if
+ jne jmpe820 # %ebx is set to EOF
+bail820:
+
+
+# method E801H:
+# memory size is in 1k chunksizes, to avoid confusing loadlin.
+# we store the 0xe801 memory size in a completely different place,
+# because it will most likely be longer than 16 bits.
+# (use 1e0 because that's what Larry Augustine uses in his
+# alternative new memory detection scheme, and it's sensible
+# to write everything into the same place.)
+
+meme801:
+ stc # fix to work around buggy
+ xorw %cx,%cx # BIOSes which don't clear/set
+ xorw %dx,%dx # carry on pass/error of
+ # e801h memory size call
+ # or merely pass cx,dx though
+ # without changing them.
+ movw $0xe801, %ax
+ int $0x15
+ jc mem88
+
+ cmpw $0x0, %cx # Kludge to handle BIOSes
+ jne e801usecxdx # which report their extended
+ cmpw $0x0, %dx # memory in AX/BX rather than
+ jne e801usecxdx # CX/DX. The spec I have read
+ movw %ax, %cx # seems to indicate AX/BX
+ movw %bx, %dx # are more reasonable anyway...
+
+e801usecxdx:
+ andl $0xffff, %edx # clear sign extend
+ shll $6, %edx # and go from 64k to 1k chunks
+ movl %edx, (0x1e0) # store extended memory size
+ andl $0xffff, %ecx # clear sign extend
+ addl %ecx, (0x1e0) # and add lower memory into
+ # total size.
+
+# Ye Olde Traditional Methode. Returns the memory size (up to 16mb or
+# 64mb, depending on the bios) in ax.
+mem88:
+
+#endif
+ movb $0x88, %ah
+ int $0x15
+ movw %ax, (2)
+
+# Set the keyboard repeat rate to the max
+ movw $0x0305, %ax
+ xorw %bx, %bx
+ int $0x16
+
+#ifndef CONFIG_VGA_NOPROBE
+
+# Check for video adapter and its parameters and allow the
+# user to browse video modes.
+ call video # NOTE: we need %ds pointing
+ # to bootsector
+#endif
+
+# Get hd0 data...
+ xorw %ax, %ax
+ movw %ax, %ds
+ ldsw (4 * 0x41), %si
+ movw %cs, %ax # aka SETUPSEG
+ subw $DELTA_INITSEG, %ax # aka INITSEG
+ pushw %ax
+ movw %ax, %es
+ movw $0x0080, %di
+ movw $0x10, %cx
+ pushw %cx
+ cld
+ rep
+ movsb
+# Get hd1 data...
+ xorw %ax, %ax
+ movw %ax, %ds
+ ldsw (4 * 0x46), %si
+ popw %cx
+ popw %es
+ movw $0x0090, %di
+ rep
+ movsb
+# Check that there IS a hd1 :-)
+ movw $0x01500, %ax
+ movb $0x81, %dl
+ int $0x13
+ jc no_disk1
+
+ cmpb $3, %ah
+ je is_disk1
+
+no_disk1:
+ movw %cs, %ax # aka SETUPSEG
+ subw $DELTA_INITSEG, %ax # aka INITSEG
+ movw %ax, %es
+ movw $0x0090, %di
+ movw $0x10, %cx
+ xorw %ax, %ax
+ cld
+ rep
+ stosb
+is_disk1:
+# check for Micro Channel (MCA) bus
+ movw %cs, %ax # aka SETUPSEG
+ subw $DELTA_INITSEG, %ax # aka INITSEG
+ movw %ax, %ds
+ xorw %ax, %ax
+ movw %ax, (0xa0) # set table length to 0
+ movb $0xc0, %ah
+ stc
+ int $0x15 # moves feature table to es:bx
+ jc no_mca
+
+ pushw %ds
+ movw %es, %ax
+ movw %ax, %ds
+ movw %cs, %ax # aka SETUPSEG
+ subw $DELTA_INITSEG, %ax # aka INITSEG
+ movw %ax, %es
+ movw %bx, %si
+ movw $0xa0, %di
+ movw (%si), %cx
+ addw $2, %cx # table length is a short
+ cmpw $0x10, %cx
+ jc sysdesc_ok
+
+ movw $0x10, %cx # we keep only first 16 bytes
+sysdesc_ok:
+ rep
+ movsb
+ popw %ds
+no_mca:
+#ifdef CONFIG_X86_VOYAGER
+ movb $0xff, 0x40 # flag on config found
+ movb $0xc0, %al
+ mov $0xff, %ah
+ int $0x15 # put voyager config info at es:di
+ jc no_voyager
+ movw $0x40, %si # place voyager info in apm table
+ cld
+ movw $7, %cx
+voyager_rep:
+ movb %es:(%di), %al
+ movb %al,(%si)
+ incw %di
+ incw %si
+ decw %cx
+ jnz voyager_rep
+no_voyager:
+#endif
+# Check for PS/2 pointing device
+ movw %cs, %ax # aka SETUPSEG
+ subw $DELTA_INITSEG, %ax # aka INITSEG
+ movw %ax, %ds
+ movb $0, (0x1ff) # default is no pointing device
+ int $0x11 # int 0x11: equipment list
+ testb $0x04, %al # check if mouse installed
+ jz no_psmouse
+
+ movb $0xAA, (0x1ff) # device present
+no_psmouse:
+
+#if defined(CONFIG_X86_SPEEDSTEP_SMI) || defined(CONFIG_X86_SPEEDSTEP_SMI_MODULE)
+ movl $0x0000E980, %eax # IST Support
+ movl $0x47534943, %edx # Request value
+ int $0x15
+
+ movl %eax, (96)
+ movl %ebx, (100)
+ movl %ecx, (104)
+ movl %edx, (108)
+#endif
+
+#if defined(CONFIG_APM) || defined(CONFIG_APM_MODULE)
+# Then check for an APM BIOS...
+ # %ds points to the bootsector
+ movw $0, 0x40 # version = 0 means no APM BIOS
+ movw $0x05300, %ax # APM BIOS installation check
+ xorw %bx, %bx
+ int $0x15
+ jc done_apm_bios # Nope, no APM BIOS
+
+ cmpw $0x0504d, %bx # Check for "PM" signature
+ jne done_apm_bios # No signature, no APM BIOS
+
+ andw $0x02, %cx # Is 32 bit supported?
+ je done_apm_bios # No 32-bit, no (good) APM BIOS
+
+ movw $0x05304, %ax # Disconnect first just in case
+ xorw %bx, %bx
+ int $0x15 # ignore return code
+ movw $0x05303, %ax # 32 bit connect
+ xorl %ebx, %ebx
+ xorw %cx, %cx # paranoia :-)
+ xorw %dx, %dx # ...
+ xorl %esi, %esi # ...
+ xorw %di, %di # ...
+ int $0x15
+ jc no_32_apm_bios # Ack, error.
+
+ movw %ax, (66) # BIOS code segment
+ movl %ebx, (68) # BIOS entry point offset
+ movw %cx, (72) # BIOS 16 bit code segment
+ movw %dx, (74) # BIOS data segment
+ movl %esi, (78) # BIOS code segment lengths
+ movw %di, (82) # BIOS data segment length
+# Redo the installation check as the 32 bit connect
+# modifies the flags returned on some BIOSs
+ movw $0x05300, %ax # APM BIOS installation check
+ xorw %bx, %bx
+ xorw %cx, %cx # paranoia
+ int $0x15
+ jc apm_disconnect # error -> shouldn't happen
+
+ cmpw $0x0504d, %bx # check for "PM" signature
+ jne apm_disconnect # no sig -> shouldn't happen
+
+ movw %ax, (64) # record the APM BIOS version
+ movw %cx, (76) # and flags
+ jmp done_apm_bios
+
+apm_disconnect: # Tidy up
+ movw $0x05304, %ax # Disconnect
+ xorw %bx, %bx
+ int $0x15 # ignore return code
+
+ jmp done_apm_bios
+
+no_32_apm_bios:
+ andw $0xfffd, (76) # remove 32 bit support bit
+done_apm_bios:
+#endif
+
+#include "edd.S"
+
+# Now we want to move to protected mode ...
+ cmpw $0, %cs:realmode_swtch
+ jz rmodeswtch_normal
+
+ lcall *%cs:realmode_swtch
+
+ jmp rmodeswtch_end
+
+rmodeswtch_normal:
+ pushw %cs
+ call default_switch
+
+rmodeswtch_end:
+# Now we move the system to its rightful place ... but we check if we have a
+# big-kernel. In that case we *must* not move it ...
+ testb $LOADED_HIGH, %cs:loadflags
+ jz do_move0 # .. then we have a normal low
+ # loaded zImage
+ # .. or else we have a high
+ # loaded bzImage
+ jmp end_move # ... and we skip moving
+
+do_move0:
+ movw $0x100, %ax # start of destination segment
+ movw %cs, %bp # aka SETUPSEG
+ subw $DELTA_INITSEG, %bp # aka INITSEG
+ movw %cs:start_sys_seg, %bx # start of source segment
+ cld
+do_move:
+ movw %ax, %es # destination segment
+ incb %ah # instead of add ax,#0x100
+ movw %bx, %ds # source segment
+ addw $0x100, %bx
+ subw %di, %di
+ subw %si, %si
+ movw $0x800, %cx
+ rep
+ movsw
+ cmpw %bp, %bx # assume start_sys_seg > 0x200,
+ # so we will perhaps read one
+ # page more than needed, but
+ # never overwrite INITSEG
+ # because destination is a
+ # minimum one page below source
+ jb do_move
+
+end_move:
+# then we load the segment descriptors
+ movw %cs, %ax # aka SETUPSEG
+ movw %ax, %ds
+
+# Check whether we need to be downward compatible with version <=201
+ cmpl $0, cmd_line_ptr
+ jne end_move_self # loader uses version >=202 features
+ cmpb $0x20, type_of_loader
+ je end_move_self # bootsect loader, we know of it
+
+# Boot loader doesnt support boot protocol version 2.02.
+# If we have our code not at 0x90000, we need to move it there now.
+# We also then need to move the params behind it (commandline)
+# Because we would overwrite the code on the current IP, we move
+# it in two steps, jumping high after the first one.
+ movw %cs, %ax
+ cmpw $SETUPSEG, %ax
+ je end_move_self
+
+ cli # make sure we really have
+ # interrupts disabled !
+ # because after this the stack
+ # should not be used
+ subw $DELTA_INITSEG, %ax # aka INITSEG
+ movw %ss, %dx
+ cmpw %ax, %dx
+ jb move_self_1
+
+ addw $INITSEG, %dx
+ subw %ax, %dx # this will go into %ss after
+ # the move
+move_self_1:
+ movw %ax, %ds
+ movw $INITSEG, %ax # real INITSEG
+ movw %ax, %es
+ movw %cs:setup_move_size, %cx
+ std # we have to move up, so we use
+ # direction down because the
+ # areas may overlap
+ movw %cx, %di
+ decw %di
+ movw %di, %si
+ subw $move_self_here+0x200, %cx
+ rep
+ movsb
+ ljmp $SETUPSEG, $move_self_here
+
+move_self_here:
+ movw $move_self_here+0x200, %cx
+ rep
+ movsb
+ movw $SETUPSEG, %ax
+ movw %ax, %ds
+ movw %dx, %ss
+end_move_self: # now we are at the right place
+
+#
+# Enable A20. This is at the very best an annoying procedure.
+# A20 code ported from SYSLINUX 1.52-1.63 by H. Peter Anvin.
+# AMD Elan bug fix by Robert Schwebel.
+#
+
+#if defined(CONFIG_X86_ELAN)
+ movb $0x02, %al # alternate A20 gate
+ outb %al, $0x92 # this works on SC410/SC520
+a20_elan_wait:
+ call a20_test
+ jz a20_elan_wait
+ jmp a20_done
+#endif
+
+
+A20_TEST_LOOPS = 32 # Iterations per wait
+A20_ENABLE_LOOPS = 255 # Total loops to try
+
+
+#ifndef CONFIG_X86_VOYAGER
+a20_try_loop:
+
+ # First, see if we are on a system with no A20 gate.
+a20_none:
+ call a20_test
+ jnz a20_done
+
+ # Next, try the BIOS (INT 0x15, AX=0x2401)
+a20_bios:
+ movw $0x2401, %ax
+ pushfl # Be paranoid about flags
+ int $0x15
+ popfl
+
+ call a20_test
+ jnz a20_done
+
+ # Try enabling A20 through the keyboard controller
+#endif /* CONFIG_X86_VOYAGER */
+a20_kbc:
+ call empty_8042
+
+#ifndef CONFIG_X86_VOYAGER
+ call a20_test # Just in case the BIOS worked
+ jnz a20_done # but had a delayed reaction.
+#endif
+
+ movb $0xD1, %al # command write
+ outb %al, $0x64
+ call empty_8042
+
+ movb $0xDF, %al # A20 on
+ outb %al, $0x60
+ call empty_8042
+
+#ifndef CONFIG_X86_VOYAGER
+ # Wait until a20 really *is* enabled; it can take a fair amount of
+ # time on certain systems; Toshiba Tecras are known to have this
+ # problem.
+a20_kbc_wait:
+ xorw %cx, %cx
+a20_kbc_wait_loop:
+ call a20_test
+ jnz a20_done
+ loop a20_kbc_wait_loop
+
+ # Final attempt: use "configuration port A"
+a20_fast:
+ inb $0x92, %al # Configuration Port A
+ orb $0x02, %al # "fast A20" version
+ andb $0xFE, %al # don't accidentally reset
+ outb %al, $0x92
+
+ # Wait for configuration port A to take effect
+a20_fast_wait:
+ xorw %cx, %cx
+a20_fast_wait_loop:
+ call a20_test
+ jnz a20_done
+ loop a20_fast_wait_loop
+
+ # A20 is still not responding. Try frobbing it again.
+ #
+ decb (a20_tries)
+ jnz a20_try_loop
+
+ movw $a20_err_msg, %si
+ call prtstr
+
+a20_die:
+ hlt
+ jmp a20_die
+
+a20_tries:
+ .byte A20_ENABLE_LOOPS
+
+a20_err_msg:
+ .ascii "linux: fatal error: A20 gate not responding!"
+ .byte 13, 10, 0
+
+ # If we get here, all is good
+a20_done:
+
+#endif /* CONFIG_X86_VOYAGER */
+# set up gdt and idt and 32bit start address
+ lidt idt_48 # load idt with 0,0
+ xorl %eax, %eax # Compute gdt_base
+ movw %ds, %ax # (Convert %ds:gdt to a linear ptr)
+ shll $4, %eax
+ addl %eax, code32
+ addl $gdt, %eax
+ movl %eax, (gdt_48+2)
+ lgdt gdt_48 # load gdt with whatever is
+ # appropriate
+
+# make sure any possible coprocessor is properly reset..
+ xorw %ax, %ax
+ outb %al, $0xf0
+ call delay
+
+ outb %al, $0xf1
+ call delay
+
+# well, that went ok, I hope. Now we mask all interrupts - the rest
+# is done in init_IRQ().
+ movb $0xFF, %al # mask all interrupts for now
+ outb %al, $0xA1
+ call delay
+
+ movb $0xFB, %al # mask all irq's but irq2 which
+ outb %al, $0x21 # is cascaded
+
+# Well, that certainly wasn't fun :-(. Hopefully it works, and we don't
+# need no steenking BIOS anyway (except for the initial loading :-).
+# The BIOS-routine wants lots of unnecessary data, and it's less
+# "interesting" anyway. This is how REAL programmers do it.
+#
+# Well, now's the time to actually move into protected mode. To make
+# things as simple as possible, we do no register set-up or anything,
+# we let the gnu-compiled 32-bit programs do that. We just jump to
+# absolute address 0x1000 (or the loader supplied one),
+# in 32-bit protected mode.
+#
+# Note that the short jump isn't strictly needed, although there are
+# reasons why it might be a good idea. It won't hurt in any case.
+ movw $1, %ax # protected mode (PE) bit
+ lmsw %ax # This is it!
+ jmp flush_instr
+
+flush_instr:
+ xorw %bx, %bx # Flag to indicate a boot
+ xorl %esi, %esi # Pointer to real-mode code
+ movw %cs, %si
+ subw $DELTA_INITSEG, %si
+ shll $4, %esi # Convert to 32-bit pointer
+
+# jump to startup_32 in arch/i386/boot/compressed/head.S
+#
+# NOTE: For high loaded big kernels we need a
+# jmpi 0x100000,__BOOT_CS
+#
+# but we yet haven't reloaded the CS register, so the default size
+# of the target offset still is 16 bit.
+# However, using an operand prefix (0x66), the CPU will properly
+# take our 48 bit far pointer. (INTeL 80386 Programmer's Reference
+# Manual, Mixing 16-bit and 32-bit code, page 16-6)
+
+ .byte 0x66, 0xea # prefix + jmpi-opcode
+code32: .long startup_32 # will be set to %cs+startup_32
+ .word __BOOT_CS
+.code32
+startup_32:
+ movl $(__BOOT_DS), %eax
+ movl %eax, %ds
+ movl %eax, %es
+ movl %eax, %fs
+ movl %eax, %gs
+ movl %eax, %ss
+
+ xorl %eax, %eax
+1: incl %eax # check that A20 really IS enabled
+ movl %eax, 0x00000000 # loop forever if it isn't
+ cmpl %eax, 0x00100000
+ je 1b
+
+ # Jump to the 32bit entry point
+ jmpl *(code32_start - start + (DELTA_INITSEG << 4))(%esi)
+.code16
+
+# Here's a bunch of information about your current kernel..
+kernel_version: .ascii UTS_RELEASE
+ .ascii " ("
+ .ascii LINUX_COMPILE_BY
+ .ascii "@"
+ .ascii LINUX_COMPILE_HOST
+ .ascii ") "
+ .ascii UTS_VERSION
+ .byte 0
+
+# This is the default real mode switch routine.
+# to be called just before protected mode transition
+default_switch:
+ cli # no interrupts allowed !
+ movb $0x80, %al # disable NMI for bootup
+ # sequence
+ outb %al, $0x70
+ lret
+
+
+#ifndef CONFIG_X86_VOYAGER
+# This routine tests whether or not A20 is enabled. If so, it
+# exits with zf = 0.
+#
+# The memory address used, 0x200, is the int $0x80 vector, which
+# should be safe.
+
+A20_TEST_ADDR = 4*0x80
+
+a20_test:
+ pushw %cx
+ pushw %ax
+ xorw %cx, %cx
+ movw %cx, %fs # Low memory
+ decw %cx
+ movw %cx, %gs # High memory area
+ movw $A20_TEST_LOOPS, %cx
+ movw %fs:(A20_TEST_ADDR), %ax
+ pushw %ax
+a20_test_wait:
+ incw %ax
+ movw %ax, %fs:(A20_TEST_ADDR)
+ call delay # Serialize and make delay constant
+ cmpw %gs:(A20_TEST_ADDR+0x10), %ax
+ loope a20_test_wait
+
+ popw %fs:(A20_TEST_ADDR)
+ popw %ax
+ popw %cx
+ ret
+
+#endif /* CONFIG_X86_VOYAGER */
+
+# This routine checks that the keyboard command queue is empty
+# (after emptying the output buffers)
+#
+# Some machines have delusions that the keyboard buffer is always full
+# with no keyboard attached...
+#
+# If there is no keyboard controller, we will usually get 0xff
+# to all the reads. With each IO taking a microsecond and
+# a timeout of 100,000 iterations, this can take about half a
+# second ("delay" == outb to port 0x80). That should be ok,
+# and should also be plenty of time for a real keyboard controller
+# to empty.
+#
+
+empty_8042:
+ pushl %ecx
+ movl $100000, %ecx
+
+empty_8042_loop:
+ decl %ecx
+ jz empty_8042_end_loop
+
+ call delay
+
+ inb $0x64, %al # 8042 status port
+ testb $1, %al # output buffer?
+ jz no_output
+
+ call delay
+ inb $0x60, %al # read it
+ jmp empty_8042_loop
+
+no_output:
+ testb $2, %al # is input buffer full?
+ jnz empty_8042_loop # yes - loop
+empty_8042_end_loop:
+ popl %ecx
+ ret
+
+# Read the cmos clock. Return the seconds in al
+gettime:
+ pushw %cx
+ movb $0x02, %ah
+ int $0x1a
+ movb %dh, %al # %dh contains the seconds
+ andb $0x0f, %al
+ movb %dh, %ah
+ movb $0x04, %cl
+ shrb %cl, %ah
+ aad
+ popw %cx
+ ret
+
+# Delay is needed after doing I/O
+delay:
+ outb %al,$0x80
+ ret
+
+# Descriptor tables
+#
+# NOTE: The intel manual says gdt should be sixteen bytes aligned for
+# efficiency reasons. However, there are machines which are known not
+# to boot with misaligned GDTs, so alter this at your peril! If you alter
+# GDT_ENTRY_BOOT_CS (in asm/segment.h) remember to leave at least two
+# empty GDT entries (one for NULL and one reserved).
+#
+# NOTE: On some CPUs, the GDT must be 8 byte aligned. This is
+# true for the Voyager Quad CPU card which will not boot without
+# This directive. 16 byte aligment is recommended by intel.
+#
+ .align 16
+gdt:
+ .fill GDT_ENTRY_BOOT_CS,8,0
+
+ .word 0xFFFF # 4Gb - (0x100000*0x1000 = 4Gb)
+ .word 0 # base address = 0
+ .word 0x9A00 # code read/exec
+ .word 0x00CF # granularity = 4096, 386
+ # (+5th nibble of limit)
+
+ .word 0xFFFF # 4Gb - (0x100000*0x1000 = 4Gb)
+ .word 0 # base address = 0
+ .word 0x9200 # data read/write
+ .word 0x00CF # granularity = 4096, 386
+ # (+5th nibble of limit)
+gdt_end:
+ .align 4
+
+ .word 0 # alignment byte
+idt_48:
+ .word 0 # idt limit = 0
+ .word 0, 0 # idt base = 0L
+
+ .word 0 # alignment byte
+gdt_48:
+ .word gdt_end - gdt - 1 # gdt limit
+ .word 0, 0 # gdt base (filled in later)
+
+#ifndef CONFIG_VGA_NOPROBE
+# Include video setup & detection code
+
+#include "video.S"
+#endif
+
+# Setup signature -- must be last
+setup_sig1: .word SIG1
+setup_sig2: .word SIG2
+
+# After this point, there is some free space which is used by the video mode
+# handling code to store the temporary mode table (not used by the kernel).
+
+modelist:
+
+.text
+endtext:
+.data
+enddata:
+.bss
+endbss:
--- /dev/null
+#
+# Automatically generated make config: don't edit
+# Linux kernel version: 2.6.22-rc5
+# Wed Jun 20 08:26:53 2007
+#
+CONFIG_X86_32=y
+CONFIG_GENERIC_TIME=y
+CONFIG_CLOCKSOURCE_WATCHDOG=y
+CONFIG_GENERIC_CLOCKEVENTS=y
+CONFIG_LOCKDEP_SUPPORT=y
+CONFIG_STACKTRACE_SUPPORT=y
+CONFIG_SEMAPHORE_SLEEPERS=y
+CONFIG_X86=y
+CONFIG_MMU=y
+CONFIG_ZONE_DMA=y
+CONFIG_QUICKLIST=y
+CONFIG_GENERIC_ISA_DMA=y
+CONFIG_GENERIC_IOMAP=y
+CONFIG_GENERIC_BUG=y
+CONFIG_GENERIC_HWEIGHT=y
+CONFIG_ARCH_MAY_HAVE_PC_FDC=y
+CONFIG_DMI=y
+CONFIG_DEFCONFIG_LIST="/lib/modules/$UNAME_RELEASE/.config"
+
+#
+# Code maturity level options
+#
+CONFIG_EXPERIMENTAL=y
+CONFIG_BROKEN_ON_SMP=y
+CONFIG_LOCK_KERNEL=y
+CONFIG_INIT_ENV_ARG_LIMIT=32
+
+#
+# General setup
+#
+CONFIG_LOCALVERSION=""
+# CONFIG_LOCALVERSION_AUTO is not set
+CONFIG_SWAP=y
+CONFIG_SYSVIPC=y
+# CONFIG_IPC_NS is not set
+CONFIG_SYSVIPC_SYSCTL=y
+CONFIG_POSIX_MQUEUE=y
+CONFIG_BSD_PROCESS_ACCT=y
+# CONFIG_BSD_PROCESS_ACCT_V3 is not set
+# CONFIG_TASKSTATS is not set
+# CONFIG_UTS_NS is not set
+CONFIG_AUDIT=y
+CONFIG_AUDITSYSCALL=y
+# CONFIG_IKCONFIG is not set
+CONFIG_LOG_BUF_SHIFT=17
+# CONFIG_SYSFS_DEPRECATED is not set
+CONFIG_RELAY=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_INITRAMFS_SOURCE=""
+CONFIG_CC_OPTIMIZE_FOR_SIZE=y
+CONFIG_SYSCTL=y
+CONFIG_EMBEDDED=y
+CONFIG_UID16=y
+# CONFIG_SYSCTL_SYSCALL is not set
+CONFIG_KALLSYMS=y
+# CONFIG_KALLSYMS_ALL is not set
+CONFIG_KALLSYMS_EXTRA_PASS=y
+CONFIG_HOTPLUG=y
+CONFIG_PRINTK=y
+CONFIG_BUG=y
+CONFIG_ELF_CORE=y
+# CONFIG_BASE_FULL is not set
+CONFIG_FUTEX=y
+CONFIG_ANON_INODES=y
+CONFIG_EPOLL=y
+CONFIG_SIGNALFD=y
+CONFIG_TIMERFD=y
+CONFIG_EVENTFD=y
+CONFIG_SHMEM=y
+CONFIG_VM_EVENT_COUNTERS=y
+CONFIG_SLAB=y
+# CONFIG_SLUB is not set
+# CONFIG_SLOB is not set
+CONFIG_RT_MUTEXES=y
+# CONFIG_TINY_SHMEM is not set
+CONFIG_BASE_SMALL=1
+
+#
+# Loadable module support
+#
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+# CONFIG_MODULE_FORCE_UNLOAD is not set
+CONFIG_MODVERSIONS=y
+CONFIG_MODULE_SRCVERSION_ALL=y
+CONFIG_KMOD=y
+
+#
+# Block layer
+#
+CONFIG_BLOCK=y
+# CONFIG_LBD is not set
+# CONFIG_BLK_DEV_IO_TRACE is not set
+# CONFIG_LSF is not set
+
+#
+# IO Schedulers
+#
+CONFIG_IOSCHED_NOOP=y
+# CONFIG_IOSCHED_AS is not set
+# CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_IOSCHED_CFQ=y
+# CONFIG_DEFAULT_AS is not set
+# CONFIG_DEFAULT_DEADLINE is not set
+CONFIG_DEFAULT_CFQ=y
+# CONFIG_DEFAULT_NOOP is not set
+CONFIG_DEFAULT_IOSCHED="cfq"
+
+#
+# Processor type and features
+#
+CONFIG_TICK_ONESHOT=y
+CONFIG_NO_HZ=y
+CONFIG_HIGH_RES_TIMERS=y
+# CONFIG_SMP is not set
+CONFIG_X86_PC=y
+# CONFIG_X86_ELAN is not set
+# CONFIG_X86_VOYAGER is not set
+# CONFIG_X86_NUMAQ is not set
+# CONFIG_X86_SUMMIT is not set
+# CONFIG_X86_BIGSMP is not set
+# CONFIG_X86_VISWS is not set
+# CONFIG_X86_GENERICARCH is not set
+# CONFIG_X86_ES7000 is not set
+# CONFIG_PARAVIRT is not set
+# CONFIG_M386 is not set
+# CONFIG_M486 is not set
+# CONFIG_M586 is not set
+# CONFIG_M586TSC is not set
+# CONFIG_M586MMX is not set
+# CONFIG_M686 is not set
+# CONFIG_MPENTIUMII is not set
+# CONFIG_MPENTIUMIII is not set
+# CONFIG_MPENTIUMM is not set
+# CONFIG_MCORE2 is not set
+# CONFIG_MPENTIUM4 is not set
+# CONFIG_MK6 is not set
+# CONFIG_MK7 is not set
+# CONFIG_MK8 is not set
+# CONFIG_MCRUSOE is not set
+# CONFIG_MEFFICEON is not set
+# CONFIG_MWINCHIPC6 is not set
+# CONFIG_MWINCHIP2 is not set
+# CONFIG_MWINCHIP3D is not set
+# CONFIG_MGEODEGX1 is not set
+CONFIG_MGEODE_LX=y
+# CONFIG_MCYRIXIII is not set
+# CONFIG_MVIAC3_2 is not set
+# CONFIG_MVIAC7 is not set
+# CONFIG_X86_GENERIC is not set
+CONFIG_X86_CMPXCHG=y
+CONFIG_X86_L1_CACHE_SHIFT=5
+CONFIG_X86_XADD=y
+CONFIG_RWSEM_XCHGADD_ALGORITHM=y
+# CONFIG_ARCH_HAS_ILOG2_U32 is not set
+# CONFIG_ARCH_HAS_ILOG2_U64 is not set
+CONFIG_GENERIC_CALIBRATE_DELAY=y
+CONFIG_X86_WP_WORKS_OK=y
+CONFIG_X86_INVLPG=y
+CONFIG_X86_BSWAP=y
+CONFIG_X86_POPAD_OK=y
+CONFIG_X86_USE_PPRO_CHECKSUM=y
+CONFIG_X86_USE_3DNOW=y
+CONFIG_X86_TSC=y
+CONFIG_X86_MINIMUM_CPU_MODEL=4
+# CONFIG_HPET_TIMER is not set
+# CONFIG_PREEMPT_NONE is not set
+# CONFIG_PREEMPT_VOLUNTARY is not set
+CONFIG_PREEMPT=y
+CONFIG_PREEMPT_BKL=y
+# CONFIG_X86_UP_APIC is not set
+# CONFIG_X86_MCE is not set
+# CONFIG_VM86 is not set
+# CONFIG_TOSHIBA is not set
+# CONFIG_I8K is not set
+CONFIG_X86_REBOOTFIXUPS=y
+# CONFIG_MICROCODE is not set
+CONFIG_X86_MSR=y
+CONFIG_X86_CPUID=m
+
+#
+# Firmware Drivers
+#
+# CONFIG_EDD is not set
+# CONFIG_DELL_RBU is not set
+# CONFIG_DCDBAS is not set
+CONFIG_NOHIGHMEM=y
+# CONFIG_HIGHMEM4G is not set
+# CONFIG_HIGHMEM64G is not set
+CONFIG_VMSPLIT_3G=y
+# CONFIG_VMSPLIT_3G_OPT is not set
+# CONFIG_VMSPLIT_2G is not set
+# CONFIG_VMSPLIT_2G_OPT is not set
+# CONFIG_VMSPLIT_1G is not set
+CONFIG_PAGE_OFFSET=0xC0000000
+CONFIG_ARCH_FLATMEM_ENABLE=y
+CONFIG_ARCH_SPARSEMEM_ENABLE=y
+CONFIG_ARCH_SELECT_MEMORY_MODEL=y
+CONFIG_ARCH_POPULATES_NODE_MAP=y
+CONFIG_SELECT_MEMORY_MODEL=y
+CONFIG_FLATMEM_MANUAL=y
+# CONFIG_DISCONTIGMEM_MANUAL is not set
+# CONFIG_SPARSEMEM_MANUAL is not set
+CONFIG_FLATMEM=y
+CONFIG_FLAT_NODE_MEM_MAP=y
+CONFIG_SPARSEMEM_STATIC=y
+CONFIG_SPLIT_PTLOCK_CPUS=4
+# CONFIG_RESOURCES_64BIT is not set
+CONFIG_ZONE_DMA_FLAG=1
+CONFIG_NR_QUICK=1
+# CONFIG_MATH_EMULATION is not set
+# CONFIG_MTRR is not set
+# CONFIG_SECCOMP is not set
+# CONFIG_VGA_NOPROBE is not set
+CONFIG_HZ_100=y
+# CONFIG_HZ_250 is not set
+# CONFIG_HZ_300 is not set
+# CONFIG_HZ_1000 is not set
+CONFIG_HZ=100
+CONFIG_KEXEC=y
+CONFIG_PHYSICAL_START=0x400000
+# CONFIG_RELOCATABLE is not set
+CONFIG_PHYSICAL_ALIGN=0x100000
+# CONFIG_COMPAT_VDSO is not set
+
+#
+# Power management options (ACPI, APM)
+#
+CONFIG_PM=y
+CONFIG_PM_LEGACY=y
+CONFIG_PM_DEBUG=y
+CONFIG_DISABLE_SUSPEND_VT_SWITCH=y
+# CONFIG_PM_TRACE is not set
+# CONFIG_PM_SYSFS_DEPRECATED is not set
+CONFIG_SOFTWARE_SUSPEND=y
+CONFIG_PM_STD_PARTITION=""
+
+#
+# ACPI (Advanced Configuration and Power Interface) Support
+#
+# CONFIG_ACPI is not set
+# CONFIG_APM is not set
+
+#
+# CPU Frequency scaling
+#
+# CONFIG_CPU_FREQ is not set
+
+#
+# Bus options (PCI, PCMCIA, EISA, MCA, ISA)
+#
+CONFIG_PCI=y
+# CONFIG_PCI_GOBIOS is not set
+# CONFIG_PCI_GOMMCONFIG is not set
+# CONFIG_PCI_GODIRECT is not set
+# CONFIG_PCI_GOANY is not set
+CONFIG_PCI_GOOLPC=y
+CONFIG_PCI_DIRECT=y
+CONFIG_PCI_OLPC=y
+# CONFIG_PCIEPORTBUS is not set
+# CONFIG_ARCH_SUPPORTS_MSI is not set
+# CONFIG_PCI_DEBUG is not set
+CONFIG_ISA_DMA_API=y
+# CONFIG_ISA is not set
+# CONFIG_MCA is not set
+# CONFIG_SCx200 is not set
+CONFIG_GEODE_MFGPT_TIMER=y
+CONFIG_OLPC=y
+CONFIG_OLPC_PM=y
+CONFIG_OPEN_FIRMWARE=y
+
+#
+# PCCARD (PCMCIA/CardBus) support
+#
+# CONFIG_PCCARD is not set
+# CONFIG_HOTPLUG_PCI is not set
+
+#
+# Executable file formats
+#
+CONFIG_BINFMT_ELF=y
+# CONFIG_BINFMT_AOUT is not set
+CONFIG_BINFMT_MISC=y
+
+#
+# Networking
+#
+CONFIG_NET=y
+
+#
+# Networking options
+#
+CONFIG_PACKET=y
+CONFIG_PACKET_MMAP=y
+CONFIG_UNIX=y
+CONFIG_XFRM=y
+CONFIG_XFRM_USER=y
+# CONFIG_XFRM_SUB_POLICY is not set
+CONFIG_XFRM_MIGRATE=y
+CONFIG_NET_KEY=m
+CONFIG_NET_KEY_MIGRATE=y
+CONFIG_INET=y
+CONFIG_IP_MULTICAST=y
+CONFIG_IP_ADVANCED_ROUTER=y
+CONFIG_ASK_IP_FIB_HASH=y
+# CONFIG_IP_FIB_TRIE is not set
+CONFIG_IP_FIB_HASH=y
+CONFIG_IP_MULTIPLE_TABLES=y
+CONFIG_IP_ROUTE_MULTIPATH=y
+# CONFIG_IP_ROUTE_MULTIPATH_CACHED is not set
+CONFIG_IP_ROUTE_VERBOSE=y
+# CONFIG_IP_PNP is not set
+# CONFIG_NET_IPIP is not set
+# CONFIG_NET_IPGRE is not set
+# CONFIG_IP_MROUTE is not set
+# CONFIG_ARPD is not set
+CONFIG_SYN_COOKIES=y
+CONFIG_INET_AH=m
+CONFIG_INET_ESP=m
+CONFIG_INET_IPCOMP=m
+CONFIG_INET_XFRM_TUNNEL=m
+CONFIG_INET_TUNNEL=m
+CONFIG_INET_XFRM_MODE_TRANSPORT=y
+CONFIG_INET_XFRM_MODE_TUNNEL=y
+CONFIG_INET_XFRM_MODE_BEET=y
+# CONFIG_INET_DIAG is not set
+CONFIG_TCP_CONG_ADVANCED=y
+CONFIG_TCP_CONG_BIC=y
+CONFIG_TCP_CONG_CUBIC=m
+CONFIG_TCP_CONG_WESTWOOD=m
+CONFIG_TCP_CONG_HTCP=m
+CONFIG_TCP_CONG_HSTCP=m
+CONFIG_TCP_CONG_HYBLA=m
+CONFIG_TCP_CONG_VEGAS=m
+CONFIG_TCP_CONG_SCALABLE=m
+CONFIG_TCP_CONG_LP=m
+CONFIG_TCP_CONG_VENO=m
+CONFIG_TCP_CONG_YEAH=m
+CONFIG_TCP_CONG_ILLINOIS=m
+CONFIG_DEFAULT_BIC=y
+# CONFIG_DEFAULT_CUBIC is not set
+# CONFIG_DEFAULT_HTCP is not set
+# CONFIG_DEFAULT_VEGAS is not set
+# CONFIG_DEFAULT_WESTWOOD is not set
+# CONFIG_DEFAULT_RENO is not set
+CONFIG_DEFAULT_TCP_CONG="bic"
+# CONFIG_TCP_MD5SIG is not set
+# CONFIG_IP_VS is not set
+CONFIG_IPV6=y
+CONFIG_IPV6_PRIVACY=y
+CONFIG_IPV6_ROUTER_PREF=y
+CONFIG_IPV6_ROUTE_INFO=y
+CONFIG_IPV6_OPTIMISTIC_DAD=y
+CONFIG_INET6_AH=m
+CONFIG_INET6_ESP=m
+CONFIG_INET6_IPCOMP=m
+CONFIG_IPV6_MIP6=y
+CONFIG_INET6_XFRM_TUNNEL=m
+CONFIG_INET6_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_TRANSPORT=m
+CONFIG_INET6_XFRM_MODE_TUNNEL=m
+CONFIG_INET6_XFRM_MODE_BEET=m
+CONFIG_INET6_XFRM_MODE_ROUTEOPTIMIZATION=m
+CONFIG_IPV6_SIT=m
+CONFIG_IPV6_TUNNEL=m
+CONFIG_IPV6_MULTIPLE_TABLES=y
+CONFIG_IPV6_SUBTREES=y
+# CONFIG_NETLABEL is not set
+CONFIG_NETWORK_SECMARK=y
+CONFIG_NETFILTER=y
+# CONFIG_NETFILTER_DEBUG is not set
+
+#
+# Core Netfilter Configuration
+#
+CONFIG_NETFILTER_NETLINK=m
+# CONFIG_NETFILTER_NETLINK_QUEUE is not set
+# CONFIG_NETFILTER_NETLINK_LOG is not set
+CONFIG_NF_CONNTRACK_ENABLED=m
+CONFIG_NF_CONNTRACK=m
+# CONFIG_NF_CT_ACCT is not set
+# CONFIG_NF_CONNTRACK_MARK is not set
+# CONFIG_NF_CONNTRACK_SECMARK is not set
+# CONFIG_NF_CONNTRACK_EVENTS is not set
+# CONFIG_NF_CT_PROTO_SCTP is not set
+# CONFIG_NF_CONNTRACK_AMANDA is not set
+CONFIG_NF_CONNTRACK_FTP=m
+# CONFIG_NF_CONNTRACK_H323 is not set
+CONFIG_NF_CONNTRACK_IRC=m
+# CONFIG_NF_CONNTRACK_NETBIOS_NS is not set
+# CONFIG_NF_CONNTRACK_PPTP is not set
+# CONFIG_NF_CONNTRACK_SANE is not set
+# CONFIG_NF_CONNTRACK_SIP is not set
+# CONFIG_NF_CONNTRACK_TFTP is not set
+# CONFIG_NF_CT_NETLINK is not set
+CONFIG_NETFILTER_XTABLES=m
+# CONFIG_NETFILTER_XT_TARGET_CLASSIFY is not set
+# CONFIG_NETFILTER_XT_TARGET_MARK is not set
+# CONFIG_NETFILTER_XT_TARGET_NFQUEUE is not set
+CONFIG_NETFILTER_XT_TARGET_NFLOG=m
+# CONFIG_NETFILTER_XT_TARGET_SECMARK is not set
+# CONFIG_NETFILTER_XT_TARGET_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_COMMENT is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNBYTES is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNMARK is not set
+# CONFIG_NETFILTER_XT_MATCH_CONNTRACK is not set
+# CONFIG_NETFILTER_XT_MATCH_DCCP is not set
+# CONFIG_NETFILTER_XT_MATCH_DSCP is not set
+# CONFIG_NETFILTER_XT_MATCH_ESP is not set
+# CONFIG_NETFILTER_XT_MATCH_HELPER is not set
+# CONFIG_NETFILTER_XT_MATCH_LENGTH is not set
+# CONFIG_NETFILTER_XT_MATCH_LIMIT is not set
+# CONFIG_NETFILTER_XT_MATCH_MAC is not set
+# CONFIG_NETFILTER_XT_MATCH_MARK is not set
+# CONFIG_NETFILTER_XT_MATCH_POLICY is not set
+# CONFIG_NETFILTER_XT_MATCH_MULTIPORT is not set
+# CONFIG_NETFILTER_XT_MATCH_PKTTYPE is not set
+# CONFIG_NETFILTER_XT_MATCH_QUOTA is not set
+# CONFIG_NETFILTER_XT_MATCH_REALM is not set
+# CONFIG_NETFILTER_XT_MATCH_SCTP is not set
+CONFIG_NETFILTER_XT_MATCH_STATE=m
+# CONFIG_NETFILTER_XT_MATCH_STATISTIC is not set
+# CONFIG_NETFILTER_XT_MATCH_STRING is not set
+# CONFIG_NETFILTER_XT_MATCH_TCPMSS is not set
+# CONFIG_NETFILTER_XT_MATCH_HASHLIMIT is not set
+
+#
+# IP: Netfilter Configuration
+#
+CONFIG_NF_CONNTRACK_IPV4=m
+CONFIG_NF_CONNTRACK_PROC_COMPAT=y
+# CONFIG_IP_NF_QUEUE is not set
+CONFIG_IP_NF_IPTABLES=m
+# CONFIG_IP_NF_MATCH_IPRANGE is not set
+# CONFIG_IP_NF_MATCH_TOS is not set
+# CONFIG_IP_NF_MATCH_RECENT is not set
+# CONFIG_IP_NF_MATCH_ECN is not set
+# CONFIG_IP_NF_MATCH_AH is not set
+# CONFIG_IP_NF_MATCH_TTL is not set
+# CONFIG_IP_NF_MATCH_OWNER is not set
+# CONFIG_IP_NF_MATCH_ADDRTYPE is not set
+CONFIG_IP_NF_FILTER=m
+# CONFIG_IP_NF_TARGET_REJECT is not set
+CONFIG_IP_NF_TARGET_LOG=m
+# CONFIG_IP_NF_TARGET_ULOG is not set
+CONFIG_NF_NAT=m
+CONFIG_NF_NAT_NEEDED=y
+CONFIG_IP_NF_TARGET_MASQUERADE=m
+# CONFIG_IP_NF_TARGET_REDIRECT is not set
+# CONFIG_IP_NF_TARGET_NETMAP is not set
+# CONFIG_IP_NF_TARGET_SAME is not set
+# CONFIG_NF_NAT_SNMP_BASIC is not set
+CONFIG_NF_NAT_FTP=m
+CONFIG_NF_NAT_IRC=m
+# CONFIG_NF_NAT_TFTP is not set
+# CONFIG_NF_NAT_AMANDA is not set
+# CONFIG_NF_NAT_PPTP is not set
+# CONFIG_NF_NAT_H323 is not set
+# CONFIG_NF_NAT_SIP is not set
+# CONFIG_IP_NF_MANGLE is not set
+# CONFIG_IP_NF_RAW is not set
+# CONFIG_IP_NF_ARPTABLES is not set
+
+#
+# IPv6: Netfilter Configuration (EXPERIMENTAL)
+#
+# CONFIG_NF_CONNTRACK_IPV6 is not set
+# CONFIG_IP6_NF_QUEUE is not set
+# CONFIG_IP6_NF_IPTABLES is not set
+# CONFIG_IP_DCCP is not set
+# CONFIG_IP_SCTP is not set
+# CONFIG_TIPC is not set
+# CONFIG_ATM is not set
+# CONFIG_BRIDGE is not set
+# CONFIG_VLAN_8021Q is not set
+# CONFIG_DECNET is not set
+# CONFIG_LLC2 is not set
+# CONFIG_IPX is not set
+# CONFIG_ATALK is not set
+# CONFIG_X25 is not set
+# CONFIG_LAPB is not set
+# CONFIG_ECONET is not set
+# CONFIG_WAN_ROUTER is not set
+
+#
+# QoS and/or fair queueing
+#
+CONFIG_NET_SCHED=y
+CONFIG_NET_SCH_FIFO=y
+
+#
+# Queueing/Scheduling
+#
+CONFIG_NET_SCH_CBQ=m
+CONFIG_NET_SCH_HTB=m
+CONFIG_NET_SCH_HFSC=m
+CONFIG_NET_SCH_PRIO=m
+CONFIG_NET_SCH_RED=m
+CONFIG_NET_SCH_SFQ=m
+CONFIG_NET_SCH_TEQL=m
+CONFIG_NET_SCH_TBF=m
+CONFIG_NET_SCH_GRED=m
+CONFIG_NET_SCH_DSMARK=m
+CONFIG_NET_SCH_NETEM=m
+CONFIG_NET_SCH_INGRESS=m
+
+#
+# Classification
+#
+CONFIG_NET_CLS=y
+CONFIG_NET_CLS_BASIC=m
+CONFIG_NET_CLS_TCINDEX=m
+CONFIG_NET_CLS_ROUTE4=m
+CONFIG_NET_CLS_ROUTE=y
+CONFIG_NET_CLS_FW=m
+CONFIG_NET_CLS_U32=m
+CONFIG_CLS_U32_PERF=y
+CONFIG_CLS_U32_MARK=y
+CONFIG_NET_CLS_RSVP=m
+CONFIG_NET_CLS_RSVP6=m
+CONFIG_NET_EMATCH=y
+CONFIG_NET_EMATCH_STACK=32
+CONFIG_NET_EMATCH_CMP=m
+CONFIG_NET_EMATCH_NBYTE=m
+CONFIG_NET_EMATCH_U32=m
+CONFIG_NET_EMATCH_META=m
+CONFIG_NET_EMATCH_TEXT=m
+CONFIG_NET_CLS_ACT=y
+CONFIG_NET_ACT_POLICE=m
+CONFIG_NET_ACT_GACT=m
+CONFIG_GACT_PROB=y
+CONFIG_NET_ACT_MIRRED=m
+# CONFIG_NET_ACT_IPT is not set
+CONFIG_NET_ACT_PEDIT=m
+CONFIG_NET_ACT_SIMP=m
+CONFIG_NET_CLS_IND=y
+CONFIG_NET_ESTIMATOR=y
+
+#
+# Network testing
+#
+# CONFIG_NET_PKTGEN is not set
+# CONFIG_NET_TCPPROBE is not set
+# CONFIG_HAMRADIO is not set
+# CONFIG_IRDA is not set
+# CONFIG_BT is not set
+# CONFIG_AF_RXRPC is not set
+CONFIG_FIB_RULES=y
+
+#
+# Wireless
+#
+# CONFIG_CFG80211 is not set
+CONFIG_WIRELESS_EXT=y
+# CONFIG_MAC80211 is not set
+CONFIG_IEEE80211=m
+# CONFIG_IEEE80211_DEBUG is not set
+CONFIG_IEEE80211_CRYPT_WEP=m
+CONFIG_IEEE80211_CRYPT_CCMP=m
+CONFIG_IEEE80211_CRYPT_TKIP=m
+CONFIG_IEEE80211_SOFTMAC=m
+CONFIG_IEEE80211_SOFTMAC_DEBUG=y
+# CONFIG_RFKILL is not set
+
+#
+# Device Drivers
+#
+
+#
+# Generic Driver Options
+#
+CONFIG_STANDALONE=y
+CONFIG_PREVENT_FIRMWARE_BUILD=y
+CONFIG_FW_LOADER=y
+# CONFIG_DEBUG_DRIVER is not set
+# CONFIG_DEBUG_DEVRES is not set
+# CONFIG_SYS_HYPERVISOR is not set
+
+#
+# Connector - unified userspace <-> kernelspace linker
+#
+# CONFIG_CONNECTOR is not set
+CONFIG_MTD=y
+# CONFIG_MTD_DEBUG is not set
+CONFIG_MTD_CONCAT=m
+CONFIG_MTD_PARTITIONS=y
+# CONFIG_MTD_REDBOOT_PARTS is not set
+# CONFIG_MTD_CMDLINE_PARTS is not set
+
+#
+# User Modules And Translation Layers
+#
+CONFIG_MTD_CHAR=m
+CONFIG_MTD_BLKDEVS=m
+CONFIG_MTD_BLOCK=m
+CONFIG_MTD_BLOCK_RO=m
+# CONFIG_FTL is not set
+# CONFIG_NFTL is not set
+# CONFIG_INFTL is not set
+# CONFIG_RFD_FTL is not set
+# CONFIG_SSFDC is not set
+# CONFIG_MTD_OOPS is not set
+
+#
+# RAM/ROM/Flash chip drivers
+#
+# CONFIG_MTD_CFI is not set
+# CONFIG_MTD_JEDECPROBE is not set
+CONFIG_MTD_MAP_BANK_WIDTH_1=y
+CONFIG_MTD_MAP_BANK_WIDTH_2=y
+CONFIG_MTD_MAP_BANK_WIDTH_4=y
+# CONFIG_MTD_MAP_BANK_WIDTH_8 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_16 is not set
+# CONFIG_MTD_MAP_BANK_WIDTH_32 is not set
+CONFIG_MTD_CFI_I1=y
+CONFIG_MTD_CFI_I2=y
+# CONFIG_MTD_CFI_I4 is not set
+# CONFIG_MTD_CFI_I8 is not set
+# CONFIG_MTD_RAM is not set
+# CONFIG_MTD_ROM is not set
+# CONFIG_MTD_ABSENT is not set
+
+#
+# Mapping drivers for chip access
+#
+# CONFIG_MTD_COMPLEX_MAPPINGS is not set
+# CONFIG_MTD_TS5500 is not set
+# CONFIG_MTD_PLATRAM is not set
+
+#
+# Self-contained MTD device drivers
+#
+# CONFIG_MTD_PMC551 is not set
+# CONFIG_MTD_SLRAM is not set
+# CONFIG_MTD_PHRAM is not set
+# CONFIG_MTD_MTDRAM is not set
+# CONFIG_MTD_BLOCK2MTD is not set
+
+#
+# Disk-On-Chip Device Drivers
+#
+# CONFIG_MTD_DOC2000 is not set
+# CONFIG_MTD_DOC2001 is not set
+# CONFIG_MTD_DOC2001PLUS is not set
+CONFIG_MTD_NAND=y
+# CONFIG_MTD_NAND_VERIFY_WRITE is not set
+# CONFIG_MTD_NAND_ECC_SMC is not set
+# CONFIG_MTD_NAND_MUSEUM_IDS is not set
+CONFIG_MTD_NAND_IDS=y
+# CONFIG_MTD_NAND_DISKONCHIP is not set
+CONFIG_MTD_NAND_CAFE=y
+# CONFIG_MTD_NAND_CS553X is not set
+# CONFIG_MTD_NAND_NANDSIM is not set
+# CONFIG_MTD_NAND_PLATFORM is not set
+# CONFIG_MTD_ONENAND is not set
+
+#
+# UBI - Unsorted block images
+#
+# CONFIG_MTD_UBI is not set
+
+#
+# Parallel port support
+#
+# CONFIG_PARPORT is not set
+
+#
+# Plug and Play support
+#
+# CONFIG_PNPACPI is not set
+
+#
+# Block devices
+#
+# CONFIG_BLK_DEV_FD is not set
+# CONFIG_BLK_CPQ_DA is not set
+# CONFIG_BLK_CPQ_CISS_DA is not set
+# CONFIG_BLK_DEV_DAC960 is not set
+# CONFIG_BLK_DEV_UMEM is not set
+# CONFIG_BLK_DEV_COW_COMMON is not set
+CONFIG_BLK_DEV_LOOP=m
+CONFIG_BLK_DEV_CRYPTOLOOP=m
+CONFIG_BLK_DEV_NBD=m
+# CONFIG_BLK_DEV_SX8 is not set
+CONFIG_BLK_DEV_UB=m
+CONFIG_BLK_DEV_RAM=y
+CONFIG_BLK_DEV_RAM_COUNT=16
+CONFIG_BLK_DEV_RAM_SIZE=16384
+CONFIG_BLK_DEV_RAM_BLOCKSIZE=1024
+# CONFIG_CDROM_PKTCDVD is not set
+# CONFIG_ATA_OVER_ETH is not set
+
+#
+# Misc devices
+#
+# CONFIG_IBM_ASM is not set
+# CONFIG_PHANTOM is not set
+# CONFIG_SGI_IOC4 is not set
+# CONFIG_TIFM_CORE is not set
+# CONFIG_EEPROM_93CX6 is not set
+CONFIG_IDE=m
+CONFIG_IDE_MAX_HWIFS=4
+CONFIG_BLK_DEV_IDE=m
+
+#
+# Please see Documentation/ide.txt for help/info on IDE drives
+#
+# CONFIG_BLK_DEV_IDE_SATA is not set
+# CONFIG_BLK_DEV_HD_IDE is not set
+CONFIG_BLK_DEV_IDEDISK=m
+CONFIG_IDEDISK_MULTI_MODE=y
+# CONFIG_BLK_DEV_IDECD is not set
+# CONFIG_BLK_DEV_IDETAPE is not set
+# CONFIG_BLK_DEV_IDEFLOPPY is not set
+# CONFIG_BLK_DEV_IDESCSI is not set
+CONFIG_IDE_TASK_IOCTL=y
+# CONFIG_IDE_PROC_FS is not set
+
+#
+# IDE chipset support/bugfixes
+#
+CONFIG_IDE_GENERIC=m
+# CONFIG_BLK_DEV_CMD640 is not set
+CONFIG_BLK_DEV_IDEPCI=y
+CONFIG_IDEPCI_SHARE_IRQ=y
+# CONFIG_IDEPCI_PCIBUS_ORDER is not set
+# CONFIG_BLK_DEV_OFFBOARD is not set
+# CONFIG_BLK_DEV_GENERIC is not set
+# CONFIG_BLK_DEV_OPTI621 is not set
+# CONFIG_BLK_DEV_RZ1000 is not set
+CONFIG_BLK_DEV_IDEDMA_PCI=y
+# CONFIG_BLK_DEV_IDEDMA_FORCED is not set
+CONFIG_IDEDMA_ONLYDISK=y
+# CONFIG_BLK_DEV_AEC62XX is not set
+# CONFIG_BLK_DEV_ALI15X3 is not set
+# CONFIG_BLK_DEV_AMD74XX is not set
+# CONFIG_BLK_DEV_ATIIXP is not set
+# CONFIG_BLK_DEV_CMD64X is not set
+# CONFIG_BLK_DEV_TRIFLEX is not set
+# CONFIG_BLK_DEV_CY82C693 is not set
+# CONFIG_BLK_DEV_CS5520 is not set
+# CONFIG_BLK_DEV_CS5530 is not set
+# CONFIG_BLK_DEV_CS5535 is not set
+# CONFIG_BLK_DEV_HPT34X is not set
+# CONFIG_BLK_DEV_HPT366 is not set
+# CONFIG_BLK_DEV_JMICRON is not set
+# CONFIG_BLK_DEV_SC1200 is not set
+CONFIG_BLK_DEV_PIIX=m
+# CONFIG_BLK_DEV_IT8213 is not set
+# CONFIG_BLK_DEV_IT821X is not set
+# CONFIG_BLK_DEV_NS87415 is not set
+# CONFIG_BLK_DEV_PDC202XX_OLD is not set
+# CONFIG_BLK_DEV_PDC202XX_NEW is not set
+# CONFIG_BLK_DEV_SVWKS is not set
+# CONFIG_BLK_DEV_SIIMAGE is not set
+# CONFIG_BLK_DEV_SIS5513 is not set
+# CONFIG_BLK_DEV_SLC90E66 is not set
+# CONFIG_BLK_DEV_TRM290 is not set
+# CONFIG_BLK_DEV_VIA82CXXX is not set
+# CONFIG_BLK_DEV_TC86C001 is not set
+# CONFIG_IDE_ARM is not set
+CONFIG_BLK_DEV_IDEDMA=y
+# CONFIG_IDEDMA_IVB is not set
+# CONFIG_BLK_DEV_HD is not set
+
+#
+# SCSI device support
+#
+# CONFIG_RAID_ATTRS is not set
+CONFIG_SCSI=y
+# CONFIG_SCSI_TGT is not set
+# CONFIG_SCSI_NETLINK is not set
+CONFIG_SCSI_PROC_FS=y
+
+#
+# SCSI support type (disk, tape, CD-ROM)
+#
+CONFIG_BLK_DEV_SD=y
+# CONFIG_CHR_DEV_ST is not set
+# CONFIG_CHR_DEV_OSST is not set
+CONFIG_BLK_DEV_SR=m
+CONFIG_BLK_DEV_SR_VENDOR=y
+CONFIG_CHR_DEV_SG=m
+CONFIG_CHR_DEV_SCH=m
+
+#
+# Some SCSI devices (e.g. CD jukebox) support multiple LUNs
+#
+CONFIG_SCSI_MULTI_LUN=y
+CONFIG_SCSI_CONSTANTS=y
+CONFIG_SCSI_LOGGING=y
+# CONFIG_SCSI_SCAN_ASYNC is not set
+CONFIG_SCSI_WAIT_SCAN=m
+
+#
+# SCSI Transports
+#
+# CONFIG_SCSI_SPI_ATTRS is not set
+# CONFIG_SCSI_FC_ATTRS is not set
+# CONFIG_SCSI_ISCSI_ATTRS is not set
+# CONFIG_SCSI_SAS_ATTRS is not set
+# CONFIG_SCSI_SAS_LIBSAS is not set
+
+#
+# SCSI low-level drivers
+#
+# CONFIG_ISCSI_TCP is not set
+# CONFIG_BLK_DEV_3W_XXXX_RAID is not set
+# CONFIG_SCSI_3W_9XXX is not set
+# CONFIG_SCSI_ACARD is not set
+# CONFIG_SCSI_AACRAID is not set
+# CONFIG_SCSI_AIC7XXX is not set
+# CONFIG_SCSI_AIC7XXX_OLD is not set
+# CONFIG_SCSI_AIC79XX is not set
+# CONFIG_SCSI_AIC94XX is not set
+# CONFIG_SCSI_DPT_I2O is not set
+# CONFIG_SCSI_ADVANSYS is not set
+# CONFIG_SCSI_ARCMSR is not set
+# CONFIG_MEGARAID_NEWGEN is not set
+# CONFIG_MEGARAID_LEGACY is not set
+# CONFIG_MEGARAID_SAS is not set
+# CONFIG_SCSI_HPTIOP is not set
+# CONFIG_SCSI_BUSLOGIC is not set
+# CONFIG_SCSI_DMX3191D is not set
+# CONFIG_SCSI_EATA is not set
+# CONFIG_SCSI_FUTURE_DOMAIN is not set
+# CONFIG_SCSI_GDTH is not set
+# CONFIG_SCSI_IPS is not set
+# CONFIG_SCSI_INITIO is not set
+# CONFIG_SCSI_INIA100 is not set
+# CONFIG_SCSI_STEX is not set
+# CONFIG_SCSI_SYM53C8XX_2 is not set
+# CONFIG_SCSI_QLOGIC_1280 is not set
+# CONFIG_SCSI_QLA_FC is not set
+# CONFIG_SCSI_QLA_ISCSI is not set
+# CONFIG_SCSI_LPFC is not set
+# CONFIG_SCSI_DC395x is not set
+# CONFIG_SCSI_DC390T is not set
+# CONFIG_SCSI_NSP32 is not set
+# CONFIG_SCSI_DEBUG is not set
+# CONFIG_SCSI_SRP is not set
+# CONFIG_ATA is not set
+
+#
+# Multi-device support (RAID and LVM)
+#
+# CONFIG_MD is not set
+
+#
+# Fusion MPT device support
+#
+# CONFIG_FUSION is not set
+# CONFIG_FUSION_SPI is not set
+# CONFIG_FUSION_FC is not set
+# CONFIG_FUSION_SAS is not set
+
+#
+# IEEE 1394 (FireWire) support
+#
+# CONFIG_FIREWIRE is not set
+# CONFIG_IEEE1394 is not set
+
+#
+# I2O device support
+#
+# CONFIG_I2O is not set
+# CONFIG_MACINTOSH_DRIVERS is not set
+
+#
+# Network device support
+#
+CONFIG_NETDEVICES=y
+CONFIG_IFB=m
+CONFIG_DUMMY=m
+# CONFIG_BONDING is not set
+# CONFIG_EQUALIZER is not set
+CONFIG_TUN=m
+# CONFIG_ARCNET is not set
+# CONFIG_PHYLIB is not set
+
+#
+# Ethernet (10 or 100Mbit)
+#
+CONFIG_NET_ETHERNET=y
+CONFIG_MII=m
+# CONFIG_HAPPYMEAL is not set
+# CONFIG_SUNGEM is not set
+# CONFIG_CASSINI is not set
+# CONFIG_NET_VENDOR_3COM is not set
+
+#
+# Tulip family network device support
+#
+# CONFIG_NET_TULIP is not set
+# CONFIG_HP100 is not set
+CONFIG_NET_PCI=y
+CONFIG_PCNET32=m
+# CONFIG_PCNET32_NAPI is not set
+# CONFIG_AMD8111_ETH is not set
+# CONFIG_ADAPTEC_STARFIRE is not set
+# CONFIG_B44 is not set
+# CONFIG_FORCEDETH is not set
+# CONFIG_DGRS is not set
+# CONFIG_EEPRO100 is not set
+# CONFIG_E100 is not set
+# CONFIG_FEALNX is not set
+# CONFIG_NATSEMI is not set
+CONFIG_NE2K_PCI=m
+CONFIG_8139CP=m
+# CONFIG_8139TOO is not set
+# CONFIG_SIS900 is not set
+# CONFIG_EPIC100 is not set
+# CONFIG_SUNDANCE is not set
+# CONFIG_TLAN is not set
+# CONFIG_VIA_RHINE is not set
+# CONFIG_SC92031 is not set
+CONFIG_NETDEV_1000=y
+# CONFIG_ACENIC is not set
+# CONFIG_DL2K is not set
+# CONFIG_E1000 is not set
+# CONFIG_NS83820 is not set
+# CONFIG_HAMACHI is not set
+# CONFIG_YELLOWFIN is not set
+# CONFIG_R8169 is not set
+# CONFIG_SIS190 is not set
+# CONFIG_SKGE is not set
+# CONFIG_SKY2 is not set
+# CONFIG_SK98LIN is not set
+# CONFIG_VIA_VELOCITY is not set
+# CONFIG_TIGON3 is not set
+# CONFIG_BNX2 is not set
+# CONFIG_QLA3XXX is not set
+# CONFIG_ATL1 is not set
+CONFIG_NETDEV_10000=y
+# CONFIG_CHELSIO_T1 is not set
+# CONFIG_CHELSIO_T3 is not set
+# CONFIG_IXGB is not set
+# CONFIG_S2IO is not set
+# CONFIG_MYRI10GE is not set
+# CONFIG_NETXEN_NIC is not set
+# CONFIG_MLX4_CORE is not set
+# CONFIG_TR is not set
+
+#
+# Wireless LAN
+#
+# CONFIG_WLAN_PRE80211 is not set
+CONFIG_WLAN_80211=y
+# CONFIG_IPW2100 is not set
+# CONFIG_IPW2200 is not set
+CONFIG_LIBERTAS=m
+CONFIG_LIBERTAS_USB=m
+CONFIG_LIBERTAS_DEBUG=y
+# CONFIG_AIRO is not set
+# CONFIG_HERMES is not set
+# CONFIG_ATMEL is not set
+# CONFIG_PRISM54 is not set
+# CONFIG_USB_ZD1201 is not set
+# CONFIG_PRISM54_USB is not set
+# CONFIG_HOSTAP is not set
+# CONFIG_BCM43XX is not set
+# CONFIG_ZD1211RW is not set
+# CONFIG_ADM8211 is not set
+# CONFIG_ACX_PCI is not set
+# CONFIG_ACX_USB is not set
+
+#
+# USB Network Adapters
+#
+CONFIG_USB_CATC=m
+CONFIG_USB_KAWETH=m
+CONFIG_USB_PEGASUS=m
+CONFIG_USB_RTL8150=m
+CONFIG_USB_USBNET_MII=m
+CONFIG_USB_USBNET=m
+CONFIG_USB_NET_AX8817X=m
+CONFIG_USB_NET_CDCETHER=m
+CONFIG_USB_NET_DM9601=m
+CONFIG_USB_NET_GL620A=m
+CONFIG_USB_NET_NET1080=m
+CONFIG_USB_NET_PLUSB=m
+CONFIG_USB_NET_MCS7830=m
+CONFIG_USB_NET_RNDIS_HOST=m
+CONFIG_USB_NET_CDC_SUBSET=m
+CONFIG_USB_ALI_M5632=y
+CONFIG_USB_AN2720=y
+CONFIG_USB_BELKIN=y
+CONFIG_USB_ARMLINUX=y
+CONFIG_USB_EPSON2888=y
+# CONFIG_USB_KC2190 is not set
+CONFIG_USB_NET_ZAURUS=m
+# CONFIG_WAN is not set
+# CONFIG_FDDI is not set
+# CONFIG_HIPPI is not set
+CONFIG_PPP=m
+CONFIG_PPP_MULTILINK=y
+CONFIG_PPP_FILTER=y
+CONFIG_PPP_ASYNC=m
+CONFIG_PPP_SYNC_TTY=m
+CONFIG_PPP_DEFLATE=m
+# CONFIG_PPP_BSDCOMP is not set
+CONFIG_PPP_MPPE=m
+CONFIG_PPPOE=m
+CONFIG_SLIP=m
+CONFIG_SLIP_COMPRESSED=y
+CONFIG_SLHC=m
+CONFIG_SLIP_SMART=y
+# CONFIG_SLIP_MODE_SLIP6 is not set
+# CONFIG_NET_FC is not set
+# CONFIG_SHAPER is not set
+CONFIG_NETCONSOLE=m
+CONFIG_NETPOLL=y
+CONFIG_NETPOLL_TRAP=y
+CONFIG_NET_POLL_CONTROLLER=y
+
+#
+# ISDN subsystem
+#
+# CONFIG_ISDN is not set
+
+#
+# Telephony Support
+#
+# CONFIG_PHONE is not set
+
+#
+# Input device support
+#
+CONFIG_INPUT=y
+# CONFIG_INPUT_FF_MEMLESS is not set
+# CONFIG_INPUT_POLLDEV is not set
+
+#
+# Userland interfaces
+#
+CONFIG_INPUT_MOUSEDEV=m
+# CONFIG_INPUT_MOUSEDEV_PSAUX is not set
+CONFIG_INPUT_MOUSEDEV_SCREEN_X=1024
+CONFIG_INPUT_MOUSEDEV_SCREEN_Y=768
+CONFIG_INPUT_JOYDEV=m
+# CONFIG_INPUT_TSDEV is not set
+CONFIG_INPUT_EVDEV=y
+# CONFIG_INPUT_EVBUG is not set
+
+#
+# Input Device Drivers
+#
+CONFIG_INPUT_KEYBOARD=y
+CONFIG_KEYBOARD_ATKBD=y
+# CONFIG_KEYBOARD_SUNKBD is not set
+# CONFIG_KEYBOARD_LKKBD is not set
+# CONFIG_KEYBOARD_XTKBD is not set
+# CONFIG_KEYBOARD_NEWTON is not set
+# CONFIG_KEYBOARD_STOWAWAY is not set
+CONFIG_INPUT_MOUSE=y
+CONFIG_MOUSE_PS2=m
+# CONFIG_MOUSE_PS2_ALPS is not set
+# CONFIG_MOUSE_PS2_LOGIPS2PP is not set
+# CONFIG_MOUSE_PS2_SYNAPTICS is not set
+# CONFIG_MOUSE_PS2_LIFEBOOK is not set
+# CONFIG_MOUSE_PS2_TRACKPOINT is not set
+# CONFIG_MOUSE_PS2_TOUCHKIT is not set
+CONFIG_MOUSE_PS2_OLPC=y
+# CONFIG_MOUSE_SERIAL is not set
+# CONFIG_MOUSE_APPLETOUCH is not set
+# CONFIG_MOUSE_VSXXXAA is not set
+# CONFIG_INPUT_JOYSTICK is not set
+# CONFIG_INPUT_TABLET is not set
+# CONFIG_INPUT_TOUCHSCREEN is not set
+CONFIG_INPUT_MISC=y
+CONFIG_INPUT_PCSPKR=m
+# CONFIG_INPUT_WISTRON_BTNS is not set
+# CONFIG_INPUT_ATI_REMOTE is not set
+# CONFIG_INPUT_ATI_REMOTE2 is not set
+# CONFIG_INPUT_KEYSPAN_REMOTE is not set
+# CONFIG_INPUT_POWERMATE is not set
+# CONFIG_INPUT_YEALINK is not set
+CONFIG_INPUT_UINPUT=m
+
+#
+# Hardware I/O ports
+#
+CONFIG_SERIO=y
+CONFIG_SERIO_I8042=y
+CONFIG_SERIO_SERPORT=y
+# CONFIG_SERIO_CT82C710 is not set
+# CONFIG_SERIO_PCIPS2 is not set
+CONFIG_SERIO_LIBPS2=y
+CONFIG_SERIO_RAW=m
+# CONFIG_GAMEPORT is not set
+
+#
+# Character devices
+#
+CONFIG_VT=y
+CONFIG_VT_CONSOLE=y
+CONFIG_HW_CONSOLE=y
+# CONFIG_VT_HW_CONSOLE_BINDING is not set
+# CONFIG_SERIAL_NONSTANDARD is not set
+
+#
+# Serial drivers
+#
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_PCI=y
+CONFIG_SERIAL_8250_NR_UARTS=1
+CONFIG_SERIAL_8250_RUNTIME_UARTS=1
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_SHARE_IRQ=y
+CONFIG_SERIAL_8250_DETECT_IRQ=y
+CONFIG_SERIAL_8250_RSA=y
+
+#
+# Non-8250 serial port support
+#
+CONFIG_SERIAL_CORE=y
+CONFIG_SERIAL_CORE_CONSOLE=y
+# CONFIG_SERIAL_JSM is not set
+CONFIG_UNIX98_PTYS=y
+# CONFIG_LEGACY_PTYS is not set
+
+#
+# IPMI
+#
+# CONFIG_IPMI_HANDLER is not set
+CONFIG_WATCHDOG=y
+# CONFIG_WATCHDOG_NOWAYOUT is not set
+
+#
+# Watchdog Device Drivers
+#
+CONFIG_SOFT_WATCHDOG=m
+# CONFIG_ACQUIRE_WDT is not set
+# CONFIG_ADVANTECH_WDT is not set
+# CONFIG_ALIM1535_WDT is not set
+# CONFIG_ALIM7101_WDT is not set
+# CONFIG_SC520_WDT is not set
+# CONFIG_EUROTECH_WDT is not set
+# CONFIG_IB700_WDT is not set
+# CONFIG_IBMASR is not set
+# CONFIG_WAFER_WDT is not set
+# CONFIG_I6300ESB_WDT is not set
+# CONFIG_ITCO_WDT is not set
+# CONFIG_SC1200_WDT is not set
+# CONFIG_PC87413_WDT is not set
+# CONFIG_60XX_WDT is not set
+# CONFIG_SBC8360_WDT is not set
+# CONFIG_CPU5_WDT is not set
+# CONFIG_SMSC37B787_WDT is not set
+# CONFIG_W83627HF_WDT is not set
+# CONFIG_W83697HF_WDT is not set
+# CONFIG_W83877F_WDT is not set
+# CONFIG_W83977F_WDT is not set
+# CONFIG_MACHZ_WDT is not set
+# CONFIG_SBC_EPX_C3_WATCHDOG is not set
+
+#
+# PCI-based Watchdog Cards
+#
+# CONFIG_PCIPCWATCHDOG is not set
+# CONFIG_WDTPCI is not set
+
+#
+# USB-based Watchdog Cards
+#
+# CONFIG_USBPCWATCHDOG is not set
+CONFIG_HW_RANDOM=y
+# CONFIG_HW_RANDOM_INTEL is not set
+# CONFIG_HW_RANDOM_AMD is not set
+CONFIG_HW_RANDOM_GEODE=y
+# CONFIG_HW_RANDOM_VIA is not set
+CONFIG_NVRAM=y
+# CONFIG_RTC is not set
+# CONFIG_GEN_RTC is not set
+# CONFIG_R3964 is not set
+# CONFIG_APPLICOM is not set
+# CONFIG_SONYPI is not set
+# CONFIG_AGP is not set
+# CONFIG_DRM is not set
+# CONFIG_MWAVE is not set
+# CONFIG_PC8736x_GPIO is not set
+# CONFIG_NSC_GPIO is not set
+CONFIG_CS5535_GPIO=m
+# CONFIG_RAW_DRIVER is not set
+CONFIG_HANGCHECK_TIMER=m
+
+#
+# TPM devices
+#
+# CONFIG_TCG_TPM is not set
+# CONFIG_TELCLOCK is not set
+CONFIG_DEVPORT=y
+CONFIG_I2C=y
+CONFIG_I2C_BOARDINFO=y
+CONFIG_I2C_CHARDEV=m
+
+#
+# I2C Algorithms
+#
+# CONFIG_I2C_ALGOBIT is not set
+# CONFIG_I2C_ALGOPCF is not set
+# CONFIG_I2C_ALGOPCA is not set
+
+#
+# I2C Hardware Bus support
+#
+# CONFIG_I2C_ALI1535 is not set
+# CONFIG_I2C_ALI1563 is not set
+# CONFIG_I2C_ALI15X3 is not set
+# CONFIG_I2C_AMD756 is not set
+# CONFIG_I2C_AMD8111 is not set
+# CONFIG_I2C_I801 is not set
+# CONFIG_I2C_I810 is not set
+# CONFIG_I2C_PIIX4 is not set
+# CONFIG_I2C_NFORCE2 is not set
+# CONFIG_I2C_OCORES is not set
+# CONFIG_I2C_PARPORT_LIGHT is not set
+# CONFIG_I2C_PROSAVAGE is not set
+# CONFIG_I2C_SAVAGE4 is not set
+# CONFIG_I2C_SIMTEC is not set
+CONFIG_SCx200_ACB=y
+# CONFIG_I2C_SIS5595 is not set
+# CONFIG_I2C_SIS630 is not set
+# CONFIG_I2C_SIS96X is not set
+# CONFIG_I2C_STUB is not set
+# CONFIG_I2C_TINY_USB is not set
+# CONFIG_I2C_VIA is not set
+# CONFIG_I2C_VIAPRO is not set
+# CONFIG_I2C_VOODOO3 is not set
+
+#
+# Miscellaneous I2C Chip support
+#
+# CONFIG_SENSORS_DS1337 is not set
+# CONFIG_SENSORS_DS1374 is not set
+# CONFIG_SENSORS_EEPROM is not set
+# CONFIG_SENSORS_PCF8574 is not set
+# CONFIG_SENSORS_PCA9539 is not set
+# CONFIG_SENSORS_PCF8591 is not set
+# CONFIG_SENSORS_MAX6875 is not set
+# CONFIG_I2C_DEBUG_CORE is not set
+# CONFIG_I2C_DEBUG_ALGO is not set
+# CONFIG_I2C_DEBUG_BUS is not set
+# CONFIG_I2C_DEBUG_CHIP is not set
+
+#
+# SPI support
+#
+# CONFIG_SPI is not set
+# CONFIG_SPI_MASTER is not set
+
+#
+# Dallas's 1-wire bus
+#
+# CONFIG_W1 is not set
+CONFIG_POWER_SUPPLY=y
+# CONFIG_POWER_SUPPLY_DEBUG is not set
+# CONFIG_PDA_POWER is not set
+# CONFIG_BATTERY_DS2760 is not set
+CONFIG_BATTERY_OLPC=y
+# CONFIG_HWMON is not set
+
+#
+# Multifunction device drivers
+#
+# CONFIG_MFD_SM501 is not set
+
+#
+# Multimedia devices
+#
+CONFIG_VIDEO_DEV=y
+# CONFIG_VIDEO_V4L1 is not set
+CONFIG_VIDEO_V4L1_COMPAT=y
+CONFIG_VIDEO_V4L2=y
+CONFIG_VIDEO_CAPTURE_DRIVERS=y
+# CONFIG_VIDEO_ADV_DEBUG is not set
+# CONFIG_VIDEO_HELPER_CHIPS_AUTO is not set
+
+#
+# Encoders/decoders and other helper chips
+#
+
+#
+# Audio decoders
+#
+# CONFIG_VIDEO_TDA9840 is not set
+# CONFIG_VIDEO_TEA6415C is not set
+# CONFIG_VIDEO_TEA6420 is not set
+# CONFIG_VIDEO_MSP3400 is not set
+# CONFIG_VIDEO_CS53L32A is not set
+# CONFIG_VIDEO_TLV320AIC23B is not set
+# CONFIG_VIDEO_WM8775 is not set
+# CONFIG_VIDEO_WM8739 is not set
+
+#
+# Video decoders
+#
+CONFIG_VIDEO_OV7670=y
+# CONFIG_VIDEO_SAA711X is not set
+# CONFIG_VIDEO_TVP5150 is not set
+
+#
+# Video and audio decoders
+#
+# CONFIG_VIDEO_CX25840 is not set
+
+#
+# MPEG video encoders
+#
+# CONFIG_VIDEO_CX2341X is not set
+
+#
+# Video encoders
+#
+# CONFIG_VIDEO_SAA7127 is not set
+
+#
+# Video improvement chips
+#
+# CONFIG_VIDEO_UPD64031A is not set
+# CONFIG_VIDEO_UPD64083 is not set
+# CONFIG_VIDEO_VIVI is not set
+# CONFIG_VIDEO_SAA5246A is not set
+# CONFIG_VIDEO_SAA5249 is not set
+# CONFIG_VIDEO_SAA7134 is not set
+# CONFIG_VIDEO_HEXIUM_ORION is not set
+# CONFIG_VIDEO_HEXIUM_GEMINI is not set
+# CONFIG_VIDEO_CX88 is not set
+CONFIG_VIDEO_CAFE_CCIC=y
+CONFIG_V4L_USB_DRIVERS=y
+# CONFIG_VIDEO_PVRUSB2 is not set
+# CONFIG_VIDEO_USBVISION is not set
+# CONFIG_USB_SN9C102 is not set
+# CONFIG_USB_ZR364XX is not set
+CONFIG_RADIO_ADAPTERS=y
+# CONFIG_RADIO_GEMTEK_PCI is not set
+# CONFIG_RADIO_MAXIRADIO is not set
+# CONFIG_RADIO_MAESTRO is not set
+# CONFIG_USB_DSBR is not set
+# CONFIG_DVB_CORE is not set
+CONFIG_DAB=y
+# CONFIG_USB_DABUSB is not set
+
+#
+# Graphics support
+#
+CONFIG_BACKLIGHT_LCD_SUPPORT=y
+CONFIG_BACKLIGHT_CLASS_DEVICE=y
+CONFIG_LCD_CLASS_DEVICE=y
+# CONFIG_BACKLIGHT_PROGEAR is not set
+
+#
+# Display device support
+#
+# CONFIG_DISPLAY_SUPPORT is not set
+CONFIG_VGASTATE=m
+CONFIG_FB=y
+# CONFIG_FIRMWARE_EDID is not set
+# CONFIG_FB_DDC is not set
+CONFIG_FB_CFB_FILLRECT=y
+CONFIG_FB_CFB_COPYAREA=y
+CONFIG_FB_CFB_IMAGEBLIT=y
+# CONFIG_FB_SYS_FILLRECT is not set
+# CONFIG_FB_SYS_COPYAREA is not set
+# CONFIG_FB_SYS_IMAGEBLIT is not set
+# CONFIG_FB_SYS_FOPS is not set
+CONFIG_FB_DEFERRED_IO=y
+# CONFIG_FB_SVGALIB is not set
+# CONFIG_FB_MACMODES is not set
+# CONFIG_FB_BACKLIGHT is not set
+CONFIG_FB_MODE_HELPERS=y
+CONFIG_FB_TILEBLITTING=y
+
+#
+# Frame buffer hardware drivers
+#
+# CONFIG_FB_CIRRUS is not set
+# CONFIG_FB_PM2 is not set
+# CONFIG_FB_CYBER2000 is not set
+# CONFIG_FB_ARC is not set
+# CONFIG_FB_ASILIANT is not set
+# CONFIG_FB_IMSTT is not set
+CONFIG_FB_VGA16=m
+CONFIG_FB_VESA=y
+# CONFIG_FB_HECUBA is not set
+# CONFIG_FB_HGA is not set
+# CONFIG_FB_S1D13XXX is not set
+# CONFIG_FB_NVIDIA is not set
+# CONFIG_FB_RIVA is not set
+# CONFIG_FB_I810 is not set
+# CONFIG_FB_LE80578 is not set
+# CONFIG_FB_INTEL is not set
+# CONFIG_FB_MATROX is not set
+# CONFIG_FB_RADEON is not set
+# CONFIG_FB_ATY128 is not set
+# CONFIG_FB_ATY is not set
+# CONFIG_FB_S3 is not set
+# CONFIG_FB_SAVAGE is not set
+# CONFIG_FB_SIS is not set
+# CONFIG_FB_NEOMAGIC is not set
+# CONFIG_FB_KYRO is not set
+# CONFIG_FB_3DFX is not set
+# CONFIG_FB_VOODOO1 is not set
+# CONFIG_FB_VT8623 is not set
+# CONFIG_FB_CYBLA is not set
+# CONFIG_FB_TRIDENT is not set
+# CONFIG_FB_ARK is not set
+# CONFIG_FB_PM3 is not set
+CONFIG_FB_GEODE=y
+CONFIG_FB_GEODE_LX=y
+CONFIG_FB_GEODE_GX=y
+# CONFIG_FB_GEODE_GX1 is not set
+CONFIG_FB_OLPC_DCON=y
+# CONFIG_FB_VIRTUAL is not set
+
+#
+# Console display driver support
+#
+CONFIG_VGA_CONSOLE=y
+CONFIG_VGACON_SOFT_SCROLLBACK=y
+CONFIG_VGACON_SOFT_SCROLLBACK_SIZE=64
+CONFIG_VIDEO_SELECT=y
+CONFIG_DUMMY_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE=y
+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
+CONFIG_FONTS=y
+# CONFIG_FONT_8x8 is not set
+CONFIG_FONT_8x16=y
+# CONFIG_FONT_6x11 is not set
+# CONFIG_FONT_7x14 is not set
+# CONFIG_FONT_PEARL_8x8 is not set
+# CONFIG_FONT_ACORN_8x8 is not set
+# CONFIG_FONT_MINI_4x6 is not set
+# CONFIG_FONT_SUN8x16 is not set
+CONFIG_FONT_SUN12x22=y
+# CONFIG_FONT_10x18 is not set
+CONFIG_LOGO=y
+# CONFIG_LOGO_LINUX_MONO is not set
+# CONFIG_LOGO_LINUX_VGA16 is not set
+CONFIG_LOGO_LINUX_CLUT224=y
+
+#
+# Sound
+#
+CONFIG_SOUND=y
+
+#
+# Advanced Linux Sound Architecture
+#
+CONFIG_SND=y
+CONFIG_SND_TIMER=y
+CONFIG_SND_PCM=y
+CONFIG_SND_HWDEP=m
+CONFIG_SND_RAWMIDI=m
+CONFIG_SND_SEQUENCER=m
+CONFIG_SND_SEQ_DUMMY=m
+CONFIG_SND_OSSEMUL=y
+CONFIG_SND_MIXER_OSS=m
+CONFIG_SND_PCM_OSS=m
+CONFIG_SND_PCM_OSS_PLUGINS=y
+CONFIG_SND_SEQUENCER_OSS=y
+CONFIG_SND_DYNAMIC_MINORS=y
+# CONFIG_SND_SUPPORT_OLD_API is not set
+CONFIG_SND_VERBOSE_PROCFS=y
+# CONFIG_SND_VERBOSE_PRINTK is not set
+# CONFIG_SND_DEBUG is not set
+
+#
+# Generic devices
+#
+CONFIG_SND_MPU401_UART=m
+CONFIG_SND_AC97_CODEC=y
+CONFIG_SND_DUMMY=m
+CONFIG_SND_VIRMIDI=m
+CONFIG_SND_MTPAV=m
+# CONFIG_SND_SERIAL_U16550 is not set
+CONFIG_SND_MPU401=m
+
+#
+# PCI devices
+#
+# CONFIG_SND_AD1889 is not set
+# CONFIG_SND_ALS300 is not set
+# CONFIG_SND_ALS4000 is not set
+# CONFIG_SND_ALI5451 is not set
+# CONFIG_SND_ATIIXP is not set
+# CONFIG_SND_ATIIXP_MODEM is not set
+# CONFIG_SND_AU8810 is not set
+# CONFIG_SND_AU8820 is not set
+# CONFIG_SND_AU8830 is not set
+# CONFIG_SND_AZT3328 is not set
+# CONFIG_SND_BT87X is not set
+# CONFIG_SND_CA0106 is not set
+# CONFIG_SND_CMIPCI is not set
+# CONFIG_SND_CS4281 is not set
+# CONFIG_SND_CS46XX is not set
+CONFIG_SND_CS5535AUDIO=y
+# CONFIG_SND_DARLA20 is not set
+# CONFIG_SND_GINA20 is not set
+# CONFIG_SND_LAYLA20 is not set
+# CONFIG_SND_DARLA24 is not set
+# CONFIG_SND_GINA24 is not set
+# CONFIG_SND_LAYLA24 is not set
+# CONFIG_SND_MONA is not set
+# CONFIG_SND_MIA is not set
+# CONFIG_SND_ECHO3G is not set
+# CONFIG_SND_INDIGO is not set
+# CONFIG_SND_INDIGOIO is not set
+# CONFIG_SND_INDIGODJ is not set
+# CONFIG_SND_EMU10K1 is not set
+# CONFIG_SND_EMU10K1X is not set
+CONFIG_SND_ENS1370=m
+CONFIG_SND_ENS1371=m
+# CONFIG_SND_ES1938 is not set
+# CONFIG_SND_ES1968 is not set
+# CONFIG_SND_FM801 is not set
+# CONFIG_SND_HDA_INTEL is not set
+# CONFIG_SND_HDSP is not set
+# CONFIG_SND_HDSPM is not set
+# CONFIG_SND_ICE1712 is not set
+# CONFIG_SND_ICE1724 is not set
+CONFIG_SND_INTEL8X0=m
+# CONFIG_SND_INTEL8X0M is not set
+# CONFIG_SND_KORG1212 is not set
+# CONFIG_SND_MAESTRO3 is not set
+# CONFIG_SND_MIXART is not set
+# CONFIG_SND_NM256 is not set
+# CONFIG_SND_PCXHR is not set
+# CONFIG_SND_RIPTIDE is not set
+# CONFIG_SND_RME32 is not set
+# CONFIG_SND_RME96 is not set
+# CONFIG_SND_RME9652 is not set
+# CONFIG_SND_SONICVIBES is not set
+# CONFIG_SND_TRIDENT is not set
+# CONFIG_SND_VIA82XX is not set
+# CONFIG_SND_VIA82XX_MODEM is not set
+# CONFIG_SND_VX222 is not set
+# CONFIG_SND_YMFPCI is not set
+CONFIG_SND_AC97_POWER_SAVE=y
+
+#
+# USB devices
+#
+CONFIG_SND_USB_AUDIO=m
+CONFIG_SND_USB_USX2Y=m
+# CONFIG_SND_USB_CAIAQ is not set
+
+#
+# System on Chip audio support
+#
+# CONFIG_SND_SOC is not set
+
+#
+# Open Sound System
+#
+# CONFIG_SOUND_PRIME is not set
+CONFIG_AC97_BUS=y
+
+#
+# HID Devices
+#
+CONFIG_HID=y
+# CONFIG_HID_DEBUG is not set
+
+#
+# USB Input Devices
+#
+CONFIG_USB_HID=y
+# CONFIG_USB_HIDINPUT_POWERBOOK is not set
+# CONFIG_HID_FF is not set
+CONFIG_USB_HIDDEV=y
+
+#
+# USB support
+#
+CONFIG_USB_ARCH_HAS_HCD=y
+CONFIG_USB_ARCH_HAS_OHCI=y
+CONFIG_USB_ARCH_HAS_EHCI=y
+CONFIG_USB=y
+# CONFIG_USB_DEBUG is not set
+
+#
+# Miscellaneous USB options
+#
+CONFIG_USB_DEVICEFS=y
+# CONFIG_USB_DEVICE_CLASS is not set
+# CONFIG_USB_DYNAMIC_MINORS is not set
+# CONFIG_USB_SUSPEND is not set
+CONFIG_USB_PERSIST=y
+# CONFIG_USB_OTG is not set
+
+#
+# USB Host Controller Drivers
+#
+CONFIG_USB_EHCI_HCD=y
+CONFIG_USB_EHCI_SPLIT_ISO=y
+CONFIG_USB_EHCI_ROOT_HUB_TT=y
+# CONFIG_USB_EHCI_TT_NEWSCHED is not set
+# CONFIG_USB_EHCI_BIG_ENDIAN_MMIO is not set
+# CONFIG_USB_ISP116X_HCD is not set
+CONFIG_USB_OHCI_HCD=y
+# CONFIG_USB_OHCI_BIG_ENDIAN_DESC is not set
+# CONFIG_USB_OHCI_BIG_ENDIAN_MMIO is not set
+CONFIG_USB_OHCI_LITTLE_ENDIAN=y
+# CONFIG_USB_UHCI_HCD is not set
+# CONFIG_USB_SL811_HCD is not set
+
+#
+# USB Device Class drivers
+#
+CONFIG_USB_ACM=m
+CONFIG_USB_PRINTER=m
+
+#
+# NOTE: USB_STORAGE enables SCSI, and 'SCSI disk support'
+#
+
+#
+# may also be needed; see USB_STORAGE Help for more information
+#
+CONFIG_USB_STORAGE=y
+# CONFIG_USB_STORAGE_DEBUG is not set
+CONFIG_USB_STORAGE_DATAFAB=y
+CONFIG_USB_STORAGE_FREECOM=y
+CONFIG_USB_STORAGE_DPCM=y
+CONFIG_USB_STORAGE_USBAT=y
+CONFIG_USB_STORAGE_SDDR09=y
+CONFIG_USB_STORAGE_SDDR55=y
+CONFIG_USB_STORAGE_JUMPSHOT=y
+CONFIG_USB_STORAGE_ALAUDA=y
+# CONFIG_USB_STORAGE_KARMA is not set
+CONFIG_USB_LIBUSUAL=y
+
+#
+# USB Imaging devices
+#
+# CONFIG_USB_MDC800 is not set
+# CONFIG_USB_MICROTEK is not set
+CONFIG_USB_MON=y
+
+#
+# USB port drivers
+#
+
+#
+# USB Serial Converter support
+#
+CONFIG_USB_SERIAL=m
+CONFIG_USB_SERIAL_GENERIC=y
+# CONFIG_USB_SERIAL_AIRCABLE is not set
+# CONFIG_USB_SERIAL_AIRPRIME is not set
+# CONFIG_USB_SERIAL_ARK3116 is not set
+# CONFIG_USB_SERIAL_BELKIN is not set
+# CONFIG_USB_SERIAL_WHITEHEAT is not set
+# CONFIG_USB_SERIAL_DIGI_ACCELEPORT is not set
+CONFIG_USB_SERIAL_CP2101=m
+# CONFIG_USB_SERIAL_CYPRESS_M8 is not set
+# CONFIG_USB_SERIAL_EMPEG is not set
+CONFIG_USB_SERIAL_FTDI_SIO=m
+# CONFIG_USB_SERIAL_FUNSOFT is not set
+# CONFIG_USB_SERIAL_VISOR is not set
+# CONFIG_USB_SERIAL_IPAQ is not set
+# CONFIG_USB_SERIAL_IR is not set
+# CONFIG_USB_SERIAL_EDGEPORT is not set
+# CONFIG_USB_SERIAL_EDGEPORT_TI is not set
+# CONFIG_USB_SERIAL_GARMIN is not set
+# CONFIG_USB_SERIAL_IPW is not set
+# CONFIG_USB_SERIAL_KEYSPAN_PDA is not set
+# CONFIG_USB_SERIAL_KEYSPAN is not set
+# CONFIG_USB_SERIAL_KLSI is not set
+# CONFIG_USB_SERIAL_KOBIL_SCT is not set
+# CONFIG_USB_SERIAL_MCT_U232 is not set
+# CONFIG_USB_SERIAL_MOS7720 is not set
+# CONFIG_USB_SERIAL_MOS7840 is not set
+# CONFIG_USB_SERIAL_NAVMAN is not set
+CONFIG_USB_SERIAL_PL2303=m
+# CONFIG_USB_SERIAL_HP4X is not set
+# CONFIG_USB_SERIAL_SAFE is not set
+# CONFIG_USB_SERIAL_SIERRAWIRELESS is not set
+# CONFIG_USB_SERIAL_TI is not set
+# CONFIG_USB_SERIAL_CYBERJACK is not set
+# CONFIG_USB_SERIAL_XIRCOM is not set
+# CONFIG_USB_SERIAL_OPTION is not set
+# CONFIG_USB_SERIAL_OMNINET is not set
+# CONFIG_USB_SERIAL_DEBUG is not set
+
+#
+# USB Miscellaneous drivers
+#
+# CONFIG_USB_EMI62 is not set
+# CONFIG_USB_EMI26 is not set
+# CONFIG_USB_ADUTUX is not set
+# CONFIG_USB_AUERSWALD is not set
+# CONFIG_USB_RIO500 is not set
+# CONFIG_USB_LEGOTOWER is not set
+# CONFIG_USB_LCD is not set
+# CONFIG_USB_BERRY_CHARGE is not set
+# CONFIG_USB_LED is not set
+# CONFIG_USB_CYPRESS_CY7C63 is not set
+# CONFIG_USB_CYTHERM is not set
+# CONFIG_USB_PHIDGET is not set
+# CONFIG_USB_IDMOUSE is not set
+# CONFIG_USB_FTDI_ELAN is not set
+# CONFIG_USB_APPLEDISPLAY is not set
+# CONFIG_USB_SISUSBVGA is not set
+# CONFIG_USB_LD is not set
+# CONFIG_USB_TRANCEVIBRATOR is not set
+# CONFIG_USB_IOWARRIOR is not set
+# CONFIG_USB_TEST is not set
+
+#
+# USB DSL modem support
+#
+
+#
+# USB Gadget Support
+#
+# CONFIG_USB_GADGET is not set
+CONFIG_MMC=y
+# CONFIG_MMC_DEBUG is not set
+# CONFIG_MMC_UNSAFE_RESUME is not set
+
+#
+# MMC/SD Card Drivers
+#
+CONFIG_MMC_BLOCK=y
+
+#
+# MMC/SD Host Controller Drivers
+#
+CONFIG_MMC_SDHCI=y
+# CONFIG_MMC_WBSD is not set
+# CONFIG_MMC_TIFM_SD is not set
+
+#
+# LED devices
+#
+CONFIG_NEW_LEDS=y
+CONFIG_LEDS_CLASS=y
+
+#
+# LED drivers
+#
+
+#
+# LED Triggers
+#
+CONFIG_LEDS_TRIGGERS=y
+CONFIG_LEDS_TRIGGER_TIMER=y
+# CONFIG_LEDS_TRIGGER_IDE_DISK is not set
+CONFIG_LEDS_TRIGGER_HEARTBEAT=y
+
+#
+# InfiniBand support
+#
+# CONFIG_INFINIBAND is not set
+
+#
+# EDAC - error detection and reporting (RAS) (EXPERIMENTAL)
+#
+# CONFIG_EDAC is not set
+
+#
+# Real Time Clock
+#
+CONFIG_RTC_LIB=y
+CONFIG_RTC_CLASS=y
+# CONFIG_RTC_HCTOSYS is not set
+# CONFIG_RTC_DEBUG is not set
+
+#
+# RTC interfaces
+#
+CONFIG_RTC_INTF_SYSFS=y
+CONFIG_RTC_INTF_PROC=y
+CONFIG_RTC_INTF_DEV=y
+# CONFIG_RTC_INTF_DEV_UIE_EMUL is not set
+# CONFIG_RTC_DRV_TEST is not set
+
+#
+# I2C RTC drivers
+#
+# CONFIG_RTC_DRV_DS1307 is not set
+# CONFIG_RTC_DRV_DS1672 is not set
+# CONFIG_RTC_DRV_MAX6900 is not set
+# CONFIG_RTC_DRV_RS5C372 is not set
+# CONFIG_RTC_DRV_ISL1208 is not set
+# CONFIG_RTC_DRV_X1205 is not set
+# CONFIG_RTC_DRV_PCF8563 is not set
+# CONFIG_RTC_DRV_PCF8583 is not set
+
+#
+# SPI RTC drivers
+#
+
+#
+# Platform RTC drivers
+#
+CONFIG_RTC_DRV_CMOS=y
+# CONFIG_RTC_DRV_DS1553 is not set
+# CONFIG_RTC_DRV_DS1742 is not set
+# CONFIG_RTC_DRV_M48T86 is not set
+# CONFIG_RTC_DRV_V3020 is not set
+
+#
+# on-CPU RTC drivers
+#
+
+#
+# DMA Engine support
+#
+# CONFIG_DMA_ENGINE is not set
+
+#
+# DMA Clients
+#
+
+#
+# DMA Devices
+#
+
+#
+# Virtualization
+#
+# CONFIG_KVM is not set
+
+#
+# Sysprof
+#
+CONFIG_SYSPROF=m
+
+#
+# File systems
+#
+CONFIG_EXT2_FS=y
+CONFIG_EXT2_FS_XATTR=y
+# CONFIG_EXT2_FS_POSIX_ACL is not set
+CONFIG_EXT2_FS_SECURITY=y
+CONFIG_EXT2_FS_XIP=y
+CONFIG_FS_XIP=y
+CONFIG_EXT3_FS=y
+CONFIG_EXT3_FS_XATTR=y
+# CONFIG_EXT3_FS_POSIX_ACL is not set
+CONFIG_EXT3_FS_SECURITY=y
+# CONFIG_EXT4DEV_FS is not set
+CONFIG_JBD=y
+# CONFIG_JBD_DEBUG is not set
+CONFIG_FS_MBCACHE=y
+# CONFIG_REISERFS_FS is not set
+# CONFIG_JFS_FS is not set
+# CONFIG_FS_POSIX_ACL is not set
+# CONFIG_XFS_FS is not set
+# CONFIG_GFS2_FS is not set
+# CONFIG_OCFS2_FS is not set
+# CONFIG_MINIX_FS is not set
+# CONFIG_ROMFS_FS is not set
+CONFIG_INOTIFY=y
+CONFIG_INOTIFY_USER=y
+CONFIG_QUOTA=y
+# CONFIG_QFMT_V1 is not set
+CONFIG_QFMT_V2=y
+CONFIG_QUOTACTL=y
+CONFIG_DNOTIFY=y
+CONFIG_AUTOFS_FS=m
+CONFIG_AUTOFS4_FS=m
+# CONFIG_FUSE_FS is not set
+
+#
+# CD-ROM/DVD Filesystems
+#
+CONFIG_ISO9660_FS=m
+CONFIG_JOLIET=y
+CONFIG_ZISOFS=y
+CONFIG_UDF_FS=m
+CONFIG_UDF_NLS=y
+
+#
+# DOS/FAT/NT Filesystems
+#
+CONFIG_FAT_FS=m
+CONFIG_MSDOS_FS=m
+CONFIG_VFAT_FS=m
+CONFIG_FAT_DEFAULT_CODEPAGE=437
+CONFIG_FAT_DEFAULT_IOCHARSET="ascii"
+# CONFIG_NTFS_FS is not set
+
+#
+# Pseudo filesystems
+#
+CONFIG_PROC_FS=y
+CONFIG_PROC_KCORE=y
+CONFIG_PROC_SYSCTL=y
+CONFIG_SYSFS=y
+CONFIG_TMPFS=y
+# CONFIG_TMPFS_POSIX_ACL is not set
+CONFIG_HUGETLBFS=y
+CONFIG_HUGETLB_PAGE=y
+CONFIG_PROMFS_FS=y
+CONFIG_RAMFS=y
+# CONFIG_CONFIGFS_FS is not set
+
+#
+# Miscellaneous filesystems
+#
+# CONFIG_ADFS_FS is not set
+# CONFIG_AFFS_FS is not set
+# CONFIG_ECRYPT_FS is not set
+# CONFIG_HFS_FS is not set
+# CONFIG_HFSPLUS_FS is not set
+# CONFIG_BEFS_FS is not set
+# CONFIG_BFS_FS is not set
+# CONFIG_EFS_FS is not set
+CONFIG_JFFS2_FS=y
+CONFIG_JFFS2_FS_DEBUG=0
+CONFIG_JFFS2_FS_WRITEBUFFER=y
+CONFIG_JFFS2_FS_WBUF_VERIFY=y
+CONFIG_JFFS2_SUMMARY=y
+CONFIG_JFFS2_FS_XATTR=y
+# CONFIG_JFFS2_FS_POSIX_ACL is not set
+CONFIG_JFFS2_FS_SECURITY=y
+# CONFIG_JFFS2_COMPRESSION_OPTIONS is not set
+CONFIG_JFFS2_ZLIB=y
+CONFIG_JFFS2_RTIME=y
+# CONFIG_JFFS2_RUBIN is not set
+CONFIG_CRAMFS=m
+# CONFIG_VXFS_FS is not set
+# CONFIG_HPFS_FS is not set
+# CONFIG_QNX4FS_FS is not set
+# CONFIG_SYSV_FS is not set
+# CONFIG_UFS_FS is not set
+
+#
+# Network File Systems
+#
+CONFIG_NFS_FS=m
+CONFIG_NFS_V3=y
+# CONFIG_NFS_V3_ACL is not set
+CONFIG_NFS_V4=y
+CONFIG_NFS_DIRECTIO=y
+# CONFIG_NFSD is not set
+CONFIG_LOCKD=m
+CONFIG_LOCKD_V4=y
+CONFIG_NFS_COMMON=y
+CONFIG_SUNRPC=m
+CONFIG_SUNRPC_GSS=m
+# CONFIG_SUNRPC_BIND34 is not set
+CONFIG_RPCSEC_GSS_KRB5=m
+CONFIG_RPCSEC_GSS_SPKM3=m
+# CONFIG_SMB_FS is not set
+# CONFIG_CIFS is not set
+# CONFIG_NCP_FS is not set
+# CONFIG_CODA_FS is not set
+# CONFIG_AFS_FS is not set
+# CONFIG_9P_FS is not set
+
+#
+# Partition Types
+#
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_ACORN_PARTITION is not set
+# CONFIG_OSF_PARTITION is not set
+# CONFIG_AMIGA_PARTITION is not set
+# CONFIG_ATARI_PARTITION is not set
+# CONFIG_MAC_PARTITION is not set
+CONFIG_MSDOS_PARTITION=y
+# CONFIG_BSD_DISKLABEL is not set
+# CONFIG_MINIX_SUBPARTITION is not set
+# CONFIG_SOLARIS_X86_PARTITION is not set
+# CONFIG_UNIXWARE_DISKLABEL is not set
+# CONFIG_LDM_PARTITION is not set
+# CONFIG_SGI_PARTITION is not set
+# CONFIG_ULTRIX_PARTITION is not set
+# CONFIG_SUN_PARTITION is not set
+# CONFIG_KARMA_PARTITION is not set
+# CONFIG_EFI_PARTITION is not set
+# CONFIG_SYSV68_PARTITION is not set
+
+#
+# Native Language Support
+#
+CONFIG_NLS=y
+CONFIG_NLS_DEFAULT="utf8"
+CONFIG_NLS_CODEPAGE_437=y
+CONFIG_NLS_CODEPAGE_737=m
+CONFIG_NLS_CODEPAGE_775=m
+CONFIG_NLS_CODEPAGE_850=m
+CONFIG_NLS_CODEPAGE_852=m
+CONFIG_NLS_CODEPAGE_855=m
+CONFIG_NLS_CODEPAGE_857=m
+CONFIG_NLS_CODEPAGE_860=m
+CONFIG_NLS_CODEPAGE_861=m
+CONFIG_NLS_CODEPAGE_862=m
+CONFIG_NLS_CODEPAGE_863=m
+CONFIG_NLS_CODEPAGE_864=m
+CONFIG_NLS_CODEPAGE_865=m
+CONFIG_NLS_CODEPAGE_866=m
+CONFIG_NLS_CODEPAGE_869=m
+CONFIG_NLS_CODEPAGE_936=m
+CONFIG_NLS_CODEPAGE_950=m
+CONFIG_NLS_CODEPAGE_932=m
+CONFIG_NLS_CODEPAGE_949=m
+CONFIG_NLS_CODEPAGE_874=m
+CONFIG_NLS_ISO8859_8=m
+CONFIG_NLS_CODEPAGE_1250=m
+CONFIG_NLS_CODEPAGE_1251=m
+CONFIG_NLS_ASCII=y
+CONFIG_NLS_ISO8859_1=m
+CONFIG_NLS_ISO8859_2=m
+CONFIG_NLS_ISO8859_3=m
+CONFIG_NLS_ISO8859_4=m
+CONFIG_NLS_ISO8859_5=m
+CONFIG_NLS_ISO8859_6=m
+CONFIG_NLS_ISO8859_7=m
+CONFIG_NLS_ISO8859_9=m
+CONFIG_NLS_ISO8859_13=m
+CONFIG_NLS_ISO8859_14=m
+CONFIG_NLS_ISO8859_15=m
+CONFIG_NLS_KOI8_R=m
+CONFIG_NLS_KOI8_U=m
+CONFIG_NLS_UTF8=m
+
+#
+# Distributed Lock Manager
+#
+# CONFIG_DLM is not set
+
+#
+# Instrumentation Support
+#
+CONFIG_PROFILING=y
+CONFIG_OPROFILE=m
+CONFIG_KPROBES=y
+
+#
+# Kernel hacking
+#
+CONFIG_TRACE_IRQFLAGS_SUPPORT=y
+CONFIG_PRINTK_TIME=y
+# CONFIG_ENABLE_MUST_CHECK is not set
+CONFIG_MAGIC_SYSRQ=y
+CONFIG_UNUSED_SYMBOLS=y
+CONFIG_DEBUG_FS=y
+# CONFIG_HEADERS_CHECK is not set
+CONFIG_DEBUG_KERNEL=y
+# CONFIG_DEBUG_SHIRQ is not set
+CONFIG_DETECT_SOFTLOCKUP=y
+CONFIG_SCHEDSTATS=y
+CONFIG_TIMER_STATS=y
+# CONFIG_DEBUG_SLAB is not set
+CONFIG_DEBUG_PREEMPT=y
+# CONFIG_DEBUG_RT_MUTEXES is not set
+# CONFIG_RT_MUTEX_TESTER is not set
+CONFIG_DEBUG_SPINLOCK=y
+# CONFIG_DEBUG_MUTEXES is not set
+# CONFIG_DEBUG_LOCK_ALLOC is not set
+# CONFIG_PROVE_LOCKING is not set
+CONFIG_DEBUG_SPINLOCK_SLEEP=y
+# CONFIG_DEBUG_LOCKING_API_SELFTESTS is not set
+# CONFIG_DEBUG_KOBJECT is not set
+# CONFIG_DEBUG_BUGVERBOSE is not set
+CONFIG_DEBUG_INFO=y
+CONFIG_DEBUG_VM=y
+CONFIG_DEBUG_LIST=y
+# CONFIG_FRAME_POINTER is not set
+# CONFIG_FORCED_INLINING is not set
+# CONFIG_RCU_TORTURE_TEST is not set
+# CONFIG_LKDTM is not set
+# CONFIG_FAULT_INJECTION is not set
+CONFIG_EARLY_PRINTK=y
+CONFIG_DEBUG_STACKOVERFLOW=y
+CONFIG_DEBUG_STACK_USAGE=y
+
+#
+# Page alloc debug is incompatible with Software Suspend on i386
+#
+CONFIG_DEBUG_RODATA=y
+CONFIG_4KSTACKS=y
+CONFIG_DOUBLEFAULT=y
+
+#
+# Security options
+#
+CONFIG_KEYS=y
+CONFIG_KEYS_DEBUG_PROC_KEYS=y
+CONFIG_SECURITY=y
+CONFIG_SECURITY_NETWORK=y
+CONFIG_SECURITY_NETWORK_XFRM=y
+CONFIG_SECURITY_CAPABILITIES=y
+# CONFIG_SECURITY_ROOTPLUG is not set
+CONFIG_SECURITY_SELINUX=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM=y
+CONFIG_SECURITY_SELINUX_BOOTPARAM_VALUE=1
+# CONFIG_SECURITY_SELINUX_DISABLE is not set
+CONFIG_SECURITY_SELINUX_DEVELOP=y
+CONFIG_SECURITY_SELINUX_AVC_STATS=y
+CONFIG_SECURITY_SELINUX_CHECKREQPROT_VALUE=1
+# CONFIG_SECURITY_SELINUX_ENABLE_SECMARK_DEFAULT is not set
+# CONFIG_SECURITY_SELINUX_POLICYDB_VERSION_MAX is not set
+
+#
+# Cryptographic options
+#
+CONFIG_CRYPTO=y
+CONFIG_CRYPTO_ALGAPI=y
+CONFIG_CRYPTO_BLKCIPHER=y
+CONFIG_CRYPTO_HASH=y
+CONFIG_CRYPTO_MANAGER=y
+CONFIG_CRYPTO_HMAC=y
+CONFIG_CRYPTO_XCBC=m
+CONFIG_CRYPTO_NULL=m
+CONFIG_CRYPTO_MD4=m
+CONFIG_CRYPTO_MD5=y
+CONFIG_CRYPTO_SHA1=y
+CONFIG_CRYPTO_SHA256=m
+CONFIG_CRYPTO_SHA512=m
+CONFIG_CRYPTO_WP512=m
+CONFIG_CRYPTO_TGR192=m
+CONFIG_CRYPTO_GF128MUL=m
+CONFIG_CRYPTO_ECB=m
+CONFIG_CRYPTO_CBC=m
+CONFIG_CRYPTO_PCBC=m
+CONFIG_CRYPTO_LRW=m
+# CONFIG_CRYPTO_CRYPTD is not set
+CONFIG_CRYPTO_DES=m
+CONFIG_CRYPTO_FCRYPT=m
+CONFIG_CRYPTO_BLOWFISH=m
+CONFIG_CRYPTO_TWOFISH=m
+CONFIG_CRYPTO_TWOFISH_COMMON=m
+# CONFIG_CRYPTO_TWOFISH_586 is not set
+CONFIG_CRYPTO_SERPENT=m
+CONFIG_CRYPTO_AES=m
+CONFIG_CRYPTO_AES_586=m
+CONFIG_CRYPTO_CAST5=m
+CONFIG_CRYPTO_CAST6=m
+CONFIG_CRYPTO_TEA=m
+CONFIG_CRYPTO_ARC4=m
+CONFIG_CRYPTO_KHAZAD=m
+CONFIG_CRYPTO_ANUBIS=m
+CONFIG_CRYPTO_DEFLATE=m
+CONFIG_CRYPTO_MICHAEL_MIC=m
+CONFIG_CRYPTO_CRC32C=m
+CONFIG_CRYPTO_CAMELLIA=m
+# CONFIG_CRYPTO_TEST is not set
+
+#
+# Hardware crypto devices
+#
+# CONFIG_CRYPTO_DEV_PADLOCK is not set
+CONFIG_CRYPTO_DEV_GEODE=y
+
+#
+# Library routines
+#
+CONFIG_BITREVERSE=y
+CONFIG_CRC_CCITT=m
+CONFIG_CRC16=m
+# CONFIG_CRC_ITU_T is not set
+CONFIG_CRC32=y
+CONFIG_LIBCRC32C=m
+CONFIG_AUDIT_GENERIC=y
+CONFIG_ZLIB_INFLATE=y
+CONFIG_ZLIB_DEFLATE=y
+CONFIG_REED_SOLOMON=y
+CONFIG_REED_SOLOMON_DEC16=y
+CONFIG_TEXTSEARCH=y
+CONFIG_TEXTSEARCH_KMP=m
+CONFIG_TEXTSEARCH_BM=m
+CONFIG_TEXTSEARCH_FSM=m
+CONFIG_PLIST=y
+CONFIG_HAS_IOMEM=y
+CONFIG_HAS_IOPORT=y
+CONFIG_HAS_DMA=y
+CONFIG_GENERIC_HARDIRQS=y
+CONFIG_GENERIC_IRQ_PROBE=y
+CONFIG_X86_BIOS_REBOOT=y
+CONFIG_KTIME_SCALAR=y
--- /dev/null
+/* Driver/API for AMD Geode Multi-Function General Purpose Timers (MFGPT)
+ *
+ * Copyright (C) 2006, Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+/* The MFPGT timers on the CS5536 provide us with suitable timers to use
+ * as clock event sources - not as good as a HPET or APIC, but certainly
+ * better then the PIT. This isn't a general purpose MFGPT driver, but
+ * a simplified one designed specifically to act as a clock event source.
+ * For full details about the MFGPT, please consult the CS5536 data sheet.
+*/
+
+/* We are using the 32Khz input clock - its the only one that has the
+ * ranges we find desirable. The following table lists the suitable
+ * divisors and the associated hz, minimum interval
+ * and the maximum interval:
+
+ Divisor Hz Min Delta (S) Max Delta (S)
+ 1 32000 .0005 2.048
+ 2 16000 .001 4.096
+ 4 8000 .002 8.192
+ 8 4000 .004 16.384
+ 16 2000 .008 32.768
+ 32 1000 .016 65.536
+ 64 500 .032 131.072
+ 128 250 .064 262.144
+ 256 125 .128 524.288
+*/
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/clocksource.h>
+#include <linux/clockchips.h>
+#include <asm/geode.h>
+
+#include "do_timer.h"
+
+#define MFGPT_MAX_TIMERS 8
+
+#define F_AVAIL 0x01
+
+static struct mfgpt_timer_t {
+ int flags;
+ struct module *owner;
+} mfgpt_timers[MFGPT_MAX_TIMERS];
+
+/* Selected from the table above */
+
+#define MFGPT_DIVISOR 16
+#define MFGPT_SCALE 4 /* divisor = 2^(scale) */
+#define MFGPT_HZ (32000 / MFGPT_DIVISOR)
+#define MFGPT_PERIODIC (MFGPT_HZ / HZ)
+
+#ifdef CONFIG_GEODE_MFGPT_TIMER
+static int __init mfgpt_timer_setup(void);
+#else
+#define mfgpt_timer_setup() (0)
+#endif
+
+/* Allow for disabling of MFGPTs */
+static int disable = 0;
+static int __init mfgpt_disable(char *s)
+{
+ disable = 1;
+ return 1;
+}
+__setup("nomfgpt", mfgpt_disable);
+
+/*
+ * Check whether any MFGPTs are available for the kernel to use. In most
+ * cases, firmware that uses AMD's VSA code will claim all timers during
+ * bootup; we certainly don't want to take them if they're already in use.
+ * In other cases (such as with VSAless OpenFirmware), the system firmware
+ * leaves timers available for us to use.
+ */
+int __init geode_mfgpt_detect(void)
+{
+ int count = 0, i;
+ u16 val;
+
+ if (disable) {
+ printk(KERN_INFO "geode-mfgpt: Skipping MFGPT setup\n");
+ return 0;
+ }
+
+ for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
+ val = geode_mfgpt_read(i, MFGPT_REG_SETUP);
+ if (!(val & MFGPT_SETUP_SETUP)) {
+ mfgpt_timers[i].flags = F_AVAIL;
+ count++;
+ }
+ }
+
+ /* set up clock event device, if desired */
+ i = mfgpt_timer_setup();
+
+ return count;
+}
+
+int geode_mfgpt_toggle_event(int timer, int cmp, int event, int enable)
+{
+ u32 msr, mask, value, dummy;
+ int shift = (cmp == MFGPT_CMP1) ? 0 : 8;
+
+ if (timer < 0 || timer >= MFGPT_MAX_TIMERS)
+ return -EIO;
+
+ /*
+ * The register maps for these are described in sections 6.17.1.x of
+ * the AMD Geode CS5536 Companion Device Data Book.
+ */
+ switch(event) {
+ case MFGPT_EVENT_RESET:
+ /* XXX: According to the docs, we cannot reset timers above
+ * 6; that is, resets for 7 and 8 will be ignored. Is this
+ * a problem? */
+ msr = MFGPT_NR_MSR;
+ mask = 1 << (timer + 24);
+ break;
+
+ case MFGPT_EVENT_NMI:
+ msr = MFGPT_NR_MSR;
+ mask = 1 << (timer + shift);
+ break;
+
+ case MFGPT_EVENT_IRQ:
+ msr = MFGPT_IRQ_MSR;
+ mask = 1 << (timer + shift);
+ break;
+
+ default:
+ return -EIO;
+ }
+
+ rdmsr(msr, value, dummy);
+
+ if (enable)
+ value |= mask;
+ else
+ value &= ~mask;
+
+ wrmsr(msr, value, dummy);
+ return 0;
+}
+EXPORT_SYMBOL(geode_mfgpt_toggle_event);
+
+int geode_mfgpt_set_irq(int timer, int cmp, int irq, int enable)
+{
+ u32 val, dummy;
+ int offset;
+
+ if (timer < 0 || timer >= MFGPT_MAX_TIMERS)
+ return -EIO;
+
+ if (geode_mfgpt_toggle_event(timer, cmp, MFGPT_EVENT_IRQ, enable))
+ return -EIO;
+
+ rdmsr(0x51400022, val, dummy);
+
+ offset = (timer % 4) * 4;
+
+ val &= ~((0xF << offset) | (0xF << (offset + 16)));
+
+ if (enable) {
+ val |= (irq & 0x0F) << (offset);
+ val |= (irq & 0x0F) << (offset + 16);
+ }
+
+ wrmsr(0x51400022, val, dummy);
+ return 0;
+}
+EXPORT_SYMBOL(geode_mfgpt_set_irq);
+
+static int mfgpt_get(int timer, struct module *owner)
+{
+ mfgpt_timers[timer].flags &= ~F_AVAIL;
+ mfgpt_timers[timer].owner = owner;
+ printk(KERN_INFO "geode-mfgpt: Registered timer %d\n", timer);
+ return timer;
+}
+
+int geode_mfgpt_alloc_timer(int timer, int domain, struct module *owner)
+{
+ int i;
+
+ if (!geode_get_dev_base(GEODE_DEV_MFGPT))
+ return -ENODEV;
+ if (timer >= MFGPT_MAX_TIMERS)
+ return -EIO;
+
+ if (timer < 0) {
+ /* Try to find an available timer */
+ for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
+ if (mfgpt_timers[i].flags & F_AVAIL)
+ return mfgpt_get(i, owner);
+
+ if (i == 5 && domain == MFGPT_DOMAIN_WORKING)
+ break;
+ }
+ }
+ else {
+ /* If they requested a specific timer, try to honor that */
+ if (mfgpt_timers[timer].flags & F_AVAIL)
+ return mfgpt_get(timer, owner);
+ }
+
+ /* No timers available - too bad */
+ return -1;
+}
+EXPORT_SYMBOL(geode_mfgpt_alloc_timer);
+
+#ifdef CONFIG_GEODE_MFGPT_TIMER
+
+static unsigned int mfgpt_tick_mode = CLOCK_EVT_MODE_SHUTDOWN;
+static u16 mfgpt_event_clock;
+
+static int irq = 7;
+static int __init mfgpt_setup(char *str)
+{
+ get_option(&str, &irq);
+ return 1;
+}
+__setup("mfgpt_irq=", mfgpt_setup);
+
+static inline void mfgpt_disable_timer(u16 clock)
+{
+ u16 val = geode_mfgpt_read(clock, MFGPT_REG_SETUP);
+ geode_mfgpt_write(clock, MFGPT_REG_SETUP, val & ~MFGPT_SETUP_CNTEN);
+}
+
+static int mfgpt_next_event(unsigned long, struct clock_event_device *);
+static void mfgpt_set_mode(enum clock_event_mode, struct clock_event_device *);
+
+static struct clock_event_device mfgpt_clockevent = {
+ .name = "mfgpt-timer",
+ .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
+ .set_mode = mfgpt_set_mode,
+ .set_next_event = mfgpt_next_event,
+ .rating = 250,
+ .cpumask = CPU_MASK_ALL,
+ .shift = 32
+};
+
+static inline void mfgpt_start_timer(u16 clock, u16 delta)
+{
+ geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_CMP2, (u16) delta);
+ geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_COUNTER, 0);
+
+ geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP,
+ MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
+}
+
+static void mfgpt_set_mode(enum clock_event_mode mode,
+ struct clock_event_device *evt)
+{
+ mfgpt_disable_timer(mfgpt_event_clock);
+
+ if (mode == CLOCK_EVT_MODE_PERIODIC)
+ mfgpt_start_timer(mfgpt_event_clock, MFGPT_PERIODIC);
+
+ mfgpt_tick_mode = mode;
+}
+
+static int mfgpt_next_event(unsigned long delta, struct clock_event_device *evt)
+{
+ mfgpt_start_timer(mfgpt_event_clock, delta);
+ return 0;
+}
+
+/* Assume (foolishly?), that this interrupt was due to our tick */
+
+static irqreturn_t mfgpt_tick(int irq, void *dev_id)
+{
+ if (mfgpt_tick_mode == CLOCK_EVT_MODE_SHUTDOWN)
+ return IRQ_HANDLED;
+
+ /* Turn off the clock */
+ mfgpt_disable_timer(mfgpt_event_clock);
+
+ /* Clear the counter */
+ geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_COUNTER, 0);
+
+ /* Restart the clock in periodic mode */
+
+ if (mfgpt_tick_mode == CLOCK_EVT_MODE_PERIODIC) {
+ geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP,
+ MFGPT_SETUP_CNTEN | MFGPT_SETUP_CMP2);
+ }
+
+ mfgpt_clockevent.event_handler(&mfgpt_clockevent);
+ return IRQ_HANDLED;
+}
+
+static struct irqaction mfgptirq = {
+ .handler = mfgpt_tick,
+ .flags = IRQF_DISABLED | IRQF_NOBALANCING,
+ .mask = CPU_MASK_NONE,
+ .name = "mfgpt-timer"
+};
+
+static int __init mfgpt_timer_setup(void)
+{
+ int timer, ret;
+ u16 val;
+
+ timer = geode_mfgpt_alloc_timer(MFGPT_TIMER_ANY, MFGPT_DOMAIN_WORKING, THIS_MODULE);
+ if (timer < 0) {
+ printk(KERN_ERR "mfgpt-timer: Could not allocate a MFPGT timer\n");
+ return -ENODEV;
+ }
+
+ mfgpt_event_clock = timer;
+ /* Set the clock scale and enable the event mode for CMP2 */
+ val = MFGPT_SCALE | (3 << 8);
+
+ geode_mfgpt_write(mfgpt_event_clock, MFGPT_REG_SETUP, val);
+
+ /* Set up the IRQ on the MFGPT side */
+ if (geode_mfgpt_setup_irq(mfgpt_event_clock, MFGPT_CMP2, irq)) {
+ printk(KERN_ERR "mfgpt-timer: Could not set up IRQ %d\n", irq);
+ return -EIO;
+ }
+
+ /* And register it with the kernel */
+ ret = setup_irq(irq, &mfgptirq);
+
+ if (ret) {
+ printk(KERN_ERR "mfgpt-timer: Unable to set up the interrupt.\n");
+ goto err;
+ }
+
+ /* Set up the clock event */
+ mfgpt_clockevent.mult = div_sc(MFGPT_HZ, NSEC_PER_SEC, 32);
+ mfgpt_clockevent.min_delta_ns = clockevent_delta2ns(0xF, &mfgpt_clockevent);
+ mfgpt_clockevent.max_delta_ns = clockevent_delta2ns(0xFFFE, &mfgpt_clockevent);
+
+ printk("mfgpt-timer: registering the MFGT timer as a clock event.\n");
+ clockevents_register_device(&mfgpt_clockevent);
+
+ return 0;
+
+err:
+ geode_mfgpt_release_irq(mfgpt_event_clock, MFGPT_CMP2, irq);
+ printk(KERN_ERR "mfgpt-timer: Unable to set up the MFGPT clock source\n");
+ return -EIO;
+}
+
+#endif
--- /dev/null
+/*
+ * ofw.c - Open Firmware client interface for 32-bit systems.
+ * This code is intended to be portable to any 32-bit Open Firmware
+ * implementation with a standard client interface that can be
+ * called when Linux is running.
+ *
+ * Copyright (C) 2007 Mitch Bradley <wmb@firmworks.com>
+ * Copyright (C) 2007 Andres Salomon <dilinger@debian.org>
+ */
+
+#include <stdarg.h>
+#include <linux/spinlock.h>
+#include <linux/module.h>
+#include <asm/ofw.h>
+
+
+int (*call_firmware)(int *);
+
+static DEFINE_SPINLOCK(prom_lock);
+
+#define MAXARGS 20
+
+/*
+ * The return value from ofw() in all cases is 0 if the attempt to call the
+ * function succeeded, <0 otherwise. That return value is from the
+ * gateway function only. Any results from the called function are returned
+ * via output argument pointers.
+ *
+ * Here are call templates for all the standard OFW client services:
+ *
+ * ofw("test", 1, 1, namestr, &missing);
+ * ofw("peer", 1, 1, phandle, &sibling_phandle);
+ * ofw("child", 1, 1, phandle, &child_phandle);
+ * ofw("parent", 1, 1, phandle, &parent_phandle);
+ * ofw("instance_to_package", 1, 1, ihandle, &phandle);
+ * ofw("getproplen", 2, 1, phandle, namestr, &proplen);
+ * ofw("getprop", 4, 1, phandle, namestr, bufaddr, buflen, &size);
+ * ofw("nextprop", 3, 1, phandle, previousstr, bufaddr, &flag);
+ * ofw("setprop", 4, 1, phandle, namestr, bufaddr, len, &size);
+ * ofw("canon", 3, 1, devspecstr, bufaddr, buflen, &length);
+ * ofw("finddevice", 1, 1, devspecstr, &phandle);
+ * ofw("instance-to-path", 3, 1, ihandle, bufaddr, buflen, &length);
+ * ofw("package-to-path", 3, 1, phandle, bufaddr, buflen, &length);
+ * ofw("call_method", numin, numout, in0, in1, ..., &out0, &out1, ...);
+ * ofw("open", 1, 1, devspecstr, &ihandle);
+ * ofw("close", 1, 0, ihandle);
+ * ofw("read", 3, 1, ihandle, addr, len, &actual);
+ * ofw("write", 3, 1, ihandle, addr, len, &actual);
+ * ofw("seek", 3, 1, ihandle, pos_hi, pos_lo, &status);
+ * ofw("claim", 3, 1, virtaddr, size, align, &baseaddr);
+ * ofw("release", 2, 0, virtaddr, size);
+ * ofw("boot", 1, 0, bootspecstr);
+ * ofw("enter", 0, 0);
+ * ofw("exit", 0, 0);
+ * ofw("chain", 5, 0, virtaddr, size, entryaddr, argsaddr, len);
+ * ofw("interpret", numin+1, numout+1, cmdstr, in0, ..., &catchres, &out0, ...);
+ * ofw("set-callback", 1, 1, newfuncaddr, &oldfuncaddr);
+ * ofw("set-symbol-lookup", 2, 0, symtovaladdr, valtosymaddr);
+ * ofw("milliseconds", 0, 1, &ms);
+ */
+
+int ofw(char *name, int numargs, int numres, ...)
+{
+ va_list ap;
+ int argarray[MAXARGS+3];
+ int argnum = 3;
+ int retval;
+ int *intp;
+ unsigned long flags;
+
+ if (!call_firmware)
+ return -1;
+ if ((numargs + numres) > MAXARGS)
+ return -1; /* spit out an error? */
+
+ argarray[0] = (int) name;
+ argarray[1] = numargs;
+ argarray[2] = numres;
+
+ va_start(ap, numres);
+ while (numargs) {
+ argarray[argnum++] = va_arg(ap, int);
+ numargs--;
+ }
+
+ spin_lock_irqsave(&prom_lock, flags);
+ retval = call_firmware(argarray);
+ spin_unlock_irqrestore(&prom_lock, flags);
+
+ if (retval == 0) {
+ while (numres) {
+ intp = va_arg(ap, int *);
+ *intp = argarray[argnum++];
+ numres--;
+ }
+ }
+ va_end(ap);
+ return retval;
+}
+EXPORT_SYMBOL(ofw);
--- /dev/null
+/* olpc-pm.c
+ * © 2006 Red Hat, Inc.
+ * Portions also copyright 2006 Advanced Micro Devices, Inc.
+ * GPLv2
+ */
+
+#include <linux/kernel.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/delay.h>
+#include <linux/input.h>
+#include <linux/suspend.h>
+#include <linux/bootmem.h>
+#include <linux/platform_device.h>
+#include <linux/rtc.h>
+#include <linux/mc146818rtc.h>
+#include <asm/io.h>
+
+#include <asm/olpc.h>
+
+/* A few words about accessing the ACPI and PM registers. Long story short,
+ byte and word accesses of the ACPI and PM registers is broken. The only
+ way to do it really correctly is to use dword accesses, which we do
+ throughout this code. For more details, please consult Eratta 17 and 18
+ here:
+
+ http://www.amd.com/files/connectivitysolutions/geode/geode_gx/34472D_CS5536_B1_specupdate.pdf
+*/
+
+#define PM_IRQ 3
+
+#define CS5536_PM_PWRBTN (1 << 8)
+#define CS5536_PM_RTC (1 << 10)
+
+#define GPIO_WAKEUP_EC (1 << 31)
+#define GPIO_WAKEUP_LID (1 << 30)
+
+#define PM_MODE_NORMAL 0
+#define PM_MODE_TEST 1
+#define PM_MODE_MAX 2
+
+/* These, and the battery EC commands, should be in an olpc.h. */
+#define EC_WRITE_SCI_MASK 0x1b
+#define EC_READ_SCI_MASK 0x1c
+
+extern void do_olpc_suspend_lowlevel(void);
+
+static struct {
+ unsigned long address;
+ unsigned short segment;
+} ofw_bios_entry = { 0, __KERNEL_CS };
+
+static int olpc_pm_mode = PM_MODE_NORMAL;
+static unsigned long acpi_base;
+static unsigned long pms_base;
+static int sci_irq;
+static int olpc_lid_flag;
+
+static struct input_dev *pm_inputdev;
+static struct input_dev *lid_inputdev;
+static struct input_dev *ebook_inputdev;
+static struct pm_ops olpc_pm_ops;
+
+static int gpio_wake_events = 0;
+static int ebook_state = -1;
+static u16 olpc_wakeup_mask = 0;
+
+struct platform_device olpc_powerbutton_dev = {
+ .name = "powerbutton",
+ .id = -1,
+};
+
+struct platform_device olpc_lid_dev = {
+ .name = "lid",
+ .id = -1,
+};
+
+static void __init init_ebook_state(void)
+{
+ if (olpc_ec_cmd(0x2a, NULL, 0, (unsigned char *) &ebook_state, 1)) {
+ printk(KERN_WARNING "olpc-pm: failed to get EBOOK state!\n");
+ ebook_state = 0;
+ }
+ ebook_state &= 1;
+
+ /* the input layer needs to know what value to default to as well */
+ input_report_switch(ebook_inputdev, SW_TABLET_MODE, ebook_state);
+ input_sync(ebook_inputdev);
+}
+
+static void (*battery_callback)(unsigned long);
+static DEFINE_SPINLOCK(battery_callback_lock);
+
+/* propagate_events is non-NULL if run from workqueue,
+ NULL when called at init time to flush SCI queue */
+static void process_sci_queue(struct work_struct *propagate_events)
+{
+ unsigned char data = 0;
+ unsigned char battery_events = 0;
+ int ret;
+
+ do {
+ ret = olpc_ec_cmd(0x84, NULL, 0, &data, 1);
+ if (!ret) {
+ printk(KERN_DEBUG "olpc-pm: SCI 0x%x received\n",
+ data);
+
+ switch (data) {
+ case EC_SCI_SRC_EMPTY:
+ case EC_SCI_SRC_GAME:
+ case EC_SCI_SRC_WLAN:
+ /* we ignore these for now */
+ break;
+ case EC_SCI_SRC_BATERR:
+ printk(KERN_ERR "olpc-pm: Battery Management System detected an error! Remove turnip from battery slot.\n");
+ case EC_SCI_SRC_BATSOC:
+ case EC_SCI_SRC_BATTERY:
+ case EC_SCI_SRC_ACPWR:
+ battery_events |= data;
+ break;
+ case EC_SCI_SRC_EBOOK:
+ ebook_state = !ebook_state;
+ if (propagate_events) {
+ input_report_switch(ebook_inputdev,
+ SW_TABLET_MODE, ebook_state);
+ input_sync(ebook_inputdev);
+ }
+ break;
+ default:
+ printk(KERN_ERR "olpc-pm: Unknown SCI event 0x%x occurred!\n", data);
+ }
+ }
+ } while (data && !ret);
+
+ if (battery_events && battery_callback && propagate_events) {
+ void (*cbk)(unsigned long);
+
+ /* Older EC versions didn't distinguish between AC and battery
+ events */
+ if (olpc_platform_info.ecver < 0x45)
+ battery_events = EC_SCI_SRC_BATTERY | EC_SCI_SRC_ACPWR;
+
+ spin_lock(&battery_callback_lock);
+ cbk = battery_callback;
+ spin_unlock(&battery_callback_lock);
+
+ cbk(battery_events);
+ }
+
+ if (ret)
+ printk(KERN_WARNING "Failed to clear SCI queue!\n");
+}
+
+static DECLARE_WORK(sci_work, process_sci_queue);
+
+void olpc_register_battery_callback(void (*f)(unsigned long))
+{
+ spin_lock(&battery_callback_lock);
+ battery_callback = f;
+ spin_unlock(&battery_callback_lock);
+}
+EXPORT_SYMBOL_GPL(olpc_register_battery_callback);
+
+void olpc_deregister_battery_callback(void)
+{
+ spin_lock(&battery_callback_lock);
+ battery_callback = NULL;
+ spin_unlock(&battery_callback_lock);
+ cancel_work_sync(&sci_work);
+}
+EXPORT_SYMBOL_GPL(olpc_deregister_battery_callback);
+
+
+static int olpc_pm_interrupt(int irq, void *id)
+{
+ uint32_t sts, gpe = 0;
+
+ sts = inl(acpi_base + PM1_STS);
+ outl(sts | 0xFFFF, acpi_base + PM1_STS);
+
+ if (olpc_get_rev() >= OLPC_REV_B2) {
+ gpe = inl(acpi_base + PM_GPE0_STS);
+ outl(0xFFFFFFFF, acpi_base + PM_GPE0_STS);
+ }
+
+ if (sts & CS5536_PM_PWRBTN) {
+ input_report_key(pm_inputdev, KEY_POWER, 1);
+ input_sync(pm_inputdev);
+ printk(KERN_DEBUG "olpm-pm: PM_PWRBTN event received\n");
+ /* Do we need to delay this (and hence schedule_work)? */
+ input_report_key(pm_inputdev, KEY_POWER, 0);
+ input_sync(pm_inputdev);
+ }
+
+ if (gpe & GPIO_WAKEUP_EC) {
+ geode_gpio_clear(OLPC_GPIO_ECSCI, GPIO_NEGATIVE_EDGE_STS);
+ schedule_work(&sci_work);
+ }
+
+ if (gpe & GPIO_WAKEUP_LID) {
+ /* Disable events */
+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_EVENTS_ENABLE);
+
+ /* Clear the edge */
+
+ if (olpc_lid_flag)
+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_NEGATIVE_EDGE_EN);
+ else
+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_POSITIVE_EDGE_EN);
+
+ /* Clear the status too */
+ geode_gpio_set(OLPC_GPIO_LID, GPIO_NEGATIVE_EDGE_STS);
+ geode_gpio_set(OLPC_GPIO_LID, GPIO_POSITIVE_EDGE_STS);
+
+ /* The line is high when the LID is open, but SW_LID
+ * should be high when the LID is closed, so we pass the old
+ * value of olpc_lid_flag
+ */
+
+ input_report_switch(lid_inputdev, SW_LID, olpc_lid_flag);
+ input_sync(lid_inputdev);
+
+ /* Swap the status */
+ olpc_lid_flag = !olpc_lid_flag;
+
+ if (olpc_lid_flag)
+ geode_gpio_set(OLPC_GPIO_LID, GPIO_NEGATIVE_EDGE_EN);
+ else
+ geode_gpio_set(OLPC_GPIO_LID, GPIO_POSITIVE_EDGE_EN);
+
+ /* re-enable the event */
+ geode_gpio_set(OLPC_GPIO_LID, GPIO_EVENTS_ENABLE);
+ }
+
+ return IRQ_HANDLED;
+}
+
+/*
+ * For now, only support STR. We also don't support suspending on
+ * B1s, due to difficulties with the cafe FPGA.
+ */
+static int olpc_pm_state_valid(suspend_state_t pm_state)
+{
+ if (pm_state == PM_SUSPEND_MEM && olpc_rev_after(OLPC_REV_B1))
+ return 1;
+
+ return 0;
+}
+
+/* This is a catchall function for operations that just don't belong
+ * anywhere else. Later we will evaluate if these belong in the
+ * individual device drivers or the firmware.
+ * If you add something to this function, please explain yourself with
+ * a comment.
+ */
+
+extern void gxfb_flatpanel_control(int state);
+
+static u32 gpio_wakeup[2];
+static u64 irq_sources[4];
+static u64 mfgpt_irq_msr, mfgpt_nr_msr;
+
+void olpc_fixup_wakeup(void)
+{
+ u32 base = geode_gpio_base();
+ int i;
+
+ /* This clears any pending events from the status register -
+ * the firmware also does this, but its possible that it tries
+ * it too early before the key has a chance to debounce
+ */
+
+ outl((CS5536_PM_PWRBTN << 16) | 0xFFFF, acpi_base + PM1_STS);
+
+ /* Enable the flatpanel sequencing as early as possible, because
+ it takes ~64ms to resume. This probably belongs in the firmware */
+
+ //gxfb_flatpanel_control(1);
+
+ /* Restore the interrupt sources */
+ wrmsrl(MSR_PIC_YSEL_LOW, irq_sources[0]);
+ wrmsrl(MSR_PIC_ZSEL_LOW, irq_sources[1]);
+ wrmsrl(MSR_PIC_YSEL_HIGH, irq_sources[2]);
+ wrmsrl(MSR_PIC_ZSEL_HIGH, irq_sources[3]);
+
+ /* Restore the X and Y sources for GPIO */
+ outl(gpio_wakeup[0], base + GPIO_MAP_X);
+ outl(gpio_wakeup[1], base + GPIO_MAP_Y);
+
+ /* Resture the MFGPT MSRs */
+ wrmsrl(MFGPT_IRQ_MSR, mfgpt_irq_msr);
+ wrmsrl(MFGPT_NR_MSR, mfgpt_nr_msr);
+
+ for (i=0;i<2;i++) {
+ /* tell the wireless module to restart USB communication */
+ olpc_ec_cmd(0x24, NULL, 0, NULL, 0);
+ }
+}
+
+void olpc_fixup_sleep(void)
+{
+ u32 base = geode_gpio_base();
+ int i;
+
+ /* Save the X and Y sources for GPIO */
+ gpio_wakeup[0] = inl(base + GPIO_MAP_X);
+ gpio_wakeup[1] = inl(base + GPIO_MAP_Y);
+
+ /* Save the Y and Z unrestricted sources */
+
+ rdmsrl(MSR_PIC_YSEL_LOW, irq_sources[0]);
+ rdmsrl(MSR_PIC_ZSEL_LOW, irq_sources[1]);
+ rdmsrl(MSR_PIC_YSEL_HIGH, irq_sources[2]);
+ rdmsrl(MSR_PIC_ZSEL_HIGH, irq_sources[3]);
+
+ /* Turn off the MFGPT timers on the way down */
+
+ for(i = 0; i < 8; i++) {
+ u32 val = geode_mfgpt_read(i, MFGPT_REG_SETUP);
+
+ if (val & MFGPT_SETUP_SETUP) {
+ val &= ~MFGPT_SETUP_CNTEN;
+ geode_mfgpt_write(i, MFGPT_REG_SETUP, val);
+ }
+ }
+
+ /* Save the MFGPT MSRs */
+ rdmsrl(MFGPT_IRQ_MSR, mfgpt_irq_msr);
+ rdmsrl(MFGPT_NR_MSR, mfgpt_nr_msr);
+
+ if (device_may_wakeup(&olpc_powerbutton_dev.dev))
+ olpc_wakeup_mask |= CS5536_PM_PWRBTN;
+ else
+ olpc_wakeup_mask &= ~(CS5536_PM_PWRBTN);
+
+ if (device_may_wakeup(&olpc_lid_dev.dev)) {
+ geode_gpio_set(OLPC_GPIO_LID, GPIO_EVENTS_ENABLE);
+ gpio_wake_events |= GPIO_WAKEUP_LID;
+ } else {
+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_EVENTS_ENABLE);
+ gpio_wake_events &= ~(GPIO_WAKEUP_LID);
+ }
+}
+
+static int olpc_pm_enter(suspend_state_t pm_state)
+{
+ /* Only STR is supported */
+ if (pm_state != PM_SUSPEND_MEM)
+ return -EINVAL;
+
+ olpc_fixup_sleep();
+
+ /* Set the GPIO wakeup bits */
+ outl(gpio_wake_events, acpi_base + PM_GPE0_EN);
+ outl(0xFFFFFFFF, acpi_base + PM_GPE0_STS);
+
+ /* Save CPU state */
+ do_olpc_suspend_lowlevel();
+
+ olpc_fixup_wakeup();
+
+ /* Restore the SCI wakeup events */
+ outl(gpio_wake_events, acpi_base + PM_GPE0_EN);
+
+ return 0;
+}
+
+int asmlinkage olpc_do_sleep(u8 sleep_state)
+{
+ void *pgd_addr = __va(read_cr3());
+ printk(KERN_ERR "olpc_do_sleep!\n"); /* this needs to remain here so
+ * that gcc doesn't optimize
+ * away our __va! */
+ /* FIXME: Set the SCI bits we want to wake up on here */
+
+ /* FIXME: Set any other SCI events that we might want here */
+
+ outl((olpc_wakeup_mask << 16) | 0xFFFF, acpi_base + PM1_STS);
+
+ /* If we are in test mode, then just return (simulate a successful
+ suspend/resume). Otherwise, if we are doing the real thing,
+ then go for the gusto */
+
+ if (olpc_pm_mode != PM_MODE_TEST) {
+ __asm__ __volatile__("movl %0,%%eax" : : "r" (pgd_addr));
+ __asm__("call *(%%edi); cld"
+ : : "D" (&ofw_bios_entry));
+ }
+
+ return 0;
+}
+
+/* This code will slowly disappear as we fixup the issues in the BIOS */
+
+static void __init olpc_fixup_bios(void)
+{
+ unsigned long hi, lo;
+
+ if (olpc_has_vsa()) {
+ /* The VSA aggressively sets up the ACPI and PM register for
+ * trapping - its not enough to force these values in the BIOS -
+ * they seem to be changed during PCI init as well.
+ */
+
+ /* Change the PM registers to decode to the DD */
+
+ rdmsr(0x510100e2, lo, hi);
+ hi |= 0x80000000;
+ wrmsr(0x510100e2, lo, hi);
+
+ /* Change the ACPI registers to decode to the DD */
+
+ rdmsr(0x510100e3, lo, hi);
+ hi |= 0x80000000;
+ wrmsr(0x510100e3, lo, hi);
+ }
+
+ /* GPIO24 controls WORK_AUX */
+
+ geode_gpio_set(OLPC_GPIO_WORKAUX, GPIO_OUTPUT_ENABLE);
+ geode_gpio_set(OLPC_GPIO_WORKAUX, GPIO_OUTPUT_AUX1);
+
+ if (olpc_get_rev() >= OLPC_REV_B2) {
+ /* GPIO10 is connected to the thermal alarm */
+ geode_gpio_set(OLPC_GPIO_THRM_ALRM, GPIO_INPUT_ENABLE);
+ geode_gpio_set(OLPC_GPIO_THRM_ALRM, GPIO_INPUT_AUX1);
+
+ /* Set up to get LID events */
+ geode_gpio_set(OLPC_GPIO_LID, GPIO_INPUT_ENABLE);
+
+ /* Clear edge detection and event enable for now */
+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_EVENTS_ENABLE);
+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_NEGATIVE_EDGE_EN);
+ geode_gpio_clear(OLPC_GPIO_LID, GPIO_POSITIVE_EDGE_EN);
+
+ geode_gpio_set(OLPC_GPIO_LID, GPIO_NEGATIVE_EDGE_STS);
+ geode_gpio_set(OLPC_GPIO_LID, GPIO_POSITIVE_EDGE_STS);
+
+ /* Set the LID to cause an PME event on group 6 */
+ geode_gpio_event_pme(OLPC_GPIO_LID, 6);
+
+ /* Set PME group 6 to fire the SCI interrupt */
+ geode_gpio_set_irq(6, sci_irq);
+ }
+
+ geode_gpio_set(OLPC_GPIO_ECSCI, GPIO_INPUT_ENABLE);
+
+ /* Clear pending events */
+
+ geode_gpio_set(OLPC_GPIO_ECSCI, GPIO_NEGATIVE_EDGE_STS);
+ geode_gpio_set(OLPC_GPIO_ECSCI, GPIO_POSITIVE_EDGE_STS);
+
+ //geode_gpio_set(OLPC_GPIO_ECSCI, GPIO_NEGATIVE_EDGE_EN);
+ geode_gpio_set(OLPC_GPIO_ECSCI, GPIO_EVENTS_ENABLE);
+
+ /* Set the SCI to cause a PME event on group 7 */
+ geode_gpio_event_pme(OLPC_GPIO_ECSCI, 7);
+
+ /* And have group 6 also fire the SCI interrupt */
+ geode_gpio_set_irq(7, sci_irq);
+}
+
+/* This provides a control file for setting up testing of the
+ power management system. For now, there is just one setting:
+ "test" which means that we don't actually enter the power
+ off routine.
+*/
+
+static const char * const pm_states[] = {
+ [PM_MODE_NORMAL] = "normal",
+ [PM_MODE_TEST] = "test",
+};
+
+extern struct mutex pm_mutex;
+extern struct kset power_subsys;
+
+static ssize_t control_show(struct kset *s, char *buf)
+{
+ return sprintf(buf, "%s\n", pm_states[olpc_pm_mode]);
+}
+
+static ssize_t control_store(struct kset *s, const char *buf, size_t n)
+{
+ int i, len;
+ char *p;
+
+ p = memchr(buf, '\n', n);
+ len = p ? p - buf : n;
+
+ /* Grab the mutex */
+ mutex_lock(&pm_mutex);
+
+ for(i = 0; i < PM_MODE_MAX; i++) {
+ if (!strncmp(buf, pm_states[i], len)) {
+ olpc_pm_mode = i;
+ break;
+ }
+ }
+
+ mutex_unlock(&pm_mutex);
+
+ return (i == PM_MODE_MAX) ? -EINVAL : n;
+}
+
+static struct subsys_attribute control_attr = {
+ .attr = {
+ .name = "olpc-pm",
+ .mode = 0644,
+ },
+ .show = control_show,
+ .store = control_store,
+};
+
+static struct attribute * olpc_attributes[] = {
+ &control_attr.attr,
+ NULL
+};
+
+static struct attribute_group olpc_attrs = {
+ .attrs = olpc_attributes,
+};
+
+static int __init alloc_inputdevs(void)
+{
+ int ret = -ENOMEM;
+
+ pm_inputdev = input_allocate_device();
+ if (!pm_inputdev)
+ goto err;
+
+ pm_inputdev->name = "OLPC PM";
+ pm_inputdev->phys = "olpc_pm/input0";
+ set_bit(EV_KEY, pm_inputdev->evbit);
+ set_bit(KEY_POWER, pm_inputdev->keybit);
+
+ ret = input_register_device(pm_inputdev);
+ if (ret) {
+ printk(KERN_ERR "olpc-pm: failed to register PM input device: %d\n", ret);
+ goto err;
+ }
+
+ lid_inputdev = input_allocate_device();
+ if (!lid_inputdev)
+ goto err;
+
+ lid_inputdev->name = "OLPC lid switch";
+ lid_inputdev->phys = "olpc_pm/input1";
+ set_bit(EV_SW, lid_inputdev->evbit);
+ set_bit(SW_LID, lid_inputdev->swbit);
+
+ ret = input_register_device(lid_inputdev);
+ if (ret) {
+ printk(KERN_ERR "olpc-pm: failed to register lid input device: %d\n", ret);
+ goto err;
+ }
+
+ ebook_inputdev = input_allocate_device();
+ if (!ebook_inputdev)
+ goto err;
+
+ ebook_inputdev->name = "OLPC ebook switch";
+ ebook_inputdev->phys = "olpc_pm/input2";
+ set_bit(EV_SW, ebook_inputdev->evbit);
+ set_bit(SW_TABLET_MODE, ebook_inputdev->swbit);
+
+ ret = input_register_device(ebook_inputdev);
+ if (ret) {
+ printk(KERN_ERR "olpc-pm: failed to register ebook input device: %d\n", ret);
+ goto err;
+ }
+
+ return ret;
+err:
+ if (ebook_inputdev) {
+ input_unregister_device(ebook_inputdev);
+ ebook_inputdev = NULL;
+ }
+ if (lid_inputdev) {
+ input_unregister_device(lid_inputdev);
+ lid_inputdev = NULL;
+ }
+ if (pm_inputdev) {
+ input_unregister_device(pm_inputdev);
+ pm_inputdev = NULL;
+ }
+
+ return ret;
+}
+
+static int __init olpc_pm_init(void)
+{
+ uint32_t lo, hi;
+ int ret;
+ uint8_t ec_byte;
+
+ if (!machine_is_olpc())
+ return -ENODEV;
+
+ acpi_base = geode_acpi_base();
+ pms_base = geode_pms_base();
+
+ if (!acpi_base || !pms_base)
+ return -ENODEV;
+
+ ret = alloc_inputdevs();
+ if (ret)
+ return ret;
+
+ rdmsr(0x51400020, lo, hi);
+ sci_irq = (lo >> 20) & 15;
+
+ if (sci_irq) {
+ printk(KERN_INFO "SCI is mapped to IRQ %d\n", sci_irq);
+ } else {
+ /* Zero doesn't mean zero -- it means masked */
+ printk(KERN_INFO "SCI unmapped. Mapping to IRQ 3\n");
+ sci_irq = 3;
+ lo |= 0x00300000;
+ wrmsrl(0x51400020, lo);
+ }
+
+ olpc_fixup_bios();
+
+ lo = inl(pms_base + PM_FSD);
+
+ /* Lock, enable failsafe, 4 seconds */
+ outl(0xc001f400, pms_base + PM_FSD);
+
+ /* Here we set up the SCI events we're interested in during
+ * real-time. We have no sleep button, and the RTC doesn't make
+ * sense, so set up the power button
+ */
+
+ outl(inl(acpi_base) | ((CS5536_PM_PWRBTN) << 16), acpi_base);
+
+ if (olpc_get_rev() >= OLPC_REV_B2) {
+ gpio_wake_events |= GPIO_WAKEUP_LID;
+
+ /* Get the current value of the GPIO, and set up the edges */
+ olpc_lid_flag = geode_gpio_isset(OLPC_GPIO_LID, GPIO_READ_BACK);
+
+ /* Watch for the opposite edge */
+
+ if (olpc_lid_flag)
+ geode_gpio_set(OLPC_GPIO_LID, GPIO_NEGATIVE_EDGE_EN);
+ else
+ geode_gpio_set(OLPC_GPIO_LID, GPIO_POSITIVE_EDGE_EN);
+
+ /* Enable the event */
+ geode_gpio_set(OLPC_GPIO_LID, GPIO_EVENTS_ENABLE);
+ }
+
+ /* Set up the mask for wakeups the EC will generate SCIs on */
+
+ ret = olpc_ec_cmd(EC_READ_SCI_MASK, NULL, 0, &ec_byte, 1);
+ if (ret)
+ printk(KERN_ERR "Error getting the EC SCI mask: %d\n", ret);
+
+ /* Disable battery 1% charge wakeups */
+ ec_byte &= ~EC_SCI_SRC_BATSOC;
+
+ ret = olpc_ec_cmd(EC_WRITE_SCI_MASK, &ec_byte, 1, NULL, 0);
+ if (ret)
+ printk(KERN_ERR "Error setting the EC SCI mask: %d\n", ret);
+
+ /* Set up the EC SCI */
+
+ gpio_wake_events |= GPIO_WAKEUP_EC;
+
+ outl(gpio_wake_events, acpi_base + PM_GPE0_EN);
+ outl(0xFFFFFFFF, acpi_base + PM_GPE0_STS);
+
+ /* Select level triggered in PIC */
+
+ if (sci_irq < 8) {
+ lo = inb(0x4d0);
+ lo |= 1 << sci_irq;
+ outb(lo, 0x4d0);
+ } else {
+ lo = inb(0x4d1);
+ lo |= 1 << (sci_irq - 8);
+ outb(lo, 0x4d1);
+ }
+ /* Clear pending interrupt */
+ outl(inl(acpi_base) | 0xFFFF, acpi_base);
+ process_sci_queue(0); /* we just want to flush the queue here */
+ init_ebook_state();
+
+ /* Enable the interrupt */
+
+ ret = request_irq(sci_irq, &olpc_pm_interrupt, 0, "SCI", &acpi_base);
+
+ if (ret) {
+ printk(KERN_ERR "Error registering SCI: %d\n", ret);
+ return ret;
+ }
+
+ ofw_bios_entry.address = 0xF0000 + PAGE_OFFSET;
+ pm_set_ops(&olpc_pm_ops);
+
+ sysfs_create_group(&power_subsys.kobj, &olpc_attrs);
+
+ return 0;
+}
+
+
+#if defined (CONFIG_RTC_DRV_CMOS) || defined (CONFIG_RTC_DRV_CMOS_MODULE)
+struct resource rtc_platform_resource[2] = {
+ {
+ .flags = IORESOURCE_IO,
+ .start = RTC_PORT(0),
+ .end = RTC_PORT(0) + RTC_IO_EXTENT
+ },
+ {
+ .flags = IORESOURCE_IRQ,
+ .start = 8,
+ .end = 8,
+ },
+};
+
+
+static void rtc_wake_on(struct device *dev)
+{
+ olpc_wakeup_mask |= CS5536_PM_RTC;
+}
+
+static void rtc_wake_off(struct device *dev)
+{
+ olpc_wakeup_mask &= ~(CS5536_PM_RTC);
+}
+
+static struct cmos_rtc_board_info rtc_info = {
+ .rtc_day_alarm = 0,
+ .rtc_mon_alarm = 0,
+ .rtc_century = 0,
+ .wake_on = rtc_wake_on,
+ .wake_off = rtc_wake_off,
+};
+
+struct platform_device olpc_rtc_device = {
+ .name = "rtc_cmos",
+ .id = -1,
+ .num_resources = ARRAY_SIZE(rtc_platform_resource),
+ .dev.platform_data = &rtc_info,
+ .resource = rtc_platform_resource,
+};
+
+static int __init olpc_platform_init(void)
+{
+ (void)platform_device_register(&olpc_rtc_device);
+ device_init_wakeup(&olpc_rtc_device.dev, 1);
+
+ (void)platform_device_register(&olpc_powerbutton_dev);
+ device_init_wakeup(&olpc_powerbutton_dev.dev, 1);
+
+ (void)platform_device_register(&olpc_lid_dev);
+ device_init_wakeup(&olpc_lid_dev.dev, 1);
+
+ return 0;
+}
+arch_initcall(olpc_platform_init);
+#endif /* CONFIG_RTC_DRV_CMOS */
+
+static void olpc_pm_exit(void)
+{
+ /* Clear any pending events, and disable them */
+ outl(0xFFFF, acpi_base+2);
+
+ free_irq(sci_irq, &acpi_base);
+ input_unregister_device(pm_inputdev);
+ input_unregister_device(lid_inputdev);
+ input_unregister_device(ebook_inputdev);
+}
+
+static struct pm_ops olpc_pm_ops = {
+ .valid = olpc_pm_state_valid,
+ .enter = olpc_pm_enter,
+};
+
+module_init(olpc_pm_init);
+module_exit(olpc_pm_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
+MODULE_DESCRIPTION("AMD Geode power management for OLPC CL1");
--- /dev/null
+.text
+
+ENTRY(olpc_sleep_asm)
+olpc_sleep:
+ ;; Get the value of PM1_CNT and store it off
+
+ add 08h, ax
+ mov bx,dx
+ in dx,eax
+ or 2000h, ax
+ mov ax,di
+
+ ;; flush the cache
+ wbinvd
+
+ ;; GX2 must disable refresh before going into self-refresh
+ mov 2000000180xh, ecx
+ rdmsr
+ mov eax, esi
+ and 0FF0000FFh, eax
+ wrmsr
+
+ ;; Now, put the memory into self refresh
+ mov 2004, cx
+ xor edx, edx
+ xor eax, eax
+ mov 04h, al
+ wrmsr
+
+ ;; Thats all she wrote - time to go to sleep
+
+ mov bx, dx
+ movzx di, eax
+ out eax, dx
+
+ ;;
+
+
+
--- /dev/null
+.text
+#include <linux/linkage.h>
+#include <asm/segment.h>
+#include <asm/page.h>
+
+ALIGN
+ .align 4096
+
+wakeup_start:
+# jmp wakeup_start
+
+ cli
+ cld
+
+ # Clear any dangerous flags
+
+ pushl $0
+ popfl
+
+ # Set up %cr3
+ movl $swsusp_pg_dir - __PAGE_OFFSET, %eax
+ movl %eax, %cr3
+
+ movl saved_cr4, %eax
+ movl %eax, %cr4
+
+ movl saved_cr0, %eax
+ movl %eax, %cr0
+
+ jmp 1f
+1:
+ ljmpl $__KERNEL_CS,$wakeup_return
+
+
+.org 0x1000
+
+wakeup_return:
+ movw $__KERNEL_DS, %ax
+ movw %ax, %ss
+ movw %ax, %ds
+ movw %ax, %es
+ movw %ax, %fs
+ movw %ax, %gs
+
+ lgdt saved_gdt
+ lidt saved_idt
+ lldt saved_ldt
+ ljmp $(__KERNEL_CS),$1f
+1:
+ movl %cr3, %eax
+ movl %eax, %cr3
+ wbinvd
+
+ # Go back to the return point
+ jmp ret_point
+
+save_registers:
+ sgdt saved_gdt
+ sidt saved_idt
+ sldt saved_ldt
+
+ pushl %edx
+ movl %cr4, %edx
+ movl %edx, saved_cr4
+
+ movl %cr0, %edx
+ movl %edx, saved_cr0
+
+ popl %edx
+
+
+ movl %ebx, saved_context_ebx
+ movl %ebp, saved_context_ebp
+ movl %esi, saved_context_esi
+ movl %edi, saved_context_edi
+
+ pushfl
+ popl saved_context_eflags
+
+ ret
+
+
+restore_registers:
+ movl saved_context_ebp, %ebp
+ movl saved_context_ebx, %ebx
+ movl saved_context_esi, %esi
+ movl saved_context_edi, %edi
+
+ pushl saved_context_eflags
+ popfl
+
+ ret
+
+
+ENTRY(do_olpc_suspend_lowlevel)
+ call save_processor_state
+ call save_registers
+
+ # This is the stack context we want to remember
+ movl %esp, saved_context_esp
+
+ pushl $3
+ call olpc_do_sleep
+
+ jmp wakeup_start
+ .p2align 4,,7
+ret_point:
+ movl saved_context_esp, %esp
+
+ call restore_registers
+ call restore_processor_state
+ ret
+
+.data
+ALIGN
+
+saved_gdt: .long 0,0
+saved_idt: .long 0,0
+saved_ldt: .long 0
+saved_cr4: .long 0
+saved_cr0: .long 0
+
--- /dev/null
+/* Support for the OLPC DCON and OLPC EC access
+ * Copyright (C) 2006, Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#include <linux/autoconf.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/mc146818rtc.h>
+#include <linux/delay.h>
+#include <linux/spinlock.h>
+
+#include <asm/olpc.h>
+#include <asm/ofw.h>
+
+/* This is our new multi-purpose structure used to contain the
+ * information about the platform that we detect
+ */
+
+struct olpc_platform_t olpc_platform_info;
+EXPORT_SYMBOL_GPL(olpc_platform_info);
+
+/*********************************************************************
+ * EC locking and access
+ *********************************************************************/
+
+static DEFINE_SPINLOCK(ec_lock);
+
+/* what the timeout *should* be (in ms) */
+#define EC_BASE_TIMEOUT 20
+
+/* the timeout that bugs in the EC might force us to actually use */
+static int ec_timeout = EC_BASE_TIMEOUT;
+
+static int __init olpc_ec_timeout_set(char *str)
+{
+ if (get_option(&str, &ec_timeout) != 1) {
+ ec_timeout = EC_BASE_TIMEOUT;
+ printk(KERN_ERR "olpc-ec: invalid argument to "
+ "'olpc_ec_timeout=', ignoring!\n");
+ }
+ printk(KERN_DEBUG "olpc-ec: using %d ms delay for EC commands.\n",
+ ec_timeout);
+ return 1;
+}
+__setup("olpc_ec_timeout=", olpc_ec_timeout_set);
+
+/*
+ * These *bf_status functions return whether the buffers are full or not.
+ */
+
+static inline unsigned int ibf_status(unsigned int port)
+{
+ return inb(port) & 0x02;
+}
+
+static inline unsigned int obf_status(unsigned int port)
+{
+ return inb(port) & 0x01;
+}
+
+#define wait_on_ibf(p, d) __wait_on_ibf(__LINE__, (p), (d))
+static int __wait_on_ibf(unsigned int line, unsigned int port, int desired)
+{
+ unsigned int timeo;
+ int state = ibf_status(port);
+
+ for (timeo = ec_timeout; state != desired && timeo; timeo--) {
+ mdelay(1);
+ state = ibf_status(port);
+ }
+
+ if ((state == desired) && (ec_timeout > EC_BASE_TIMEOUT) &&
+ timeo < (ec_timeout - EC_BASE_TIMEOUT)) {
+ printk(KERN_WARNING "olpc-ec: waited %u ms for IBF (%d)!\n",
+ EC_BASE_TIMEOUT-timeo, line);
+ }
+
+ return !(state == desired);
+}
+
+#define wait_on_obf(p, d) __wait_on_obf(__LINE__, (p), (d))
+static int __wait_on_obf(unsigned int line, unsigned int port, int desired)
+{
+ unsigned int timeo;
+ int state = obf_status(port);
+
+ for (timeo = ec_timeout; state != desired && timeo; timeo--) {
+ mdelay(1);
+ state = obf_status(port);
+ }
+
+ if ((state == desired) && (ec_timeout > EC_BASE_TIMEOUT) &&
+ timeo < (ec_timeout - EC_BASE_TIMEOUT)) {
+ printk(KERN_WARNING "olpc-ec: waited %u ms for OBF (%d)!\n",
+ EC_BASE_TIMEOUT-timeo, line);
+ }
+
+ return !(state == desired);
+}
+
+int olpc_ec_cmd(unsigned char cmd, unsigned char *inbuf, size_t inlen,
+ unsigned char *outbuf, size_t outlen)
+{
+ unsigned long flags;
+ int ret = -EIO;
+ int i;
+
+ spin_lock_irqsave(&ec_lock, flags);
+
+ if (wait_on_ibf(0x6c, 0)) {
+ printk(KERN_ERR "olpc-ec: timeout waiting for EC to "
+ "quiesce!\n");
+ goto err;
+ }
+
+restart:
+ /*
+ * Note that if we time out during any IBF checks, that's a failure;
+ * we have to return. There's no way for the kernel to clear that.
+ *
+ * If we time out during an OBF check, we can restart the command;
+ * reissuing it will clear the OBF flag, and we should be alright.
+ * The OBF flag will sometimes misbehave due to what we believe
+ * is a hardware quirk..
+ */
+ printk(KERN_DEBUG "olpc-ec: running cmd 0x%x\n", cmd);
+ outb(cmd, 0x6c);
+
+ if (wait_on_ibf(0x6c, 0)) {
+ printk(KERN_ERR "olpc-ec: timeout waiting for EC to read "
+ "command!\n");
+ goto err;
+ }
+
+ if (inbuf && inlen) {
+ /* write data to EC */
+ for (i = 0; i < inlen; i++) {
+ if (wait_on_ibf(0x6c, 0)) {
+ printk(KERN_ERR "olpc-ec: timeout waiting for"
+ " EC accept data!\n");
+ goto err;
+ }
+ printk(KERN_DEBUG "olpc-ec: sending cmd arg 0x%x\n",
+ inbuf[i]);
+ outb(inbuf[i], 0x68);
+ }
+ }
+ if (outbuf && outlen) {
+ /* read data from EC */
+ for (i = 0; i < outlen; i++) {
+ if (wait_on_obf(0x6c, 1)) {
+ printk(KERN_ERR "olpc-ec: timeout waiting for"
+ " EC to provide data!\n");
+ goto restart;
+ }
+ outbuf[i] = inb(0x68);
+ printk(KERN_DEBUG "olpc-ec: received 0x%x\n",
+ outbuf[i]);
+ }
+ }
+
+ ret = 0;
+err:
+ spin_unlock_irqrestore(&ec_lock, flags);
+ return ret;
+}
+EXPORT_SYMBOL_GPL(olpc_ec_cmd);
+
+/*********************************************************************
+ * DCON stuff
+ *********************************************************************/
+
+static void olpc_power_off(void)
+{
+ printk(KERN_INFO "OLPC power off sequence...\n");
+ outb(0xff, 0x381);
+ outb(0x14, 0x382);
+ outb(0x01, 0x383);
+ outb(0xff, 0x381);
+ outb(0x14, 0x382);
+ outb(0x00, 0x383);
+}
+
+static void __init
+ec_detect(void)
+{
+ olpc_ec_cmd(0x08, NULL, 0, (unsigned char *) &olpc_platform_info.ecver, 1);
+}
+
+/* Check to see if this version of the OLPC board has VSA built
+ * in, and set a flag
+ */
+
+static void __init vsa_detect(void)
+{
+ u16 rev;
+
+ outw(0xFC53, 0xAC1C);
+ outw(0x0003, 0xAC1C);
+
+ rev = inw(0xAC1E);
+
+ if (rev == 0x4132)
+ olpc_platform_info.flags |= OLPC_F_VSA;
+}
+
+/* Map OFW revisions to what OLPC_REV_* */
+static const char __initdata *olpc_boardrev_str[] = {
+ "A1",
+ "preB1",
+ "B1",
+ "preB2",
+ "B2",
+ "preB3",
+ "B3",
+ "B4",
+ "C1",
+ "R1",
+};
+
+static void __init platform_detect(char *revision, size_t len)
+{
+ size_t propsize;
+ int i;
+
+ BUG_ON(ARRAY_SIZE(olpc_boardrev_str) != OLPC_REV_UNKNOWN);
+
+ if (ofw("getprop", 4, 1, NULL, "model", revision, len, &propsize)) {
+ printk(KERN_ERR "ofw: getprop call failed!\n");
+ goto failed;
+ }
+ if (len < propsize) {
+ printk(KERN_ERR "ofw: revision string is too long!\n");
+ goto failed;
+ }
+
+ for (i=0; i < ARRAY_SIZE(olpc_boardrev_str); i++) {
+ if (strcmp(revision, olpc_boardrev_str[i]) == 0) {
+ olpc_platform_info.boardrev = i;
+ return;
+ }
+ }
+
+failed:
+ strncpy(revision, "Unknown", len);
+ olpc_platform_info.boardrev = OLPC_REV_UNKNOWN;
+}
+
+static int olpc_dcon_present = -1;
+module_param(olpc_dcon_present, int, 0444);
+
+/* REV_A CMOS map:
+ * bit 440; DCON present bit
+ */
+
+#define OLPC_CMOS_DCON_OFFSET (440 / 8)
+#define OLPC_CMOS_DCON_MASK 0x01
+
+static int __init olpc_init(void)
+{
+ unsigned char *romsig;
+ char revision[10];
+
+ spin_lock_init(&ec_lock);
+
+ romsig = ioremap(0xffffffc0, 16);
+
+ if (!romsig)
+ return 0;
+
+ if (strncmp(romsig, "CL1 Q", 7))
+ goto unmap;
+ if (strncmp(romsig+6, romsig+13, 3)) {
+ printk(KERN_INFO "OLPC BIOS signature looks invalid. Assuming not OLPC\n");
+ goto unmap;
+ }
+ printk(KERN_INFO "OLPC board with OpenFirmware: %.16s\n", romsig);
+
+ olpc_platform_info.flags |= OLPC_F_PRESENT;
+
+ pm_power_off = olpc_power_off;
+
+ /* Get the platform revision */
+ platform_detect(revision, sizeof(revision));
+
+ /* If olpc_dcon_present isn't set by the command line, then
+ * "detect" it
+ */
+
+ if (olpc_dcon_present == -1) {
+ /* B1 and greater always has a DCON */
+ if (olpc_platform_info.boardrev >= OLPC_REV_B1 &&
+ olpc_platform_info.boardrev < OLPC_REV_UNKNOWN)
+ olpc_dcon_present = 1;
+ }
+
+ if (olpc_dcon_present)
+ olpc_platform_info.flags |= OLPC_F_DCON;
+
+ /* Get the EC revision */
+ ec_detect();
+
+ /* Check to see if the VSA exists */
+ vsa_detect();
+
+ printk(KERN_INFO "OLPC board revision: %s (EC=%x)\n", revision,
+ olpc_platform_info.ecver);
+
+ unmap:
+ iounmap(romsig);
+
+ return 0;
+}
+
+postcore_initcall(olpc_init);
--- /dev/null
+/*
+ * Procedures for creating, accessing and interpreting the device tree.
+ *
+ * Paul Mackerras August 1996.
+ * Copyright (C) 1996-2005 Paul Mackerras.
+ *
+ * Adapted for 64bit PowerPC by Dave Engebretsen and Peter Bergner.
+ * {engebret|bergner}@us.ibm.com
+ *
+ * Adapted for sparc64 by David S. Miller davem@davemloft.net
+ *
+ * Adapter for i386/OLPC by Andres Salomon <dilinger@debian.org>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/string.h>
+#include <linux/mm.h>
+#include <linux/bootmem.h>
+#include <linux/module.h>
+#include <asm/prom.h>
+#include <asm/ofw.h>
+
+/*
+ * XXX: This is very much a stub; right now we're keeping 2 device trees
+ * in memory (one for promfs, and one here). That will not remain
+ * for long!
+ */
+
+static struct device_node *allnodes;
+
+/* use when traversing tree through the allnext, child, sibling,
+ * or parent members of struct device_node.
+ */
+static DEFINE_RWLOCK(devtree_lock);
+
+int of_device_is_compatible(const struct device_node *device,
+ const char *compat)
+{
+ const char* cp;
+ int cplen, l;
+
+ cp = of_get_property(device, "compatible", &cplen);
+ if (cp == NULL)
+ return 0;
+ while (cplen > 0) {
+ if (strncmp(cp, compat, strlen(compat)) == 0)
+ return 1;
+ l = strlen(cp) + 1;
+ cp += l;
+ cplen -= l;
+ }
+
+ return 0;
+}
+EXPORT_SYMBOL(of_device_is_compatible);
+
+struct device_node *of_get_parent(const struct device_node *node)
+{
+ struct device_node *np;
+
+ if (!node)
+ return NULL;
+
+ np = node->parent;
+
+ return np;
+}
+EXPORT_SYMBOL(of_get_parent);
+
+struct device_node *of_get_next_child(const struct device_node *node,
+ struct device_node *prev)
+{
+ struct device_node *next;
+
+ next = prev ? prev->sibling : node->child;
+ for (; next != 0; next = next->sibling) {
+ break;
+ }
+
+ return next;
+}
+EXPORT_SYMBOL(of_get_next_child);
+
+struct device_node *of_find_node_by_path(const char *path)
+{
+ struct device_node *np = allnodes;
+
+ for (; np != 0; np = np->allnext) {
+ if (np->full_name != 0 && strcmp(np->full_name, path) == 0)
+ break;
+ }
+
+ return np;
+}
+EXPORT_SYMBOL(of_find_node_by_path);
+
+struct device_node *of_find_node_by_phandle(phandle handle)
+{
+ struct device_node *np;
+
+ for (np = allnodes; np != 0; np = np->allnext)
+ if (np->node == handle)
+ break;
+
+ return np;
+}
+EXPORT_SYMBOL(of_find_node_by_phandle);
+
+struct device_node *of_find_node_by_name(struct device_node *from,
+ const char *name)
+{
+ struct device_node *np;
+
+ np = from ? from->allnext : allnodes;
+ for (; np != NULL; np = np->allnext)
+ if (np->name != NULL && strcmp(np->name, name) == 0)
+ break;
+
+ return np;
+}
+EXPORT_SYMBOL(of_find_node_by_name);
+
+struct device_node *of_find_node_by_type(struct device_node *from,
+ const char *type)
+{
+ struct device_node *np;
+
+ np = from ? from->allnext : allnodes;
+ for (; np != 0; np = np->allnext)
+ if (np->type != 0 && strcmp(np->type, type) == 0)
+ break;
+
+ return np;
+}
+EXPORT_SYMBOL(of_find_node_by_type);
+
+struct device_node *of_find_compatible_node(struct device_node *from,
+ const char *type, const char *compatible)
+{
+ struct device_node *np;
+
+ np = from ? from->allnext : allnodes;
+ for (; np != 0; np = np->allnext) {
+ if (type != NULL
+ && !(np->type != 0 && strcmp(np->type, type) == 0))
+ continue;
+ if (of_device_is_compatible(np, compatible))
+ break;
+ }
+
+ return np;
+}
+EXPORT_SYMBOL(of_find_compatible_node);
+
+struct property *of_find_property(const struct device_node *np,
+ const char *name,
+ int *lenp)
+{
+ struct property *pp;
+
+ for (pp = np->properties; pp != 0; pp = pp->next) {
+ if (strcasecmp(pp->name, name) == 0) {
+ if (lenp != 0)
+ *lenp = pp->length;
+ break;
+ }
+ }
+ return pp;
+}
+EXPORT_SYMBOL(of_find_property);
+
+/*
+ * Find a property with a given name for a given node
+ * and return the value.
+ */
+const void *of_get_property(const struct device_node *np, const char *name,
+ int *lenp)
+{
+ struct property *pp = of_find_property(np,name,lenp);
+ return pp ? pp->value : NULL;
+}
+EXPORT_SYMBOL(of_get_property);
+
+int of_getintprop_default(struct device_node *np, const char *name, int def)
+{
+ struct property *prop;
+ int len;
+
+ prop = of_find_property(np, name, &len);
+ if (!prop || len != 4)
+ return def;
+
+ return *(int *) prop->value;
+}
+EXPORT_SYMBOL(of_getintprop_default);
+
+int of_n_addr_cells(struct device_node *np)
+{
+ const int* ip;
+ do {
+ if (np->parent)
+ np = np->parent;
+ ip = of_get_property(np, "#address-cells", NULL);
+ if (ip != NULL)
+ return *ip;
+ } while (np->parent);
+ /* No #address-cells property for the root node, default to 2 */
+ return 2;
+}
+EXPORT_SYMBOL(of_n_addr_cells);
+
+int of_n_size_cells(struct device_node *np)
+{
+ const int* ip;
+ do {
+ if (np->parent)
+ np = np->parent;
+ ip = of_get_property(np, "#size-cells", NULL);
+ if (ip != NULL)
+ return *ip;
+ } while (np->parent);
+ /* No #size-cells property for the root node, default to 1 */
+ return 1;
+}
+EXPORT_SYMBOL(of_n_size_cells);
+
+int of_set_property(struct device_node *dp, const char *name, void *val, int len)
+{
+ return -EIO;
+}
+EXPORT_SYMBOL(of_set_property);
+
+static unsigned int prom_early_allocated;
+
+static void * __init prom_early_alloc(unsigned long size)
+{
+ void *ret;
+
+ ret = kmalloc(size, GFP_KERNEL);
+ if (ret != NULL)
+ memset(ret, 0, size);
+ else
+ printk(KERN_ERR "ACK! couldn't allocate prom memory!\n");
+
+ prom_early_allocated += size;
+
+ return ret;
+}
+
+static int is_root_node(const struct device_node *dp)
+{
+ if (!dp)
+ return 0;
+
+ return (dp->parent == NULL);
+}
+
+static char * __init build_path_component(struct device_node *dp)
+{
+ int pathlen;
+ char *n, *i;
+
+ if (ofw("package-to-path", 3, 1, dp->node, NULL, 0, &pathlen)) {
+ printk(KERN_ERR "PROM: unable to get path name from OFW!\n");
+ return "ERROR";
+ }
+ n = prom_early_alloc(pathlen + 1);
+ if (ofw("package-to-path", 3, 1, dp->node, n, pathlen+1, &pathlen))
+ printk(KERN_ERR "PROM: unable to get path name from OFW\n");
+
+ if ((i = strrchr(n, '/')))
+ n = ++i; /* we only want the file name */
+ return n;
+}
+
+static char * __init build_full_name(struct device_node *dp)
+{
+ int len, ourlen, plen;
+ char *n;
+
+ plen = strlen(dp->parent->full_name);
+ ourlen = strlen(dp->path_component_name);
+ len = ourlen + plen + 2;
+
+ n = prom_early_alloc(len);
+ strcpy(n, dp->parent->full_name);
+ if (!is_root_node(dp->parent)) {
+ strcpy(n + plen, "/");
+ plen++;
+ }
+ strcpy(n + plen, dp->path_component_name);
+
+ return n;
+}
+
+static struct property * __init build_one_prop(phandle node, char *prev, char *special_name, void *special_val, int special_len)
+{
+ static struct property *tmp = NULL;
+ struct property *p;
+
+ if (tmp) {
+ p = tmp;
+ memset(p, 0, sizeof(*p) + 32);
+ tmp = NULL;
+ } else {
+ p = prom_early_alloc(sizeof(struct property) + 32);
+ }
+
+ p->name = (char *) (p + 1);
+ if (special_name) {
+ strcpy(p->name, special_name);
+ p->length = special_len;
+ p->value = prom_early_alloc(special_len);
+ memcpy(p->value, special_val, special_len);
+ } else {
+ int fl;
+ if (prev == NULL) {
+ if (ofw("nextprop", 3, 1, node, "", p->name, &fl)) {
+ printk(KERN_ERR "PROM: %s: nextprop failed!\n", __func__);
+ return NULL;
+ }
+ } else {
+ if (ofw("nextprop", 3, 1, node, prev, p->name, &fl)) {
+ printk(KERN_ERR "PROM: %s: nextprop failed!\n", __func__);
+ return NULL;
+ }
+ }
+ if (strlen(p->name) == 0 || fl != 1) {
+ tmp = p;
+ return NULL;
+ }
+ if (ofw("getproplen", 2, 1, node, p->name, &p->length)) {
+ printk(KERN_ERR "PROM: %s: getproplen failed!\n", __func__);
+ return NULL;
+ }
+ if (p->length <= 0) {
+ p->length = 0;
+ } else {
+ p->value = prom_early_alloc(p->length + 1);
+ if (ofw("getprop", 4, 1, node, p->name, p->value, p->length, &p->length)) {
+ printk(KERN_ERR "PROM: %s: getprop failed!\n", __func__);
+ return NULL;
+ }
+ ((unsigned char *)p->value)[p->length] = '\0';
+ }
+ }
+ return p;
+}
+
+static struct property * __init build_prop_list(phandle node)
+{
+ struct property *head, *tail;
+
+ head = tail = build_one_prop(node, NULL,
+ ".node", &node, sizeof(node));
+
+ tail->next = build_one_prop(node, NULL, NULL, NULL, 0);
+ tail = tail->next;
+ while(tail) {
+ tail->next = build_one_prop(node, tail->name,
+ NULL, NULL, 0);
+ tail = tail->next;
+ }
+
+ return head;
+}
+
+static char * __init get_one_property(phandle node, const char *name)
+{
+ char *buf = "<NULL>";
+ int len;
+
+ if (ofw("getproplen", 2, 1, node, name, &len)) {
+ printk(KERN_ERR "PROM: %s: getproplen failed!\n", __func__);
+ return NULL;
+ }
+ if (len > 0) {
+ buf = prom_early_alloc(len);
+ if (ofw("getprop", 4, 1, node, name, buf, len, &len)) {
+ printk(KERN_ERR "PROM: %s: getprop failed!\n", __func__);
+ return NULL;
+ }
+ }
+
+ return buf;
+}
+
+static struct device_node * __init create_node(phandle node, struct device_node *parent)
+{
+ struct device_node *dp;
+
+ if (!node)
+ return NULL;
+
+ dp = prom_early_alloc(sizeof(*dp));
+ dp->parent = parent;
+
+ kref_init(&dp->kref);
+
+ dp->name = get_one_property(node, "name");
+ dp->type = get_one_property(node, "device_type");
+ dp->node = node;
+
+ dp->properties = build_prop_list(node);
+
+ return dp;
+}
+
+static struct device_node * __init build_tree(struct device_node *parent, phandle node, struct device_node ***nextp)
+{
+ struct device_node *ret = NULL, *prev_sibling = NULL;
+ struct device_node *dp;
+ u32 child;
+
+ while (1) {
+ dp = create_node(node, parent);
+ if (!dp)
+ break;
+
+ if (prev_sibling)
+ prev_sibling->sibling = dp;
+
+ if (!ret)
+ ret = dp;
+ prev_sibling = dp;
+
+ *(*nextp) = dp;
+ *nextp = &dp->allnext;
+
+ dp->path_component_name = build_path_component(dp);
+ dp->full_name = build_full_name(dp);
+
+ if (ofw("child", 1, 1, node, &child)) {
+ printk(KERN_ERR "PROM: %s: fetching child failed!\n", __func__);
+ return NULL;
+ }
+ dp->child = build_tree(dp, child, nextp);
+
+ if (ofw("peer", 1, 1, node, &node)) {
+ printk(KERN_ERR "PROM: %s: fetching peer failed!\n", __func__);
+ return NULL;
+ }
+ }
+
+ return ret;
+}
+
+static phandle root_node;
+
+void __init prom_build_devicetree(void)
+{
+ struct device_node **nextp;
+ u32 child;
+
+ if (ofw("peer", 1, 1, 0, &root_node)) {
+ printk(KERN_ERR "PROM: unable to get root node from OFW!\n");
+ return;
+ }
+
+ allnodes = create_node(root_node, NULL);
+ allnodes->path_component_name = "";
+ allnodes->full_name = "/";
+
+ nextp = &allnodes->allnext;
+ if (ofw("child", 1, 1, allnodes->node, &child)) {
+ printk(KERN_ERR "PROM: unable to get child node from OFW!\n");
+ return;
+ }
+ allnodes->child = build_tree(allnodes, child, &nextp);
+ printk("PROM: Built device tree with %u bytes of memory.\n",
+ prom_early_allocated);
+}
--- /dev/null
+/*
+ * olpcpci.c - Low-level PCI config space access for OLPC systems
+ * without the VSA PCI virtualization software.
+ *
+ * The AMD Geode chipset (GX2 processor, cs5536 I/O companion device)
+ * has some I/O functions (display, southbridge, sound, USB HCIs, etc)
+ * that more or less behave like PCI devices, but the hardware doesn't
+ * directly implement the PCI configuration space headers. AMD provides
+ * "VSA" (Virtual System Architecture) software that emulates PCI config
+ * space for these devices, by trapping I/O accesses to PCI config register
+ * (CF8/CFC) and running some code in System Management Mode interrupt state.
+ * On the OLPC platform, we don't want to use that VSA code because
+ * (a) it slows down suspend/resume, and (b) recompiling it requires special
+ * compilers that are hard to get. So instead of letting the complex VSA
+ * code simulate the PCI config registers for the on-chip devices, we
+ * just simulate them the easy way, by inserting the code into the
+ * pci_write_config and pci_read_config path. Most of the config registers
+ * are read-only anyway, so the bulk of the simulation is just table lookup.
+ */
+
+#include <linux/pci.h>
+#include <linux/init.h>
+#include <asm/olpc.h>
+#include <asm/geode.h>
+#include "pci.h"
+
+static int is_lx;
+
+/*
+ * In the tables below, the first two line (8 longwords) are the
+ * size masks that are used when the higher level PCI code determines
+ * the size of the region by writing ~0 to a base address register
+ * and reading back the result.
+ *
+ * The following lines are the values that are read during normal
+ * PCI config access cycles, i.e. not after just having written
+ * ~0 to a base address register.
+ */
+
+static const u32 lxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+
+ 0x281022 , 0x2200005 , 0x6000021 , 0x80f808 , /* AMD Vendor ID */
+ 0x0 , 0x0 , 0x0 , 0x0 , /* No virtual registers, hence no BAR for them */
+ 0x0 , 0x0 , 0x0 , 0x28100b ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+};
+
+static const u32 gxnb_hdr[] = { /* dev 1 function 0 - devfn = 8 */
+ 0xfffffffd , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+
+ 0x28100b , 0x2200005 , 0x6000021 , 0x80f808 , /* NSC Vendor ID */
+ 0xac1d , 0x0 , 0x0 , 0x0 , /* I/O BAR - base of virtual registers */
+ 0x0 , 0x0 , 0x0 , 0x28100b ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+};
+
+static const u32 lxfb_hdr[] = { /* dev 1 function 1 - devfn = 9 */
+ 0xff800008 , 0xffffc000 , 0xffffc000 , 0xffffc000 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+
+ 0x20811022 , 0x2200003 , 0x3000000 , 0x0 , /* AMD Vendor ID */
+ 0xfd000000 , 0xfe000000 , 0xfe004000 , 0xfe008000 , /* FB, GP, VG, DF */
+ 0xfe00c000 , 0x0 , 0x0 , 0x30100b , /* VIP */
+ 0x0 , 0x0 , 0x0 , 0x10e , /* INTA, IRQ14 for graphics accel */
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x3d0 , 0x3c0 , 0xa0000 , 0x0 , /* VG IO, VG IO, EGA FB, MONO FB */
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+};
+
+static const u32 gxfb_hdr[] = { /* dev 1 function 1 - devfn = 9 */
+ 0xff800008 , 0xffffc000 , 0xffffc000 , 0xffffc000 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+
+ 0x30100b , 0x2200003 , 0x3000000 , 0x0 , /* NSC Vendor ID */
+ 0xfd000000 , 0xfe000000 , 0xfe004000 , 0xfe008000 , /* FB, GP, VG, DF */
+ 0x0 , 0x0 , 0x0 , 0x30100b ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x3d0 , 0x3c0 , 0xa0000 , 0x0 , /* VG IO, VG IO, EGA FB, MONO FB */
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+};
+
+static const u32 aes_hdr[] = { /* dev 1 function 2 - devfn = 0xa */
+ 0xffffc000 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+
+ 0x20821022 , 0x2a00006 , 0x10100000 , 0x8 , /* NSC Vendor ID */
+ 0xfe010000 , 0x0 , 0x0 , 0x0 , /* AES registers */
+ 0x0 , 0x0 , 0x0 , 0x20821022 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+};
+
+
+static const u32 isa_hdr[] = { /* dev f function 0 - devfn = 78 */
+ 0xfffffff9 , 0xffffff01 , 0xffffffc1 , 0xffffffe1 ,
+ 0xffffff81 , 0xffffffc1 , 0x0 , 0x0 ,
+
+ 0x20901022 , 0x2a00049 , 0x6010003 , 0x802000 ,
+ 0x18b1 , 0x1001 , 0x1801 , 0x1881 , /* SMB-8 GPIO-256 MFGPT-64 IRQ-32 */
+ 0x1401 , 0x1841 , 0x0 , 0x20901022 , /* PMS-128 ACPI-64 */
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0xaa5b , /* interrupt steering */
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+};
+
+static const u32 ac97_hdr[] = { /* dev f function 3 - devfn = 7b */
+ 0xffffff81 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+
+ 0x20931022 , 0x2a00041 , 0x4010001 , 0x0 ,
+ 0x1481 , 0x0 , 0x0 , 0x0 , /* I/O BAR-128 */
+ 0x0 , 0x0 , 0x0 , 0x20931022 ,
+ 0x0 , 0x0 , 0x0 , 0x205 , /* IntB , IRQ5 */
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+};
+
+static const u32 ohci_hdr[] = { /* dev f function 4 - devfn = 7c */
+ 0xfffff000 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+
+ 0x20941022 , 0x2300006 , 0xc031002 , 0x0 ,
+ 0xfe01a000 , 0x0 , 0x0 , 0x0 , /* MEMBAR-1000 */
+ 0x0 , 0x0 , 0x0 , 0x20941022 ,
+ 0x0 , 0x40 , 0x0 , 0x40a , /* CapPtr INT-D, IRQ A */
+ 0xc8020001 , 0x0 , 0x0 , 0x0 , /* Capabilities - 40 is R/O, 44 is mask 8103 (power control) */
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+};
+
+static const u32 ehci_hdr[] = { /* dev f function 4 - devfn = 7d */
+ 0xfffff000 , 0x0 , 0x0 , 0x0 ,
+ 0x0 , 0x0 , 0x0 , 0x0 ,
+
+ 0x20951022 , 0x2300006 , 0xc032002 , 0x0 ,
+ 0xfe01b000 , 0x0 , 0x0 , 0x0 , /* MEMBAR-1000 */
+ 0x0 , 0x0 , 0x0 , 0x20951022 ,
+ 0x0 , 0x40 , 0x0 , 0x40a , /* CapPtr INT-D, IRQ A */
+ 0xc8020001 , 0x0 , 0x0 , 0x0 , /* Capabilities - 40 is R/O, 44 is mask 8103 (power control) */
+#if 0
+ 0x1 , 0x40080000 , 0x0 , 0x0 , /* EECP - see section 2.1.7 of EHCI spec */
+#endif
+ 0x01000001 , 0x00000000 , 0x0 , 0x0 , /* EECP - see section 2.1.7 of EHCI spec */
+ 0x2020 , 0x0 , 0x0 , 0x0 , /* (EHCI page 8) 60 SBRN (R/O), 61 FLADJ (R/W), PORTWAKECAP */
+};
+
+static u32 ff_loc = ~0;
+static u32 zero_loc = 0;
+
+static int bar_probing = 0; /* Set after a write of ~0 to a BAR */
+
+#define NB_SLOT 0x1 /* Northbridge - GX chip - Device 1 */
+#define SB_SLOT 0xf /* Southbridge - CS5536 chip - Device F */
+#define SIMULATED(bus, devfn) (((bus) == 0) && ((PCI_SLOT(devfn) == NB_SLOT) || (PCI_SLOT(devfn) == SB_SLOT)))
+
+static u32 *hdr_addr(const u32 *hdr, int reg)
+{
+ u32 addr;
+
+ /*
+ * This is a little bit tricky. The header maps consist of
+ * 0x20 bytes of size masks, followed by 0x70 bytes of header data.
+ * In the normal case, when not probing a BAR's size, we want
+ * to access the header data, so we add 0x20 to the reg offset,
+ * thus skipping the size mask area.
+ * In the BAR probing case, we want to access the size mask for
+ * the BAR, so we subtract 0x10 (the config header offset for
+ * BAR0), and don't skip the size mask area.
+ */
+
+ addr = (u32)hdr + reg + (bar_probing ? -0x10 : 0x20);
+
+ bar_probing = 0;
+ return (u32 *)addr;
+}
+
+static int pci_olpc_read(unsigned int seg, unsigned int bus,
+ unsigned int devfn, int reg, int len, u32 *value)
+{
+ u32 *addr;
+
+ /* Use the hardware mechanism for non-simulated devices */
+ if (!SIMULATED(bus, devfn))
+ return pci_conf1_read(seg, bus, devfn, reg, len, value);
+
+ /*
+ * No device has config registers past 0x70, so we save table space
+ * by not storing entries for the nonexistent registers
+ */
+ if (reg >= 0x70)
+ addr = &zero_loc;
+ else {
+ switch (devfn) {
+ case 0x8:
+ addr = hdr_addr(is_lx ? lxnb_hdr : gxnb_hdr, reg);
+ break;
+ case 0x9:
+ addr = hdr_addr(is_lx ? lxfb_hdr : gxfb_hdr, reg);
+ break;
+ case 0xa:
+ addr = is_lx ? hdr_addr(aes_hdr, reg) : &ff_loc;
+ break;
+ case 0x78:
+ addr = hdr_addr(isa_hdr, reg);
+ break;
+ case 0x7b:
+ addr = hdr_addr(ac97_hdr, reg);
+ break;
+ case 0x7c:
+ addr = hdr_addr(ohci_hdr, reg);
+ break;
+ case 0x7d:
+ addr = hdr_addr(ehci_hdr, reg);
+ break;
+ default:
+ addr = &ff_loc;
+ break;
+ }
+ }
+ switch (len) {
+ case 1:
+ *value = *(u8 *) addr;
+ break;
+ case 2:
+ *value = *(u16 *) addr;
+ break;
+ case 4:
+ *value = *addr;
+ break;
+ default:
+ BUG();
+ }
+
+ return 0;
+}
+
+static int pci_olpc_write(unsigned int seg, unsigned int bus,
+ unsigned int devfn, int reg, int len, u32 value)
+{
+ /* Use the hardware mechanism for non-simulated devices */
+ if (!SIMULATED(bus, devfn))
+ return pci_conf1_write(seg, bus, devfn, reg, len, value);
+
+ /* XXX we may want to extend this to simulate EHCI power management */
+
+ /*
+ * Mostly we just discard writes, but if the write is a size probe
+ * (i.e. writing ~0 to a BAR), we remember it and arrange to return
+ * the appropriate size mask on the next read. This is cheating
+ * to some extent, because it depends on the fact that the next
+ * access after such a write will always be a read to the same BAR.
+ */
+
+ if ((reg >= 0x10) && (reg < 0x2c)) {
+ /* Write is to a BAR */
+ if (value == ~0)
+ bar_probing = 1;
+ } else {
+ /*
+ * No warning on writes to ROM BAR, CMD, LATENCY_TIMER,
+ * CACHE_LINE_SIZE, or PM registers.
+ */
+ if ((reg != 0x30) && (reg != 0x04) && (reg != 0x0d) &&
+ (reg != 0x0c) && (reg != 0x44))
+ printk(KERN_WARNING "OLPC PCI: Config write to devfn %x reg %x value %x\n", devfn, reg, value);
+ }
+
+ return 0;
+}
+
+static struct pci_raw_ops pci_olpc_conf = {
+ .read = pci_olpc_read,
+ .write = pci_olpc_write,
+};
+
+void __init pci_olpc_init(void)
+{
+ if (!machine_is_olpc() || olpc_has_vsa())
+ return;
+
+ printk(KERN_INFO "PCI: Using configuration type OLPC\n");
+ raw_pci_ops = &pci_olpc_conf;
+ is_lx = is_geode_lx();
+}
--- /dev/null
+/*
+ * OLPC touchpad PS/2 mouse driver
+ *
+ * Copyright (c) 2006 One Laptop Per Child, inc.
+ * Authors Zephaniah E. Hull and Andres Salomon <dilinger@laptop.org>
+ *
+ * This driver is partly based on the ALPS driver, which is:
+ *
+ * Copyright (c) 2003 Neil Brown <neilb@cse.unsw.edu.au>
+ * Copyright (c) 2003-2005 Peter Osterlund <petero2@telia.com>
+ * Copyright (c) 2004 Dmitry Torokhov <dtor@mail.ru>
+ * Copyright (c) 2005 Vojtech Pavlik <vojtech@suse.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+/*
+ * The touchpad on the OLPC is fairly wide, with the entire area usable
+ * as a tablet ("PT mode"), and the center 1/3rd also usable as a touchpad
+ * ("GS mode").
+ *
+ * Earlier version of the device had simultaneous reporting; however, that
+ * was removed. Instead, the device now reports packets in one mode, and
+ * tells the driver when a mode switch needs to happen.
+ */
+
+#include <linux/input.h>
+#include <linux/serio.h>
+#include <linux/libps2.h>
+#include <linux/delay.h>
+#include <asm/olpc.h>
+
+#include "psmouse.h"
+#include "olpc.h"
+
+static int tpdebug;
+module_param(tpdebug, int, 0644);
+
+#define OLPC_GS 1 /* The GS sensor. */
+#define OLPC_PT 2 /* The PT sensor. */
+
+static struct olpc_model_info olpc_model_data[] = {
+ { { 0x67, 0x00, 0x00 }, OLPC_GS | OLPC_PT }, /* unknown ID */
+ { { 0x67, 0x00, 0x0a }, OLPC_GS | OLPC_PT }, /* pre-B1 */
+ { { 0x67, 0x00, 0x14 }, OLPC_GS }, /* B1.*/
+ { { 0x67, 0x00, 0x28 }, OLPC_GS | OLPC_PT }, /* B2 */
+ { { 0x67, 0x00, 0x3c }, OLPC_GS | OLPC_PT }, /* B2-2 */
+ { { 0x67, 0x00, 0x50 }, OLPC_GS | OLPC_PT }, /* C1 */
+};
+
+#define OLPC_PKT_PT 0xcf
+#define OLPC_PKT_GS 0xff
+
+static int olpc_absolute_mode(struct psmouse *psmouse, int mode);
+
+/*
+ * OLPC absolute Mode - single-mode format
+ *
+ * byte 0: 1 1 0 0 1 1 1 1
+ * byte 1: 0 x6 x5 x4 x3 x2 x1 x0
+ * byte 2(PT): 0 0 x9 x8 x7 ? pt-dsw gs-dsw
+ * byte 2(GS): 0 x10 x9 x8 x7 ? gs-dsw pt-dsw
+ * byte 3: 0 y9 y8 y7 1 0 swr swl
+ * byte 4: 0 y6 y5 y4 y3 y2 y1 y0
+ * byte 5: 0 z6 z5 z4 z3 z2 z1 z0
+ *
+ * ?'s are not defined in the protocol spec, may vary between models.
+ *
+ * swr/swl are the left/right buttons.
+ *
+ * pt-dsw/gs-dsw indicate that the pt/gs sensor is detecting a
+ * pen/finger
+ */
+
+static void olpc_process_packet_gspt(struct psmouse *psmouse)
+{
+ struct olpc_data *priv = psmouse->private;
+ unsigned char *packet = psmouse->packet;
+ struct input_dev *dev = psmouse->dev;
+ struct input_dev *dev2 = priv->dev2;
+ int x, y, z, gs_down = 0, pt_down = 0, left, right;
+ struct timeval now_tv;
+ s64 now_ns;
+
+ left = packet[3] & 1;
+ right = packet[3] & 2;
+ x = packet[1] | ((packet[2] & 0x78) << 4);
+ y = packet[4] | ((packet[3] & 0x70) << 3);
+ z = packet[5];
+
+ if (psmouse->packet[0] == OLPC_PKT_GS) {
+ pt_down = !!(packet[2] & 1);
+ gs_down = !!(packet[2] & 2);
+ } else if (psmouse->packet[0] == OLPC_PKT_PT) {
+ gs_down = !!(packet[2] & 1);
+ pt_down = !!(packet[2] & 2);
+ }
+
+ /*
+ * XXX: Kludge.
+ * If it's been more than 30ms since the last packet,
+ * assume that there was a lift we were never told about.
+ */
+ do_gettimeofday(&now_tv);
+ now_ns = timeval_to_ns (&now_tv);
+ if (now_ns >= priv->late) {
+ input_report_key(dev, BTN_TOUCH, 0);
+ input_report_key(dev, BTN_TOOL_PEN, 0);
+ input_report_key(dev2, BTN_TOUCH, 0);
+ input_report_key(dev2, BTN_TOOL_FINGER, 0);
+
+ input_sync(dev);
+ input_sync(dev2);
+ }
+
+ priv->late = now_ns + (30 * NSEC_PER_MSEC);
+
+
+ if (tpdebug) {
+ printk(KERN_DEBUG "%s %02x %02x %02x %02x %02x %02x\n",
+ __FUNCTION__, psmouse->packet[0], psmouse->packet[1],
+ psmouse->packet[2], psmouse->packet[3], psmouse->packet[4],
+ psmouse->packet[5]);
+ printk(KERN_DEBUG "l=%d r=%d p=%d g=%d x=%d y=%d z=%d\n",
+ left, right, pt_down, gs_down, x, y, z);
+ }
+
+ if (psmouse->packet[0] == OLPC_PKT_PT) {
+ input_report_key(dev, BTN_LEFT, left);
+ input_report_key(dev, BTN_RIGHT, right);
+ } else if (psmouse->packet[0] == OLPC_PKT_GS) {
+ input_report_key(dev, BTN_LEFT, left);
+ input_report_key(dev, BTN_RIGHT, right);
+ input_report_key(dev2, BTN_LEFT, left);
+ input_report_key(dev2, BTN_RIGHT, right);
+ }
+
+ input_report_key(dev, BTN_TOUCH, pt_down);
+ input_report_key(dev, BTN_TOOL_PEN, pt_down);
+ input_report_key(dev2, BTN_TOUCH, gs_down);
+ input_report_key(dev2, BTN_TOOL_FINGER, gs_down);
+
+ input_report_abs(dev2, ABS_PRESSURE, z);
+
+ if (psmouse->packet[0] == OLPC_PKT_PT && pt_down) {
+ input_report_abs(dev, ABS_X, x);
+ input_report_abs(dev, ABS_Y, y);
+ } else if (psmouse->packet[0] == OLPC_PKT_GS && gs_down) {
+ input_report_abs(dev2, ABS_X, x);
+ input_report_abs(dev2, ABS_Y, y);
+ }
+
+ input_sync(dev);
+ input_sync(dev2);
+
+ if (priv->pending_mode == OLPC_GS &&
+ psmouse->packet[0] == OLPC_PKT_PT && pt_down) {
+ priv->pending_mode = 0;
+ cancel_delayed_work(&priv->mode_switch);
+ }
+
+ if (priv->i->flags & (OLPC_PT|OLPC_GS)) {
+ int pending = 0;
+ if (psmouse->packet[0] == OLPC_PKT_PT && !pt_down)
+ pending = OLPC_GS;
+ else if (psmouse->packet[0] == OLPC_PKT_GS && pt_down)
+ pending = OLPC_PT;
+
+ if (priv->current_mode == pending) {
+ priv->pending_mode = 0;
+ pending = priv->current_mode;
+ }
+ else if (priv->pending_mode != pending) {
+ priv->pending_mode = pending;
+ if (tpdebug)
+ printk(KERN_WARNING "Scheduling mode switch to %s.\n",
+ pending == OLPC_GS ? "GS" : "PT");
+
+ /*
+ * Apply a de-bounce when switching from PT to GS, to allow for
+ * spurious PT-up packets.
+ */
+ if (priv->pending_mode == OLPC_GS)
+ queue_delayed_work(kpsmoused_wq, &priv->mode_switch, msecs_to_jiffies(50));
+ else
+ queue_delayed_work(kpsmoused_wq, &priv->mode_switch, 0);
+ }
+ }
+}
+
+static psmouse_ret_t olpc_process_byte(struct psmouse *psmouse)
+{
+ psmouse_ret_t ret = PSMOUSE_BAD_DATA;
+
+ if (psmouse->packet[0] != OLPC_PKT_PT &&
+ psmouse->packet[0] != OLPC_PKT_GS)
+ goto out;
+
+ /* Bytes 2 - 6 should have 0 in the highest bit */
+ if (psmouse->pktcnt >= 2 && psmouse->pktcnt <= 6 &&
+ (psmouse->packet[psmouse->pktcnt - 1] & 0x80))
+ goto out;
+
+ if (psmouse->pktcnt == 6) {
+ olpc_process_packet_gspt(psmouse);
+ ret = PSMOUSE_FULL_PACKET;
+ goto out;
+ }
+
+ ret = PSMOUSE_GOOD_DATA;
+out:
+ if (ret != PSMOUSE_GOOD_DATA && ret != PSMOUSE_FULL_PACKET)
+ printk(KERN_DEBUG "%s: (%d) %02x %02x %02x %02x %02x %02x\n",
+ __FUNCTION__, psmouse->pktcnt, psmouse->packet[0],
+ psmouse->packet[1], psmouse->packet[2],
+ psmouse->packet[3], psmouse->packet[4],
+ psmouse->packet[5]);
+ return ret;
+}
+
+static struct olpc_model_info *olpc_get_model(struct psmouse *psmouse)
+{
+ struct ps2dev *ps2dev = &psmouse->ps2dev;
+ unsigned char param[4];
+ int i;
+
+ /*
+ * Now try "E7 report". Allowed responses are in
+ * olpc_model_data[].signature
+ */
+ if (ps2_command(ps2dev, NULL, PSMOUSE_CMD_SETSCALE21) ||
+ ps2_command(ps2dev, NULL, PSMOUSE_CMD_SETSCALE21) ||
+ ps2_command(ps2dev, NULL, PSMOUSE_CMD_SETSCALE21))
+ return NULL;
+
+ param[0] = param[1] = param[2] = 0xff;
+ if (ps2_command(ps2dev, param, PSMOUSE_CMD_GETINFO))
+ return NULL;
+
+ pr_debug("olpc.c(%d): E7 report: %2.2x %2.2x %2.2x",
+ __LINE__, param[0], param[1], param[2]);
+
+ for (i = 0; i < ARRAY_SIZE(olpc_model_data); i++) {
+ if (!memcmp(param, olpc_model_data[i].signature,
+ sizeof(olpc_model_data[i].signature))) {
+ printk(KERN_INFO __FILE__ ": OLPC touchpad revision 0x%x.\n", param[2]);
+ return olpc_model_data + i;
+ }
+ }
+
+ /*
+ * ALPS creates new IDs pretty frequently; rather than listing them
+ * all, just assume they support the defaults. We've set aside the
+ * first entry of olpc_model_data as the catch-all.
+ */
+ if (!memcmp(param, olpc_model_data[0].signature, 2)) {
+ printk(KERN_INFO __FILE__ ": unknown ALPS revision %x, assuming default flags.\n", param[2]);
+ return &olpc_model_data[0];
+ }
+
+ return NULL;
+}
+
+static int olpc_find_mode(struct psmouse *psmouse)
+{
+ struct olpc_data *priv = psmouse->private;
+ int mode = priv->i->flags;
+
+ if (mode & OLPC_GS)
+ mode = OLPC_GS;
+ else if (mode & OLPC_PT)
+ mode = OLPC_PT;
+ else
+ mode = -1;
+
+ return mode;
+}
+
+/*
+ * Touchpad should be disabled before calling this!
+ */
+static int olpc_new_mode(struct psmouse *psmouse, int mode)
+{
+ struct ps2dev *ps2dev = &psmouse->ps2dev;
+ struct olpc_data *priv = psmouse->private;
+ unsigned char param;
+ int ret;
+
+ if (tpdebug)
+ printk(KERN_WARNING __FILE__ ": Switching to %d. [%lu]\n", mode, jiffies);
+
+ if ((ret = ps2_command(ps2dev, ¶m, 0x01F2)))
+ goto failed;
+ if ((ret = ps2_command(ps2dev, ¶m, 0x01F2)))
+ goto failed;
+ if ((ret = ps2_command(ps2dev, ¶m, 0x01F2)))
+ goto failed;
+
+ switch (mode) {
+ default:
+ printk(KERN_WARNING __FILE__ ": Invalid mode %d. Defaulting to OLPC_GS.\n", mode);
+ case OLPC_GS:
+ ret = ps2_command(ps2dev, NULL, 0xE6);
+ break;
+ case OLPC_PT:
+ ret = ps2_command(ps2dev, NULL, 0xE7);
+ break;
+ }
+ if (ret)
+ goto failed;
+
+ /* XXX: This is a bit hacky, make sure this isn't screwing stuff up. */
+ psmouse->pktcnt = psmouse->out_of_sync = 0;
+ psmouse->last = jiffies;
+ psmouse->state = PSMOUSE_ACTIVATED;
+
+ if ((ret = ps2_command(ps2dev, NULL, PSMOUSE_CMD_ENABLE)))
+ goto failed;
+
+ priv->current_mode = mode;
+ priv->pending_mode = 0;
+ if (tpdebug)
+ printk(KERN_WARNING __FILE__ ": Switched to mode %d successful.\n", mode);
+
+failed:
+ if (ret)
+ printk(KERN_WARNING __FILE__ ": Mode switch to %d failed! (%d) [%lu]\n", mode, ret, jiffies);
+ return ret;
+}
+
+static int olpc_absolute_mode(struct psmouse *psmouse, int mode)
+{
+ struct ps2dev *ps2dev = &psmouse->ps2dev;
+
+ /* Switch to 'Advanced mode.', four disables in a row. */
+ if (ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE) ||
+ ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE) ||
+ ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE) ||
+ ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE))
+ return -1;
+
+ return olpc_new_mode(psmouse, mode);
+}
+
+/*
+ * olpc_poll() - poll the touchpad for current motion packet.
+ * Used in resync.
+ * Note: We can't poll, so always return failure.
+ */
+static int olpc_poll(struct psmouse *psmouse)
+{
+ return -1;
+}
+
+static int olpc_reconnect(struct psmouse *psmouse)
+{
+ struct olpc_data *priv = psmouse->private;
+ int mode;
+
+ if (olpc_rev_after(OLPC_REV_B2))
+ if (psmouse->ps2dev.serio->dev.power.power_state.event != PM_EVENT_ON)
+ return 0;
+
+ psmouse_reset(psmouse);
+
+ if (!(priv->i = olpc_get_model(psmouse)))
+ return -1;
+
+ mode = olpc_find_mode(psmouse);
+ if (mode < 0)
+ return -1;
+
+ if (olpc_absolute_mode(psmouse, mode)) {
+ printk(KERN_ERR __FILE__ ": Failed to reenable absolute mode.\n");
+ return -1;
+ }
+
+ return 0;
+}
+
+static void olpc_disconnect(struct psmouse *psmouse)
+{
+ struct olpc_data *priv = psmouse->private;
+
+ psmouse_reset(psmouse);
+ input_unregister_device(priv->dev2);
+ kfree(priv);
+}
+
+static void olpc_mode_switch(struct work_struct *w)
+{
+ struct delayed_work *work = container_of(w, struct delayed_work, work);
+ struct olpc_data *priv = container_of(work, struct olpc_data, mode_switch);
+ struct psmouse *psmouse = priv->psmouse;
+ struct ps2dev *ps2dev = &psmouse->ps2dev;
+ int pending_mode, ret;
+
+ if (priv->pending_mode == priv->current_mode) {
+ priv->pending_mode = 0;
+ printk (KERN_DEBUG __FILE__ ": In switch_mode, no target mode.\n");
+ return;
+ }
+
+ if (tpdebug)
+ printk(KERN_WARNING __FILE__ ": Disable for switch to %d. [%lu]\n", priv->pending_mode, jiffies);
+
+ /* XXX: This is a bit hacky, make sure this isn't screwing stuff up. */
+ psmouse->state = PSMOUSE_INITIALIZING;
+
+ ret = ps2_command(ps2dev, NULL, PSMOUSE_CMD_DISABLE);
+ if (ret) {
+ /* XXX: if this ever fails, we need to do a full reset! */
+ printk(KERN_WARNING __FILE__ ": Disable failed for switch to %d. (%d) [%lu]\n", priv->pending_mode, ret, jiffies);
+ return;
+ }
+
+ /*
+ * ALPS tells us that it may take up to 20msec for the disable to
+ * take effect; however, ps2_command() will wait up to 200msec for
+ * the ACK to come back (and I'm assuming that by the time the
+ * hardware sends back its ACK, it has stopped sending bytes).
+ */
+ pending_mode = priv->pending_mode;
+
+ if (olpc_new_mode(psmouse, priv->pending_mode))
+ goto bad;
+
+ /*
+ * Deal with a potential race condition.
+ *
+ * If there is a brief tap of a stylus or a fingernail that
+ * triggers a mode switch to PT mode, and the stylus/fingernail is
+ * lifted after the DISABLE above, but before we reenable in the new mode,
+ * then we can get stuck in PT mode.
+ */
+ if (pending_mode == OLPC_PT) {
+ priv->pending_mode = OLPC_GS;
+ queue_delayed_work(kpsmoused_wq, &priv->mode_switch, msecs_to_jiffies(50));
+ }
+
+ return;
+
+bad:
+ printk(KERN_WARNING __FILE__ ": Failure to switch modes, resetting device...\n");
+ olpc_reconnect(psmouse);
+}
+
+int olpc_init(struct psmouse *psmouse)
+{
+ struct olpc_data *priv;
+ struct input_dev *dev = psmouse->dev;
+ struct input_dev *dev2;
+ int mode;
+
+ priv = kzalloc(sizeof(struct olpc_data), GFP_KERNEL);
+ dev2 = input_allocate_device();
+ if (!priv || !dev2)
+ goto init_fail;
+
+ psmouse->private = priv;
+ priv->dev2 = dev2;
+ priv->psmouse = psmouse;
+
+ psmouse_reset(psmouse);
+ if (!(priv->i = olpc_get_model(psmouse)))
+ goto init_fail;
+
+ mode = olpc_find_mode(psmouse);
+ if (mode < 0) {
+ printk(KERN_ERR __FILE__ ": Failed to identify proper mode\n");
+ goto init_fail;
+ }
+
+ if (olpc_absolute_mode(psmouse, mode)) {
+ printk(KERN_ERR __FILE__ ": Failed to enable absolute mode\n");
+ goto init_fail;
+ }
+
+ /*
+ * Unset some of the default bits for things we don't have.
+ */
+ dev->evbit[LONG(EV_REL)] &= ~BIT(EV_REL);
+ dev->relbit[LONG(REL_X)] &= ~(BIT(REL_X) | BIT(REL_Y));
+ dev->keybit[LONG(BTN_MIDDLE)] &= ~BIT(BTN_MIDDLE);
+
+ dev->evbit[LONG(EV_KEY)] |= BIT(EV_KEY);
+ dev->keybit[LONG(BTN_TOUCH)] |= BIT(BTN_TOUCH);
+ dev->keybit[LONG(BTN_TOOL_PEN)] |= BIT(BTN_TOOL_PEN);
+ dev->keybit[LONG(BTN_LEFT)] |= BIT(BTN_LEFT) | BIT(BTN_RIGHT);
+
+ dev->evbit[LONG(EV_ABS)] |= BIT(EV_ABS);
+ input_set_abs_params(dev, ABS_X, 2, 1000, 0, 0);
+ input_set_abs_params(dev, ABS_Y, 0, 717, 0, 0);
+
+ snprintf(priv->phys, sizeof(priv->phys),
+ "%s/input1", psmouse->ps2dev.serio->phys);
+ dev2->phys = priv->phys;
+ dev2->name = "OLPC ALPS GlideSensor";
+ dev2->id.bustype = BUS_I8042;
+ dev2->id.vendor = 0x0002;
+ dev2->id.product = PSMOUSE_OLPC;
+ dev2->id.version = 0x0000;
+
+ dev2->evbit[LONG(EV_KEY)] |= BIT(EV_KEY);
+ dev2->keybit[LONG(BTN_TOUCH)] |= BIT(BTN_TOUCH);
+ dev2->keybit[LONG(BTN_TOOL_FINGER)] |= BIT(BTN_TOOL_FINGER);
+ dev2->keybit[LONG(BTN_LEFT)] |= BIT(BTN_LEFT) | BIT(BTN_RIGHT);
+
+ dev2->evbit[LONG(EV_ABS)] |= BIT(EV_ABS);
+ input_set_abs_params(dev2, ABS_X, 350, 512, 0, 0);
+ input_set_abs_params(dev2, ABS_Y, 70, 325, 0, 0);
+ input_set_abs_params(dev2, ABS_PRESSURE, 0, 63, 0, 0);
+
+ if (input_register_device(dev2)) {
+ printk(KERN_ERR __FILE__ ": Failed to register GlideSensor\n");
+ goto init_fail;
+ }
+
+ psmouse->protocol_handler = olpc_process_byte;
+ psmouse->poll = olpc_poll;
+ psmouse->disconnect = olpc_disconnect;
+ psmouse->reconnect = olpc_reconnect;
+ psmouse->pktsize = 6;
+
+ /* Disable the idle resync. */
+ psmouse->resync_time = 0;
+ /* Reset after a lot of bad bytes. */
+ psmouse->resetafter = 1024;
+
+ INIT_DELAYED_WORK(&priv->mode_switch, olpc_mode_switch);
+
+ return 0;
+
+init_fail:
+ input_free_device(dev2);
+ kfree(priv);
+ return -1;
+}
+
+int olpc_detect(struct psmouse *psmouse, int set_properties)
+{
+ if (!olpc_get_model(psmouse))
+ return -1;
+
+ if (set_properties) {
+ psmouse->vendor = "ALPS";
+ psmouse->name = "PenTablet";
+ psmouse->model = 0;
+ }
+ return 0;
+}
+
--- /dev/null
+/*
+ * OLPC touchpad PS/2 mouse driver
+ *
+ * Copyright (c) 2006 One Laptop Per Child, inc.
+ *
+ * This driver is partly based on the ALPS driver.
+ * Copyright (c) 2003 Peter Osterlund <petero2@telia.com>
+ * Copyright (c) 2005 Vojtech Pavlik <vojtech@suse.cz>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License version 2 as published by
+ * the Free Software Foundation.
+ */
+
+#ifndef _OLPC_H
+#define _OLPC_H
+
+struct olpc_model_info {
+ unsigned char signature[3];
+ unsigned char flags;
+};
+
+struct olpc_data {
+ struct input_dev *dev2; /* Relative device */
+ struct psmouse *psmouse;
+ char name[32]; /* Name */
+ char phys[32]; /* Phys */
+ struct olpc_model_info *i; /* Info */
+ int pending_mode;
+ int current_mode;
+ s64 late;
+ struct delayed_work mode_switch;
+};
+
+#ifdef CONFIG_MOUSE_PS2_OLPC
+int olpc_detect(struct psmouse *psmouse, int set_properties);
+int olpc_init(struct psmouse *psmouse);
+#else
+inline int olpc_detect(struct psmouse *psmouse, int set_properties)
+{
+ return -ENOSYS;
+}
+inline int olpc_init(struct psmouse *psmouse)
+{
+ return -ENOSYS;
+}
+#endif
+
+#endif
--- /dev/null
+/*
+ * Register definitions for the m88alp01 camera interface. Offsets in bytes
+ * as given in the spec.
+ *
+ * Copyright 2006 One Laptop Per Child Association, Inc.
+ *
+ * Written by Jonathan Corbet, corbet@lwn.net.
+ *
+ * This file may be distributed under the terms of the GNU General
+ * Public License, version 2.
+ */
+#define REG_Y0BAR 0x00
+#define REG_Y1BAR 0x04
+#define REG_Y2BAR 0x08
+/* ... */
+
+#define REG_IMGPITCH 0x24 /* Image pitch register */
+#define IMGP_YP_SHFT 2 /* Y pitch params */
+#define IMGP_YP_MASK 0x00003ffc /* Y pitch field */
+#define IMGP_UVP_SHFT 18 /* UV pitch (planar) */
+#define IMGP_UVP_MASK 0x3ffc0000
+#define REG_IRQSTATRAW 0x28 /* RAW IRQ Status */
+#define IRQ_EOF0 0x00000001 /* End of frame 0 */
+#define IRQ_EOF1 0x00000002 /* End of frame 1 */
+#define IRQ_EOF2 0x00000004 /* End of frame 2 */
+#define IRQ_SOF0 0x00000008 /* Start of frame 0 */
+#define IRQ_SOF1 0x00000010 /* Start of frame 1 */
+#define IRQ_SOF2 0x00000020 /* Start of frame 2 */
+#define IRQ_OVERFLOW 0x00000040 /* FIFO overflow */
+#define IRQ_TWSIW 0x00010000 /* TWSI (smbus) write */
+#define IRQ_TWSIR 0x00020000 /* TWSI read */
+#define IRQ_TWSIE 0x00040000 /* TWSI error */
+#define TWSIIRQS (IRQ_TWSIW|IRQ_TWSIR|IRQ_TWSIE)
+#define FRAMEIRQS (IRQ_EOF0|IRQ_EOF1|IRQ_EOF2|IRQ_SOF0|IRQ_SOF1|IRQ_SOF2)
+#define ALLIRQS (TWSIIRQS|FRAMEIRQS|IRQ_OVERFLOW)
+#define REG_IRQMASK 0x2c /* IRQ mask - same bits as IRQSTAT */
+#define REG_IRQSTAT 0x30 /* IRQ status / clear */
+
+#define REG_IMGSIZE 0x34 /* Image size */
+#define IMGSZ_V_MASK 0x1fff0000
+#define IMGSZ_V_SHIFT 16
+#define IMGSZ_H_MASK 0x00003fff
+#define REG_IMGOFFSET 0x38 /* IMage offset */
+
+#define REG_CTRL0 0x3c /* Control 0 */
+#define C0_ENABLE 0x00000001 /* Makes the whole thing go */
+
+/* Mask for all the format bits */
+#define C0_DF_MASK 0x00fffffc /* Bits 2-23 */
+
+/* RGB ordering */
+#define C0_RGB4_RGBX 0x00000000
+#define C0_RGB4_XRGB 0x00000004
+#define C0_RGB4_BGRX 0x00000008
+#define C0_RGB4_XBGR 0x0000000c
+#define C0_RGB5_RGGB 0x00000000
+#define C0_RGB5_GRBG 0x00000004
+#define C0_RGB5_GBRG 0x00000008
+#define C0_RGB5_BGGR 0x0000000c
+
+/* Spec has two fields for DIN and DOUT, but they must match, so
+ combine them here. */
+#define C0_DF_YUV 0x00000000 /* Data is YUV */
+#define C0_DF_RGB 0x000000a0 /* ... RGB */
+#define C0_DF_BAYER 0x00000140 /* ... Bayer */
+/* 8-8-8 must be missing from the below - ask */
+#define C0_RGBF_565 0x00000000
+#define C0_RGBF_444 0x00000800
+#define C0_RGB_BGR 0x00001000 /* Blue comes first */
+#define C0_YUV_PLANAR 0x00000000 /* YUV 422 planar format */
+#define C0_YUV_PACKED 0x00008000 /* YUV 422 packed */
+#define C0_YUV_420PL 0x0000a000 /* YUV 420 planar */
+/* Think that 420 packed must be 111 - ask */
+#define C0_YUVE_YUYV 0x00000000 /* Y1CbY0Cr */
+#define C0_YUVE_YVYU 0x00010000 /* Y1CrY0Cb */
+#define C0_YUVE_VYUY 0x00020000 /* CrY1CbY0 */
+#define C0_YUVE_UYVY 0x00030000 /* CbY1CrY0 */
+#define C0_YUVE_XYUV 0x00000000 /* 420: .YUV */
+#define C0_YUVE_XYVU 0x00010000 /* 420: .YVU */
+#define C0_YUVE_XUVY 0x00020000 /* 420: .UVY */
+#define C0_YUVE_XVUY 0x00030000 /* 420: .VUY */
+/* Bayer bits 18,19 if needed */
+#define C0_HPOL_LOW 0x01000000 /* HSYNC polarity active low */
+#define C0_VPOL_LOW 0x02000000 /* VSYNC polarity active low */
+#define C0_VCLK_LOW 0x04000000 /* VCLK on falling edge */
+#define C0_DOWNSCALE 0x08000000 /* Enable downscaler */
+#define C0_SIFM_MASK 0xc0000000 /* SIF mode bits */
+#define C0_SIF_HVSYNC 0x00000000 /* Use H/VSYNC */
+#define CO_SOF_NOSYNC 0x40000000 /* Use inband active signaling */
+
+
+#define REG_CTRL1 0x40 /* Control 1 */
+#define C1_444ALPHA 0x00f00000 /* Alpha field in RGB444 */
+#define C1_ALPHA_SHFT 20
+#define C1_DMAB32 0x00000000 /* 32-byte DMA burst */
+#define C1_DMAB16 0x02000000 /* 16-byte DMA burst */
+#define C1_DMAB64 0x04000000 /* 64-byte DMA burst */
+#define C1_DMAB_MASK 0x06000000
+#define C1_TWOBUFS 0x08000000 /* Use only two DMA buffers */
+#define C1_PWRDWN 0x10000000 /* Power down */
+
+#define REG_CLKCTRL 0x88 /* Clock control */
+#define CLK_DIV_MASK 0x0000ffff /* Upper bits RW "reserved" */
+
+#define REG_GPR 0xb4 /* General purpose register. This
+ controls inputs to the power and reset
+ pins on the OV7670 used with OLPC;
+ other deployments could differ. */
+#define GPR_C1EN 0x00000020 /* Pad 1 (power down) enable */
+#define GPR_C0EN 0x00000010 /* Pad 0 (reset) enable */
+#define GPR_C1 0x00000002 /* Control 1 value */
+/*
+ * Control 0 is wired to reset on OLPC machines. For ov7x sensors,
+ * it is active low, for 0v6x, instead, it's active high. What
+ * fun.
+ */
+#define GPR_C0 0x00000001 /* Control 0 value */
+
+#define REG_TWSIC0 0xb8 /* TWSI (smbus) control 0 */
+#define TWSIC0_EN 0x00000001 /* TWSI enable */
+#define TWSIC0_MODE 0x00000002 /* 1 = 16-bit, 0 = 8-bit */
+#define TWSIC0_SID 0x000003fc /* Slave ID */
+#define TWSIC0_SID_SHIFT 2
+#define TWSIC0_CLKDIV 0x0007fc00 /* Clock divider */
+#define TWSIC0_MASKACK 0x00400000 /* Mask ack from sensor */
+#define TWSIC0_OVMAGIC 0x00800000 /* Make it work on OV sensors */
+
+#define REG_TWSIC1 0xbc /* TWSI control 1 */
+#define TWSIC1_DATA 0x0000ffff /* Data to/from camchip */
+#define TWSIC1_ADDR 0x00ff0000 /* Address (register) */
+#define TWSIC1_ADDR_SHIFT 16
+#define TWSIC1_READ 0x01000000 /* Set for read op */
+#define TWSIC1_WSTAT 0x02000000 /* Write status */
+#define TWSIC1_RVALID 0x04000000 /* Read data valid */
+#define TWSIC1_ERROR 0x08000000 /* Something screwed up */
+
+
+#define REG_UBAR 0xc4 /* Upper base address register */
+
+/*
+ * Here's the weird global control registers which are said to live
+ * way up here.
+ */
+#define REG_GL_CSR 0x3004 /* Control/status register */
+#define GCSR_SRS 0x00000001 /* SW Reset set */
+#define GCSR_SRC 0x00000002 /* SW Reset clear */
+#define GCSR_MRS 0x00000004 /* Master reset set */
+#define GCSR_MRC 0x00000008 /* HW Reset clear */
+#define GCSR_CCIC_EN 0x00004000 /* CCIC Clock enable */
+#define REG_GL_IMASK 0x300c /* Interrupt mask register */
+#define GIMSK_CCIC_EN 0x00000004 /* CCIC Interrupt enable */
+
+#define REG_GL_FCR 0x3038 /* GPIO functional control register */
+#define GFCR_GPIO_ON 0x08 /* Camera GPIO enabled */
+#define REG_GL_GPIOR 0x315c /* GPIO register */
+#define GGPIO_OUT 0x80000 /* GPIO output */
+#define GGPIO_VAL 0x00008 /* Output pin value */
+
+#define REG_LEN REG_GL_IMASK + 4
+
+
+/*
+ * Useful stuff that probably belongs somewhere global.
+ */
+#define VGA_WIDTH 640
+#define VGA_HEIGHT 480
--- /dev/null
+/*
+ * A driver for the CMOS camera controller in the Marvell 88ALP01 "cafe"
+ * multifunction chip. Currently works with the Omnivision OV7670
+ * sensor.
+ *
+ * Copyright 2006 One Laptop Per Child Association, Inc.
+ * Copyright 2006-7 Jonathan Corbet <corbet@lwn.net>
+ *
+ * Written by Jonathan Corbet, corbet@lwn.net.
+ *
+ * This file may be distributed under the terms of the GNU General
+ * Public License, version 2.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/moduleparam.h>
+#include <linux/init.h>
+#include <linux/fs.h>
+#include <linux/pci.h>
+#include <linux/i2c.h>
+#include <linux/interrupt.h>
+#include <linux/spinlock.h>
+#include <linux/videodev2.h>
+#include <media/v4l2-common.h>
+#include <media/v4l2-chip-ident.h>
+#include <linux/device.h>
+#include <linux/wait.h>
+#include <linux/list.h>
+#include <linux/dma-mapping.h>
+#include <linux/delay.h>
+#include <linux/debugfs.h>
+#include <linux/jiffies.h>
+#include <linux/vmalloc.h>
+
+#include <asm/uaccess.h>
+#include <asm/io.h>
+
+#include "cafe_ccic-regs.h"
+
+#define CAFE_VERSION 0x000002
+
+
+/*
+ * Parameters.
+ */
+MODULE_AUTHOR("Jonathan Corbet <corbet@lwn.net>");
+MODULE_DESCRIPTION("Marvell 88ALP01 CMOS Camera Controller driver");
+MODULE_LICENSE("GPL");
+MODULE_SUPPORTED_DEVICE("Video");
+
+/*
+ * Internal DMA buffer management. Since the controller cannot do S/G I/O,
+ * we must have physically contiguous buffers to bring frames into.
+ * These parameters control how many buffers we use, whether we
+ * allocate them at load time (better chance of success, but nails down
+ * memory) or when somebody tries to use the camera (riskier), and,
+ * for load-time allocation, how big they should be.
+ *
+ * The controller can cycle through three buffers. We could use
+ * more by flipping pointers around, but it probably makes little
+ * sense.
+ */
+
+#define MAX_DMA_BUFS 3
+static int alloc_bufs_at_read = 0;
+module_param(alloc_bufs_at_read, bool, 0444);
+MODULE_PARM_DESC(alloc_bufs_at_read,
+ "Non-zero value causes DMA buffers to be allocated when the "
+ "video capture device is read, rather than at module load "
+ "time. This saves memory, but decreases the chances of "
+ "successfully getting those buffers.");
+
+static int n_dma_bufs = 3;
+module_param(n_dma_bufs, uint, 0644);
+MODULE_PARM_DESC(n_dma_bufs,
+ "The number of DMA buffers to allocate. Can be either two "
+ "(saves memory, makes timing tighter) or three.");
+
+static int dma_buf_size = VGA_WIDTH * VGA_HEIGHT * 2; /* Worst case */
+module_param(dma_buf_size, uint, 0444);
+MODULE_PARM_DESC(dma_buf_size,
+ "The size of the allocated DMA buffers. If actual operating "
+ "parameters require larger buffers, an attempt to reallocate "
+ "will be made.");
+
+static int min_buffers = 1;
+module_param(min_buffers, uint, 0644);
+MODULE_PARM_DESC(min_buffers,
+ "The minimum number of streaming I/O buffers we are willing "
+ "to work with.");
+
+static int max_buffers = 10;
+module_param(max_buffers, uint, 0644);
+MODULE_PARM_DESC(max_buffers,
+ "The maximum number of streaming I/O buffers an application "
+ "will be allowed to allocate. These buffers are big and live "
+ "in vmalloc space.");
+
+static int flip = 0;
+module_param(flip, bool, 0444);
+MODULE_PARM_DESC(flip,
+ "If set, the sensor will be instructed to flip the image "
+ "vertically.");
+
+
+enum cafe_state {
+ S_NOTREADY, /* Not yet initialized */
+ S_IDLE, /* Just hanging around */
+ S_FLAKED, /* Some sort of problem */
+ S_SINGLEREAD, /* In read() */
+ S_SPECREAD, /* Speculative read (for future read()) */
+ S_STREAMING /* Streaming data */
+};
+
+/*
+ * Tracking of streaming I/O buffers.
+ */
+struct cafe_sio_buffer {
+ struct list_head list;
+ struct v4l2_buffer v4lbuf;
+ char *buffer; /* Where it lives in kernel space */
+ int mapcount;
+ struct cafe_camera *cam;
+};
+
+/*
+ * A description of one of our devices.
+ * Locking: controlled by s_mutex. Certain fields, however, require
+ * the dev_lock spinlock; they are marked as such by comments.
+ * dev_lock is also required for access to device registers.
+ */
+struct cafe_camera
+{
+ enum cafe_state state;
+ unsigned long flags; /* Buffer status, mainly (dev_lock) */
+ int users; /* How many open FDs */
+ struct file *owner; /* Who has data access (v4l2) */
+
+ /*
+ * Subsystem structures.
+ */
+ struct pci_dev *pdev;
+ struct video_device v4ldev;
+ struct i2c_adapter i2c_adapter;
+ struct i2c_client *sensor;
+
+ unsigned char __iomem *regs;
+ struct list_head dev_list; /* link to other devices */
+
+ /* DMA buffers */
+ unsigned int nbufs; /* How many are alloc'd */
+ int next_buf; /* Next to consume (dev_lock) */
+ unsigned int dma_buf_size; /* allocated size */
+ void *dma_bufs[MAX_DMA_BUFS]; /* Internal buffer addresses */
+ dma_addr_t dma_handles[MAX_DMA_BUFS]; /* Buffer bus addresses */
+ unsigned int specframes; /* Unconsumed spec frames (dev_lock) */
+ unsigned int sequence; /* Frame sequence number */
+ unsigned int buf_seq[MAX_DMA_BUFS]; /* Sequence for individual buffers */
+
+ /* Streaming buffers */
+ unsigned int n_sbufs; /* How many we have */
+ struct cafe_sio_buffer *sb_bufs; /* The array of housekeeping structs */
+ struct list_head sb_avail; /* Available for data (we own) (dev_lock) */
+ struct list_head sb_full; /* With data (user space owns) (dev_lock) */
+ struct tasklet_struct s_tasklet;
+
+ /* Current operating parameters */
+ u32 sensor_type; /* Currently ov7670 only */
+ struct v4l2_pix_format pix_format;
+
+ /* Locks */
+ struct mutex s_mutex; /* Access to this structure */
+ spinlock_t dev_lock; /* Access to device */
+
+ /* Misc */
+ wait_queue_head_t smbus_wait; /* Waiting on i2c events */
+ wait_queue_head_t iowait; /* Waiting on frame data */
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+ struct dentry *dfs_regs;
+ struct dentry *dfs_cam_regs;
+#endif
+};
+
+/*
+ * Status flags. Always manipulated with bit operations.
+ */
+#define CF_BUF0_VALID 0 /* Buffers valid - first three */
+#define CF_BUF1_VALID 1
+#define CF_BUF2_VALID 2
+#define CF_DMA_ACTIVE 3 /* A frame is incoming */
+#define CF_CONFIG_NEEDED 4 /* Must configure hardware */
+
+
+
+/*
+ * Start over with DMA buffers - dev_lock needed.
+ */
+static void cafe_reset_buffers(struct cafe_camera *cam)
+{
+ int i;
+
+ cam->next_buf = -1;
+ for (i = 0; i < cam->nbufs; i++)
+ clear_bit(i, &cam->flags);
+ cam->specframes = 0;
+}
+
+static inline int cafe_needs_config(struct cafe_camera *cam)
+{
+ return test_bit(CF_CONFIG_NEEDED, &cam->flags);
+}
+
+static void cafe_set_config_needed(struct cafe_camera *cam, int needed)
+{
+ if (needed)
+ set_bit(CF_CONFIG_NEEDED, &cam->flags);
+ else
+ clear_bit(CF_CONFIG_NEEDED, &cam->flags);
+}
+
+
+
+
+/*
+ * Debugging and related.
+ */
+#define cam_err(cam, fmt, arg...) \
+ dev_err(&(cam)->pdev->dev, fmt, ##arg);
+#define cam_warn(cam, fmt, arg...) \
+ dev_warn(&(cam)->pdev->dev, fmt, ##arg);
+#define cam_dbg(cam, fmt, arg...) \
+ dev_dbg(&(cam)->pdev->dev, fmt, ##arg);
+
+
+/* ---------------------------------------------------------------------*/
+/*
+ * We keep a simple list of known devices to search at open time.
+ */
+static LIST_HEAD(cafe_dev_list);
+static DEFINE_MUTEX(cafe_dev_list_lock);
+
+static void cafe_add_dev(struct cafe_camera *cam)
+{
+ mutex_lock(&cafe_dev_list_lock);
+ list_add_tail(&cam->dev_list, &cafe_dev_list);
+ mutex_unlock(&cafe_dev_list_lock);
+}
+
+static void cafe_remove_dev(struct cafe_camera *cam)
+{
+ mutex_lock(&cafe_dev_list_lock);
+ list_del(&cam->dev_list);
+ mutex_unlock(&cafe_dev_list_lock);
+}
+
+static struct cafe_camera *cafe_find_dev(int minor)
+{
+ struct cafe_camera *cam;
+
+ mutex_lock(&cafe_dev_list_lock);
+ list_for_each_entry(cam, &cafe_dev_list, dev_list) {
+ if (cam->v4ldev.minor == minor)
+ goto done;
+ }
+ cam = NULL;
+ done:
+ mutex_unlock(&cafe_dev_list_lock);
+ return cam;
+}
+
+
+static struct cafe_camera *cafe_find_by_pdev(struct pci_dev *pdev)
+{
+ struct cafe_camera *cam;
+
+ mutex_lock(&cafe_dev_list_lock);
+ list_for_each_entry(cam, &cafe_dev_list, dev_list) {
+ if (cam->pdev == pdev)
+ goto done;
+ }
+ cam = NULL;
+ done:
+ mutex_unlock(&cafe_dev_list_lock);
+ return cam;
+}
+
+
+/* ------------------------------------------------------------------------ */
+/*
+ * Device register I/O
+ */
+static inline void cafe_reg_write(struct cafe_camera *cam, unsigned int reg,
+ unsigned int val)
+{
+ iowrite32(val, cam->regs + reg);
+}
+
+static inline unsigned int cafe_reg_read(struct cafe_camera *cam,
+ unsigned int reg)
+{
+ return ioread32(cam->regs + reg);
+}
+
+
+static inline void cafe_reg_write_mask(struct cafe_camera *cam, unsigned int reg,
+ unsigned int val, unsigned int mask)
+{
+ unsigned int v = cafe_reg_read(cam, reg);
+
+ v = (v & ~mask) | (val & mask);
+ cafe_reg_write(cam, reg, v);
+}
+
+static inline void cafe_reg_clear_bit(struct cafe_camera *cam,
+ unsigned int reg, unsigned int val)
+{
+ cafe_reg_write_mask(cam, reg, 0, val);
+}
+
+static inline void cafe_reg_set_bit(struct cafe_camera *cam,
+ unsigned int reg, unsigned int val)
+{
+ cafe_reg_write_mask(cam, reg, val, val);
+}
+
+
+
+/* -------------------------------------------------------------------- */
+/*
+ * The I2C/SMBUS interface to the camera itself starts here. The
+ * controller handles SMBUS itself, presenting a relatively simple register
+ * interface; all we have to do is to tell it where to route the data.
+ */
+#define CAFE_SMBUS_TIMEOUT (HZ) /* generous */
+
+static int cafe_smbus_write_done(struct cafe_camera *cam)
+{
+ unsigned long flags;
+ int c1;
+
+ /*
+ * We must delay after the interrupt, or the controller gets confused
+ * and never does give us good status. Fortunately, we don't do this
+ * often.
+ */
+ udelay(20);
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ c1 = cafe_reg_read(cam, REG_TWSIC1);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ return (c1 & (TWSIC1_WSTAT|TWSIC1_ERROR)) != TWSIC1_WSTAT;
+}
+
+static int cafe_smbus_write_data(struct cafe_camera *cam,
+ u16 addr, u8 command, u8 value)
+{
+ unsigned int rval;
+ unsigned long flags;
+
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ rval = TWSIC0_EN | ((addr << TWSIC0_SID_SHIFT) & TWSIC0_SID);
+ rval |= TWSIC0_OVMAGIC; /* Make OV sensors work */
+ /*
+ * Marvell sez set clkdiv to all 1's for now.
+ */
+ rval |= TWSIC0_CLKDIV;
+ cafe_reg_write(cam, REG_TWSIC0, rval);
+ (void) cafe_reg_read(cam, REG_TWSIC1); /* force write */
+ rval = value | ((command << TWSIC1_ADDR_SHIFT) & TWSIC1_ADDR);
+ cafe_reg_write(cam, REG_TWSIC1, rval);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ mdelay(2); /* It'll probably take about 900µs anyway, and the
+ CAFÉ is apparently quite sensitive to being poked
+ at this point. If we can work out precisely what's
+ going on and reduce this delay, it would be nice. */
+
+ wait_event_timeout(cam->smbus_wait, cafe_smbus_write_done(cam),
+ CAFE_SMBUS_TIMEOUT);
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ rval = cafe_reg_read(cam, REG_TWSIC1);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+
+ if (rval & TWSIC1_WSTAT) {
+ cam_err(cam, "SMBUS write (%02x/%02x/%02x) timed out\n", addr,
+ command, value);
+ return -EIO;
+ }
+ if (rval & TWSIC1_ERROR) {
+ cam_err(cam, "SMBUS write (%02x/%02x/%02x) error\n", addr,
+ command, value);
+ return -EIO;
+ }
+ return 0;
+}
+
+
+
+static int cafe_smbus_read_done(struct cafe_camera *cam)
+{
+ unsigned long flags;
+ int c1;
+
+ /*
+ * We must delay after the interrupt, or the controller gets confused
+ * and never does give us good status. Fortunately, we don't do this
+ * often.
+ */
+ udelay(20);
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ c1 = cafe_reg_read(cam, REG_TWSIC1);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ return c1 & (TWSIC1_RVALID|TWSIC1_ERROR);
+}
+
+
+
+static int cafe_smbus_read_data(struct cafe_camera *cam,
+ u16 addr, u8 command, u8 *value)
+{
+ unsigned int rval;
+ unsigned long flags;
+
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ rval = TWSIC0_EN | ((addr << TWSIC0_SID_SHIFT) & TWSIC0_SID);
+ rval |= TWSIC0_OVMAGIC; /* Make OV sensors work */
+ /*
+ * Marvel sez set clkdiv to all 1's for now.
+ */
+ rval |= TWSIC0_CLKDIV;
+ cafe_reg_write(cam, REG_TWSIC0, rval);
+ (void) cafe_reg_read(cam, REG_TWSIC1); /* force write */
+ rval = TWSIC1_READ | ((command << TWSIC1_ADDR_SHIFT) & TWSIC1_ADDR);
+ cafe_reg_write(cam, REG_TWSIC1, rval);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+
+ wait_event_timeout(cam->smbus_wait,
+ cafe_smbus_read_done(cam), CAFE_SMBUS_TIMEOUT);
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ rval = cafe_reg_read(cam, REG_TWSIC1);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+
+ if (rval & TWSIC1_ERROR) {
+ cam_err(cam, "SMBUS read (%02x/%02x) error\n", addr, command);
+ return -EIO;
+ }
+ if (! (rval & TWSIC1_RVALID)) {
+ cam_err(cam, "SMBUS read (%02x/%02x) timed out\n", addr,
+ command);
+ return -EIO;
+ }
+ *value = rval & 0xff;
+ return 0;
+}
+
+/*
+ * Perform a transfer over SMBUS. This thing is called under
+ * the i2c bus lock, so we shouldn't race with ourselves...
+ */
+static int cafe_smbus_xfer(struct i2c_adapter *adapter, u16 addr,
+ unsigned short flags, char rw, u8 command,
+ int size, union i2c_smbus_data *data)
+{
+ struct cafe_camera *cam = i2c_get_adapdata(adapter);
+ int ret = -EINVAL;
+
+ /*
+ * Refuse to talk to anything but OV cam chips. We should
+ * never even see an attempt to do so, but one never knows.
+ */
+ if (cam->sensor && addr != cam->sensor->addr) {
+ cam_err(cam, "funky smbus addr %d\n", addr);
+ return -EINVAL;
+ }
+ /*
+ * This interface would appear to only do byte data ops. OK
+ * it can do word too, but the cam chip has no use for that.
+ */
+ if (size != I2C_SMBUS_BYTE_DATA) {
+ cam_err(cam, "funky xfer size %d\n", size);
+ return -EINVAL;
+ }
+
+ if (rw == I2C_SMBUS_WRITE)
+ ret = cafe_smbus_write_data(cam, addr, command, data->byte);
+ else if (rw == I2C_SMBUS_READ)
+ ret = cafe_smbus_read_data(cam, addr, command, &data->byte);
+ return ret;
+}
+
+
+static void cafe_smbus_enable_irq(struct cafe_camera *cam)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ cafe_reg_set_bit(cam, REG_IRQMASK, TWSIIRQS);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+}
+
+static u32 cafe_smbus_func(struct i2c_adapter *adapter)
+{
+ return I2C_FUNC_SMBUS_READ_BYTE_DATA |
+ I2C_FUNC_SMBUS_WRITE_BYTE_DATA;
+}
+
+static struct i2c_algorithm cafe_smbus_algo = {
+ .smbus_xfer = cafe_smbus_xfer,
+ .functionality = cafe_smbus_func
+};
+
+/* Somebody is on the bus */
+static int cafe_cam_init(struct cafe_camera *cam);
+static void cafe_ctlr_stop_dma(struct cafe_camera *cam);
+static void cafe_ctlr_power_down(struct cafe_camera *cam);
+
+static int cafe_smbus_attach(struct i2c_client *client)
+{
+ struct cafe_camera *cam = i2c_get_adapdata(client->adapter);
+
+ /*
+ * Don't talk to chips we don't recognize.
+ */
+ if (client->driver->id == I2C_DRIVERID_OV7670) {
+ cam->sensor = client;
+ return cafe_cam_init(cam);
+ }
+ return -EINVAL;
+}
+
+static int cafe_smbus_detach(struct i2c_client *client)
+{
+ struct cafe_camera *cam = i2c_get_adapdata(client->adapter);
+
+ if (cam->sensor == client) {
+ cafe_ctlr_stop_dma(cam);
+ cafe_ctlr_power_down(cam);
+ cam_err(cam, "lost the sensor!\n");
+ cam->sensor = NULL; /* Bummer, no camera */
+ cam->state = S_NOTREADY;
+ }
+ return 0;
+}
+
+static int cafe_smbus_setup(struct cafe_camera *cam)
+{
+ struct i2c_adapter *adap = &cam->i2c_adapter;
+ int ret;
+
+ cafe_smbus_enable_irq(cam);
+ adap->id = I2C_HW_SMBUS_CAFE;
+ adap->class = I2C_CLASS_CAM_DIGITAL;
+ adap->owner = THIS_MODULE;
+ adap->client_register = cafe_smbus_attach;
+ adap->client_unregister = cafe_smbus_detach;
+ adap->algo = &cafe_smbus_algo;
+ strcpy(adap->name, "cafe_ccic");
+ adap->dev.parent = &cam->pdev->dev;
+ i2c_set_adapdata(adap, cam);
+ ret = i2c_add_adapter(adap);
+ if (ret)
+ printk(KERN_ERR "Unable to register cafe i2c adapter\n");
+ return ret;
+}
+
+static void cafe_smbus_shutdown(struct cafe_camera *cam)
+{
+ i2c_del_adapter(&cam->i2c_adapter);
+}
+
+
+/* ------------------------------------------------------------------- */
+/*
+ * Deal with the controller.
+ */
+
+/*
+ * Do everything we think we need to have the interface operating
+ * according to the desired format.
+ */
+static void cafe_ctlr_dma(struct cafe_camera *cam)
+{
+ /*
+ * Store the first two Y buffers (we aren't supporting
+ * planar formats for now, so no UV bufs). Then either
+ * set the third if it exists, or tell the controller
+ * to just use two.
+ */
+ cafe_reg_write(cam, REG_Y0BAR, cam->dma_handles[0]);
+ cafe_reg_write(cam, REG_Y1BAR, cam->dma_handles[1]);
+ if (cam->nbufs > 2) {
+ cafe_reg_write(cam, REG_Y2BAR, cam->dma_handles[2]);
+ cafe_reg_clear_bit(cam, REG_CTRL1, C1_TWOBUFS);
+ }
+ else
+ cafe_reg_set_bit(cam, REG_CTRL1, C1_TWOBUFS);
+ cafe_reg_write(cam, REG_UBAR, 0); /* 32 bits only for now */
+}
+
+static void cafe_ctlr_image(struct cafe_camera *cam)
+{
+ int imgsz;
+ struct v4l2_pix_format *fmt = &cam->pix_format;
+
+ imgsz = ((fmt->height << IMGSZ_V_SHIFT) & IMGSZ_V_MASK) |
+ (fmt->bytesperline & IMGSZ_H_MASK);
+ cafe_reg_write(cam, REG_IMGSIZE, imgsz);
+ cafe_reg_write(cam, REG_IMGOFFSET, 0);
+ /* YPITCH just drops the last two bits */
+ cafe_reg_write_mask(cam, REG_IMGPITCH, fmt->bytesperline,
+ IMGP_YP_MASK);
+ /*
+ * Tell the controller about the image format we are using.
+ */
+ switch (cam->pix_format.pixelformat) {
+ case V4L2_PIX_FMT_YUYV:
+ cafe_reg_write_mask(cam, REG_CTRL0,
+ C0_DF_YUV|C0_YUV_PACKED|C0_YUVE_YUYV,
+ C0_DF_MASK);
+ break;
+
+ case V4L2_PIX_FMT_RGB444:
+ cafe_reg_write_mask(cam, REG_CTRL0,
+ C0_DF_RGB|C0_RGBF_444|C0_RGB4_XRGB,
+ C0_DF_MASK);
+ /* Alpha value? */
+ break;
+
+ case V4L2_PIX_FMT_RGB565:
+ cafe_reg_write_mask(cam, REG_CTRL0,
+ C0_DF_RGB|C0_RGBF_565|C0_RGB5_BGGR,
+ C0_DF_MASK);
+ break;
+
+ default:
+ cam_err(cam, "Unknown format %x\n", cam->pix_format.pixelformat);
+ break;
+ }
+ /*
+ * Make sure it knows we want to use hsync/vsync.
+ */
+ cafe_reg_write_mask(cam, REG_CTRL0, C0_SIF_HVSYNC,
+ C0_SIFM_MASK);
+}
+
+
+/*
+ * Configure the controller for operation; caller holds the
+ * device mutex.
+ */
+static int cafe_ctlr_configure(struct cafe_camera *cam)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ cafe_ctlr_dma(cam);
+ cafe_ctlr_image(cam);
+ cafe_set_config_needed(cam, 0);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ return 0;
+}
+
+static void cafe_ctlr_irq_enable(struct cafe_camera *cam)
+{
+ /*
+ * Clear any pending interrupts, since we do not
+ * expect to have I/O active prior to enabling.
+ */
+ cafe_reg_write(cam, REG_IRQSTAT, FRAMEIRQS);
+ cafe_reg_set_bit(cam, REG_IRQMASK, FRAMEIRQS);
+}
+
+static void cafe_ctlr_irq_disable(struct cafe_camera *cam)
+{
+ cafe_reg_clear_bit(cam, REG_IRQMASK, FRAMEIRQS);
+}
+
+/*
+ * Make the controller start grabbing images. Everything must
+ * be set up before doing this.
+ */
+static void cafe_ctlr_start(struct cafe_camera *cam)
+{
+ /* set_bit performs a read, so no other barrier should be
+ needed here */
+ cafe_reg_set_bit(cam, REG_CTRL0, C0_ENABLE);
+}
+
+static void cafe_ctlr_stop(struct cafe_camera *cam)
+{
+ cafe_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
+}
+
+static void cafe_ctlr_init(struct cafe_camera *cam)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ /*
+ * Added magic to bring up the hardware on the B-Test board
+ */
+ cafe_reg_write(cam, 0x3038, 0x8);
+ cafe_reg_write(cam, 0x315c, 0x80008);
+ /*
+ * Go through the dance needed to wake the device up.
+ * Note that these registers are global and shared
+ * with the NAND and SD devices. Interaction between the
+ * three still needs to be examined.
+ */
+ cafe_reg_write(cam, REG_GL_CSR, GCSR_SRS|GCSR_MRS); /* Needed? */
+ cafe_reg_write(cam, REG_GL_CSR, GCSR_SRC|GCSR_MRC);
+ cafe_reg_write(cam, REG_GL_CSR, GCSR_SRC|GCSR_MRS);
+ /*
+ * Here we must wait a bit for the controller to come around.
+ */
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ mdelay(5); /* FIXME revisit this */
+ spin_lock_irqsave(&cam->dev_lock, flags);
+
+ cafe_reg_write(cam, REG_GL_CSR, GCSR_CCIC_EN|GCSR_SRC|GCSR_MRC);
+ cafe_reg_set_bit(cam, REG_GL_IMASK, GIMSK_CCIC_EN);
+ /*
+ * Make sure it's not powered down.
+ */
+ cafe_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN);
+ /*
+ * Turn off the enable bit. It sure should be off anyway,
+ * but it's good to be sure.
+ */
+ cafe_reg_clear_bit(cam, REG_CTRL0, C0_ENABLE);
+ /*
+ * Mask all interrupts.
+ */
+ cafe_reg_write(cam, REG_IRQMASK, 0);
+ /*
+ * Clock the sensor appropriately. Controller clock should
+ * be 48MHz, sensor "typical" value is half that.
+ */
+ cafe_reg_write_mask(cam, REG_CLKCTRL, 2, CLK_DIV_MASK);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+}
+
+
+/*
+ * Stop the controller, and don't return until we're really sure that no
+ * further DMA is going on.
+ */
+static void cafe_ctlr_stop_dma(struct cafe_camera *cam)
+{
+ unsigned long flags;
+
+ /*
+ * Theory: stop the camera controller (whether it is operating
+ * or not). Delay briefly just in case we race with the SOF
+ * interrupt, then wait until no DMA is active.
+ */
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ cafe_ctlr_stop(cam);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ mdelay(1);
+ wait_event_timeout(cam->iowait,
+ !test_bit(CF_DMA_ACTIVE, &cam->flags), HZ);
+ if (test_bit(CF_DMA_ACTIVE, &cam->flags))
+ cam_err(cam, "Timeout waiting for DMA to end\n");
+ /* This would be bad news - what now? */
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ cam->state = S_IDLE;
+ cafe_ctlr_irq_disable(cam);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+}
+
+/*
+ * Power up and down.
+ */
+static void cafe_ctlr_power_up(struct cafe_camera *cam)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ cafe_reg_clear_bit(cam, REG_CTRL1, C1_PWRDWN);
+ /*
+ * Part one of the sensor dance: turn the global
+ * GPIO signal on.
+ */
+ cafe_reg_write(cam, REG_GL_FCR, GFCR_GPIO_ON);
+ cafe_reg_write(cam, REG_GL_GPIOR, GGPIO_OUT|GGPIO_VAL);
+ /*
+ * Put the sensor into operational mode (assumes OLPC-style
+ * wiring). Control 0 is reset - set to 1 to operate.
+ * Control 1 is power down, set to 0 to operate.
+ */
+ cafe_reg_write(cam, REG_GPR, GPR_C1EN|GPR_C0EN); /* pwr up, reset */
+// mdelay(1); /* Marvell says 1ms will do it */
+ cafe_reg_write(cam, REG_GPR, GPR_C1EN|GPR_C0EN|GPR_C0);
+// mdelay(1); /* Enough? */
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ msleep(5); /* Just to be sure */
+}
+
+static void cafe_ctlr_power_down(struct cafe_camera *cam)
+{
+ unsigned long flags;
+
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ cafe_reg_write(cam, REG_GPR, GPR_C1EN|GPR_C0EN|GPR_C1);
+ cafe_reg_write(cam, REG_GL_FCR, GFCR_GPIO_ON);
+ cafe_reg_write(cam, REG_GL_GPIOR, GGPIO_OUT);
+ cafe_reg_set_bit(cam, REG_CTRL1, C1_PWRDWN);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+}
+
+/* -------------------------------------------------------------------- */
+/*
+ * Communications with the sensor.
+ */
+
+static int __cafe_cam_cmd(struct cafe_camera *cam, int cmd, void *arg)
+{
+ struct i2c_client *sc = cam->sensor;
+ int ret;
+
+ if (sc == NULL || sc->driver == NULL || sc->driver->command == NULL)
+ return -EINVAL;
+ ret = sc->driver->command(sc, cmd, arg);
+ if (ret == -EPERM) /* Unsupported command */
+ return 0;
+ return ret;
+}
+
+static int __cafe_cam_reset(struct cafe_camera *cam)
+{
+ int zero = 0;
+ return __cafe_cam_cmd(cam, VIDIOC_INT_RESET, &zero);
+}
+
+/*
+ * We have found the sensor on the i2c. Let's try to have a
+ * conversation.
+ */
+static int cafe_cam_init(struct cafe_camera *cam)
+{
+ struct v4l2_chip_ident chip = { V4L2_CHIP_MATCH_I2C_ADDR, 0, 0, 0 };
+ int ret;
+
+ mutex_lock(&cam->s_mutex);
+ if (cam->state != S_NOTREADY)
+ cam_warn(cam, "Cam init with device in funky state %d",
+ cam->state);
+ ret = __cafe_cam_reset(cam);
+ if (ret)
+ goto out;
+ chip.match_chip = cam->sensor->addr;
+ ret = __cafe_cam_cmd(cam, VIDIOC_G_CHIP_IDENT, &chip);
+ if (ret)
+ goto out;
+ cam->sensor_type = chip.ident;
+// if (cam->sensor->addr != OV7xx0_SID) {
+ if (cam->sensor_type != V4L2_IDENT_OV7670) {
+ cam_err(cam, "Unsupported sensor type %d", cam->sensor->addr);
+ ret = -EINVAL;
+ goto out;
+ }
+/* Get/set parameters? */
+ ret = 0;
+ cam->state = S_IDLE;
+ out:
+ cafe_ctlr_power_down(cam);
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+/*
+ * Configure the sensor to match the parameters we have. Caller should
+ * hold s_mutex
+ */
+static int cafe_cam_set_flip(struct cafe_camera *cam)
+{
+ struct v4l2_control ctrl;
+
+ memset(&ctrl, 0, sizeof(ctrl));
+ ctrl.id = V4L2_CID_VFLIP;
+ ctrl.value = flip;
+ return __cafe_cam_cmd(cam, VIDIOC_S_CTRL, &ctrl);
+}
+
+
+static int cafe_cam_configure(struct cafe_camera *cam)
+{
+ struct v4l2_format fmt;
+ int ret, zero = 0;
+
+ fmt.fmt.pix = cam->pix_format;
+ ret = __cafe_cam_cmd(cam, VIDIOC_INT_INIT, &zero);
+ if (ret == 0)
+ ret = __cafe_cam_cmd(cam, VIDIOC_S_FMT, &fmt);
+ /*
+ * OV7670 does weird things if flip is set *before* format...
+ */
+ ret += cafe_cam_set_flip(cam);
+ return ret;
+}
+
+/* -------------------------------------------------------------------- */
+/*
+ * DMA buffer management. These functions need s_mutex held.
+ */
+
+/* FIXME: this is inefficient as hell, since dma_alloc_coherent just
+ * does a get_free_pages() call, and we waste a good chunk of an orderN
+ * allocation. Should try to allocate the whole set in one chunk.
+ */
+static int cafe_alloc_dma_bufs(struct cafe_camera *cam, int loadtime)
+{
+ int i;
+
+ cafe_set_config_needed(cam, 1);
+ if (loadtime)
+ cam->dma_buf_size = dma_buf_size;
+ else
+ cam->dma_buf_size = cam->pix_format.sizeimage;
+ if (n_dma_bufs > 3)
+ n_dma_bufs = 3;
+
+ cam->nbufs = 0;
+ for (i = 0; i < n_dma_bufs; i++) {
+ cam->dma_bufs[i] = dma_alloc_coherent(&cam->pdev->dev,
+ cam->dma_buf_size, cam->dma_handles + i,
+ GFP_KERNEL);
+ if (cam->dma_bufs[i] == NULL) {
+ cam_warn(cam, "Failed to allocate DMA buffer\n");
+ break;
+ }
+ /* For debug, remove eventually */
+ memset(cam->dma_bufs[i], 0xcc, cam->dma_buf_size);
+ (cam->nbufs)++;
+ }
+
+ switch (cam->nbufs) {
+ case 1:
+ dma_free_coherent(&cam->pdev->dev, cam->dma_buf_size,
+ cam->dma_bufs[0], cam->dma_handles[0]);
+ cam->nbufs = 0;
+ case 0:
+ cam_err(cam, "Insufficient DMA buffers, cannot operate\n");
+ return -ENOMEM;
+
+ case 2:
+ if (n_dma_bufs > 2)
+ cam_warn(cam, "Will limp along with only 2 buffers\n");
+ break;
+ }
+ return 0;
+}
+
+static void cafe_free_dma_bufs(struct cafe_camera *cam)
+{
+ int i;
+
+ for (i = 0; i < cam->nbufs; i++) {
+ dma_free_coherent(&cam->pdev->dev, cam->dma_buf_size,
+ cam->dma_bufs[i], cam->dma_handles[i]);
+ cam->dma_bufs[i] = NULL;
+ }
+ cam->nbufs = 0;
+}
+
+
+
+
+
+/* ----------------------------------------------------------------------- */
+/*
+ * Here starts the V4L2 interface code.
+ */
+
+/*
+ * Read an image from the device.
+ */
+static ssize_t cafe_deliver_buffer(struct cafe_camera *cam,
+ char __user *buffer, size_t len, loff_t *pos)
+{
+ int bufno;
+ unsigned long flags;
+
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ if (cam->next_buf < 0) {
+ cam_err(cam, "deliver_buffer: No next buffer\n");
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ return -EIO;
+ }
+ bufno = cam->next_buf;
+ clear_bit(bufno, &cam->flags);
+ if (++(cam->next_buf) >= cam->nbufs)
+ cam->next_buf = 0;
+ if (! test_bit(cam->next_buf, &cam->flags))
+ cam->next_buf = -1;
+ cam->specframes = 0;
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+
+ if (len > cam->pix_format.sizeimage)
+ len = cam->pix_format.sizeimage;
+ if (copy_to_user(buffer, cam->dma_bufs[bufno], len))
+ return -EFAULT;
+ (*pos) += len;
+ return len;
+}
+
+/*
+ * Get everything ready, and start grabbing frames.
+ */
+static int cafe_read_setup(struct cafe_camera *cam, enum cafe_state state)
+{
+ int ret;
+ unsigned long flags;
+
+ /*
+ * Configuration. If we still don't have DMA buffers,
+ * make one last, desperate attempt.
+ */
+ if (cam->nbufs == 0)
+ if (cafe_alloc_dma_bufs(cam, 0))
+ return -ENOMEM;
+
+ if (cafe_needs_config(cam)) {
+ cafe_cam_configure(cam);
+ ret = cafe_ctlr_configure(cam);
+ if (ret)
+ return ret;
+ }
+
+ /*
+ * Turn it loose.
+ */
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ cafe_reset_buffers(cam);
+ cafe_ctlr_irq_enable(cam);
+ cam->state = state;
+ cafe_ctlr_start(cam);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ return 0;
+}
+
+
+static ssize_t cafe_v4l_read(struct file *filp,
+ char __user *buffer, size_t len, loff_t *pos)
+{
+ struct cafe_camera *cam = filp->private_data;
+ int ret = 0;
+
+ /*
+ * Perhaps we're in speculative read mode and already
+ * have data?
+ */
+ mutex_lock(&cam->s_mutex);
+ if (cam->state == S_SPECREAD) {
+ if (cam->next_buf >= 0) {
+ ret = cafe_deliver_buffer(cam, buffer, len, pos);
+ if (ret != 0)
+ goto out_unlock;
+ }
+ } else if (cam->state == S_FLAKED || cam->state == S_NOTREADY) {
+ ret = -EIO;
+ goto out_unlock;
+ } else if (cam->state != S_IDLE) {
+ ret = -EBUSY;
+ goto out_unlock;
+ }
+
+ /*
+ * v4l2: multiple processes can open the device, but only
+ * one gets to grab data from it.
+ */
+ if (cam->owner && cam->owner != filp) {
+ ret = -EBUSY;
+ goto out_unlock;
+ }
+ cam->owner = filp;
+
+ /*
+ * Do setup if need be.
+ */
+ if (cam->state != S_SPECREAD) {
+ ret = cafe_read_setup(cam, S_SINGLEREAD);
+ if (ret)
+ goto out_unlock;
+ }
+ /*
+ * Wait for something to happen. This should probably
+ * be interruptible (FIXME).
+ */
+ wait_event_timeout(cam->iowait, cam->next_buf >= 0, HZ);
+ if (cam->next_buf < 0) {
+ cam_err(cam, "read() operation timed out\n");
+ cafe_ctlr_stop_dma(cam);
+ ret = -EIO;
+ goto out_unlock;
+ }
+ /*
+ * Give them their data and we should be done.
+ */
+ ret = cafe_deliver_buffer(cam, buffer, len, pos);
+
+ out_unlock:
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+
+
+
+
+
+
+
+/*
+ * Streaming I/O support.
+ */
+
+
+
+static int cafe_vidioc_streamon(struct file *filp, void *priv,
+ enum v4l2_buf_type type)
+{
+ struct cafe_camera *cam = filp->private_data;
+ int ret = -EINVAL;
+
+ if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ goto out;
+ mutex_lock(&cam->s_mutex);
+ if (cam->state != S_IDLE || cam->n_sbufs == 0)
+ goto out_unlock;
+
+ cam->sequence = 0;
+ ret = cafe_read_setup(cam, S_STREAMING);
+
+ out_unlock:
+ mutex_unlock(&cam->s_mutex);
+ out:
+ return ret;
+}
+
+
+static int cafe_vidioc_streamoff(struct file *filp, void *priv,
+ enum v4l2_buf_type type)
+{
+ struct cafe_camera *cam = filp->private_data;
+ int ret = -EINVAL;
+
+ if (type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ goto out;
+ mutex_lock(&cam->s_mutex);
+ if (cam->state != S_STREAMING)
+ goto out_unlock;
+
+ cafe_ctlr_stop_dma(cam);
+ ret = 0;
+
+ out_unlock:
+ mutex_unlock(&cam->s_mutex);
+ out:
+ return ret;
+}
+
+
+
+static int cafe_setup_siobuf(struct cafe_camera *cam, int index)
+{
+ struct cafe_sio_buffer *buf = cam->sb_bufs + index;
+
+ INIT_LIST_HEAD(&buf->list);
+ buf->v4lbuf.length = PAGE_ALIGN(cam->pix_format.sizeimage);
+ buf->buffer = vmalloc_user(buf->v4lbuf.length);
+ if (buf->buffer == NULL)
+ return -ENOMEM;
+ buf->mapcount = 0;
+ buf->cam = cam;
+
+ buf->v4lbuf.index = index;
+ buf->v4lbuf.type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+ buf->v4lbuf.field = V4L2_FIELD_NONE;
+ buf->v4lbuf.memory = V4L2_MEMORY_MMAP;
+ /*
+ * Offset: must be 32-bit even on a 64-bit system. video-buf
+ * just uses the length times the index, but the spec warns
+ * against doing just that - vma merging problems. So we
+ * leave a gap between each pair of buffers.
+ */
+ buf->v4lbuf.m.offset = 2*index*buf->v4lbuf.length;
+ return 0;
+}
+
+static int cafe_free_sio_buffers(struct cafe_camera *cam)
+{
+ int i;
+
+ /*
+ * If any buffers are mapped, we cannot free them at all.
+ */
+ for (i = 0; i < cam->n_sbufs; i++)
+ if (cam->sb_bufs[i].mapcount > 0)
+ return -EBUSY;
+ /*
+ * OK, let's do it.
+ */
+ for (i = 0; i < cam->n_sbufs; i++)
+ vfree(cam->sb_bufs[i].buffer);
+ cam->n_sbufs = 0;
+ kfree(cam->sb_bufs);
+ cam->sb_bufs = NULL;
+ INIT_LIST_HEAD(&cam->sb_avail);
+ INIT_LIST_HEAD(&cam->sb_full);
+ return 0;
+}
+
+
+
+static int cafe_vidioc_reqbufs(struct file *filp, void *priv,
+ struct v4l2_requestbuffers *req)
+{
+ struct cafe_camera *cam = filp->private_data;
+ int ret = 0; /* Silence warning */
+
+ /*
+ * Make sure it's something we can do. User pointers could be
+ * implemented without great pain, but that's not been done yet.
+ */
+ if (req->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ return -EINVAL;
+ if (req->memory != V4L2_MEMORY_MMAP)
+ return -EINVAL;
+ /*
+ * If they ask for zero buffers, they really want us to stop streaming
+ * (if it's happening) and free everything. Should we check owner?
+ */
+ mutex_lock(&cam->s_mutex);
+ if (req->count == 0) {
+ if (cam->state == S_STREAMING)
+ cafe_ctlr_stop_dma(cam);
+ ret = cafe_free_sio_buffers (cam);
+ goto out;
+ }
+ /*
+ * Device needs to be idle and working. We *could* try to do the
+ * right thing in S_SPECREAD by shutting things down, but it
+ * probably doesn't matter.
+ */
+ if (cam->state != S_IDLE || (cam->owner && cam->owner != filp)) {
+ ret = -EBUSY;
+ goto out;
+ }
+ cam->owner = filp;
+
+ if (req->count < min_buffers)
+ req->count = min_buffers;
+ else if (req->count > max_buffers)
+ req->count = max_buffers;
+ if (cam->n_sbufs > 0) {
+ ret = cafe_free_sio_buffers(cam);
+ if (ret)
+ goto out;
+ }
+
+ cam->sb_bufs = kzalloc(req->count*sizeof(struct cafe_sio_buffer),
+ GFP_KERNEL);
+ if (cam->sb_bufs == NULL) {
+ ret = -ENOMEM;
+ goto out;
+ }
+ for (cam->n_sbufs = 0; cam->n_sbufs < req->count; (cam->n_sbufs++)) {
+ ret = cafe_setup_siobuf(cam, cam->n_sbufs);
+ if (ret)
+ break;
+ }
+
+ if (cam->n_sbufs == 0) /* no luck at all - ret already set */
+ kfree(cam->sb_bufs);
+ req->count = cam->n_sbufs; /* In case of partial success */
+
+ out:
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+
+static int cafe_vidioc_querybuf(struct file *filp, void *priv,
+ struct v4l2_buffer *buf)
+{
+ struct cafe_camera *cam = filp->private_data;
+ int ret = -EINVAL;
+
+ mutex_lock(&cam->s_mutex);
+ if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ goto out;
+ if (buf->index < 0 || buf->index >= cam->n_sbufs)
+ goto out;
+ *buf = cam->sb_bufs[buf->index].v4lbuf;
+ ret = 0;
+ out:
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+static int cafe_vidioc_qbuf(struct file *filp, void *priv,
+ struct v4l2_buffer *buf)
+{
+ struct cafe_camera *cam = filp->private_data;
+ struct cafe_sio_buffer *sbuf;
+ int ret = -EINVAL;
+ unsigned long flags;
+
+ mutex_lock(&cam->s_mutex);
+ if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ goto out;
+ if (buf->index < 0 || buf->index >= cam->n_sbufs)
+ goto out;
+ sbuf = cam->sb_bufs + buf->index;
+ if (sbuf->v4lbuf.flags & V4L2_BUF_FLAG_QUEUED) {
+ ret = 0; /* Already queued?? */
+ goto out;
+ }
+ if (sbuf->v4lbuf.flags & V4L2_BUF_FLAG_DONE) {
+ /* Spec doesn't say anything, seems appropriate tho */
+ ret = -EBUSY;
+ goto out;
+ }
+ sbuf->v4lbuf.flags |= V4L2_BUF_FLAG_QUEUED;
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ list_add(&sbuf->list, &cam->sb_avail);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ ret = 0;
+ out:
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+static int cafe_vidioc_dqbuf(struct file *filp, void *priv,
+ struct v4l2_buffer *buf)
+{
+ struct cafe_camera *cam = filp->private_data;
+ struct cafe_sio_buffer *sbuf;
+ int ret = -EINVAL;
+ unsigned long flags;
+
+ mutex_lock(&cam->s_mutex);
+ if (buf->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ goto out_unlock;
+ if (cam->state != S_STREAMING)
+ goto out_unlock;
+ if (list_empty(&cam->sb_full) && filp->f_flags & O_NONBLOCK) {
+ ret = -EAGAIN;
+ goto out_unlock;
+ }
+
+ while (list_empty(&cam->sb_full) && cam->state == S_STREAMING) {
+ mutex_unlock(&cam->s_mutex);
+ if (wait_event_interruptible(cam->iowait,
+ !list_empty(&cam->sb_full))) {
+ ret = -ERESTARTSYS;
+ goto out;
+ }
+ mutex_lock(&cam->s_mutex);
+ }
+
+ if (cam->state != S_STREAMING)
+ ret = -EINTR;
+ else {
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ /* Should probably recheck !list_empty() here */
+ sbuf = list_entry(cam->sb_full.next,
+ struct cafe_sio_buffer, list);
+ list_del_init(&sbuf->list);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ sbuf->v4lbuf.flags &= ~V4L2_BUF_FLAG_DONE;
+ *buf = sbuf->v4lbuf;
+ ret = 0;
+ }
+
+ out_unlock:
+ mutex_unlock(&cam->s_mutex);
+ out:
+ return ret;
+}
+
+
+
+static void cafe_v4l_vm_open(struct vm_area_struct *vma)
+{
+ struct cafe_sio_buffer *sbuf = vma->vm_private_data;
+ /*
+ * Locking: done under mmap_sem, so we don't need to
+ * go back to the camera lock here.
+ */
+ sbuf->mapcount++;
+}
+
+
+static void cafe_v4l_vm_close(struct vm_area_struct *vma)
+{
+ struct cafe_sio_buffer *sbuf = vma->vm_private_data;
+
+ mutex_lock(&sbuf->cam->s_mutex);
+ sbuf->mapcount--;
+ /* Docs say we should stop I/O too... */
+ if (sbuf->mapcount == 0)
+ sbuf->v4lbuf.flags &= ~V4L2_BUF_FLAG_MAPPED;
+ mutex_unlock(&sbuf->cam->s_mutex);
+}
+
+static struct vm_operations_struct cafe_v4l_vm_ops = {
+ .open = cafe_v4l_vm_open,
+ .close = cafe_v4l_vm_close
+};
+
+
+static int cafe_v4l_mmap(struct file *filp, struct vm_area_struct *vma)
+{
+ struct cafe_camera *cam = filp->private_data;
+ unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
+ int ret = -EINVAL;
+ int i;
+ struct cafe_sio_buffer *sbuf = NULL;
+
+ if (! (vma->vm_flags & VM_WRITE) || ! (vma->vm_flags & VM_SHARED))
+ return -EINVAL;
+ /*
+ * Find the buffer they are looking for.
+ */
+ mutex_lock(&cam->s_mutex);
+ for (i = 0; i < cam->n_sbufs; i++)
+ if (cam->sb_bufs[i].v4lbuf.m.offset == offset) {
+ sbuf = cam->sb_bufs + i;
+ break;
+ }
+ if (sbuf == NULL)
+ goto out;
+
+ ret = remap_vmalloc_range(vma, sbuf->buffer, 0);
+ if (ret)
+ goto out;
+ vma->vm_flags |= VM_DONTEXPAND;
+ vma->vm_private_data = sbuf;
+ vma->vm_ops = &cafe_v4l_vm_ops;
+ sbuf->v4lbuf.flags |= V4L2_BUF_FLAG_MAPPED;
+ cafe_v4l_vm_open(vma);
+ ret = 0;
+ out:
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+
+
+static int cafe_v4l_open(struct inode *inode, struct file *filp)
+{
+ struct cafe_camera *cam;
+
+ cam = cafe_find_dev(iminor(inode));
+ if (cam == NULL)
+ return -ENODEV;
+ filp->private_data = cam;
+
+ mutex_lock(&cam->s_mutex);
+ if (cam->users == 0) {
+ cafe_ctlr_power_up(cam);
+ __cafe_cam_reset(cam);
+ cafe_set_config_needed(cam, 1);
+ /* FIXME make sure this is complete */
+ }
+ (cam->users)++;
+ mutex_unlock(&cam->s_mutex);
+ return 0;
+}
+
+
+static int cafe_v4l_release(struct inode *inode, struct file *filp)
+{
+ struct cafe_camera *cam = filp->private_data;
+
+ mutex_lock(&cam->s_mutex);
+ (cam->users)--;
+ if (filp == cam->owner) {
+ cafe_ctlr_stop_dma(cam);
+ cafe_free_sio_buffers(cam);
+ cam->owner = NULL;
+ }
+ if (cam->users == 0) {
+ cafe_ctlr_power_down(cam);
+ if (alloc_bufs_at_read)
+ cafe_free_dma_bufs(cam);
+ }
+ mutex_unlock(&cam->s_mutex);
+ return 0;
+}
+
+
+
+static unsigned int cafe_v4l_poll(struct file *filp,
+ struct poll_table_struct *pt)
+{
+ struct cafe_camera *cam = filp->private_data;
+
+ poll_wait(filp, &cam->iowait, pt);
+ if (cam->next_buf >= 0)
+ return POLLIN | POLLRDNORM;
+ return 0;
+}
+
+
+
+static int cafe_vidioc_queryctrl(struct file *filp, void *priv,
+ struct v4l2_queryctrl *qc)
+{
+ struct cafe_camera *cam = filp->private_data;
+ int ret;
+
+ mutex_lock(&cam->s_mutex);
+ ret = __cafe_cam_cmd(cam, VIDIOC_QUERYCTRL, qc);
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+
+static int cafe_vidioc_g_ctrl(struct file *filp, void *priv,
+ struct v4l2_control *ctrl)
+{
+ struct cafe_camera *cam = filp->private_data;
+ int ret;
+
+ mutex_lock(&cam->s_mutex);
+ ret = __cafe_cam_cmd(cam, VIDIOC_G_CTRL, ctrl);
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+
+static int cafe_vidioc_s_ctrl(struct file *filp, void *priv,
+ struct v4l2_control *ctrl)
+{
+ struct cafe_camera *cam = filp->private_data;
+ int ret;
+
+ mutex_lock(&cam->s_mutex);
+ ret = __cafe_cam_cmd(cam, VIDIOC_S_CTRL, ctrl);
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+
+
+
+
+static int cafe_vidioc_querycap(struct file *file, void *priv,
+ struct v4l2_capability *cap)
+{
+ strcpy(cap->driver, "cafe_ccic");
+ strcpy(cap->card, "cafe_ccic");
+ cap->version = CAFE_VERSION;
+ cap->capabilities = V4L2_CAP_VIDEO_CAPTURE |
+ V4L2_CAP_READWRITE | V4L2_CAP_STREAMING;
+ return 0;
+}
+
+
+/*
+ * The default format we use until somebody says otherwise.
+ */
+static struct v4l2_pix_format cafe_def_pix_format = {
+ .width = VGA_WIDTH,
+ .height = VGA_HEIGHT,
+ .pixelformat = V4L2_PIX_FMT_YUYV,
+ .field = V4L2_FIELD_NONE,
+ .bytesperline = VGA_WIDTH*2,
+ .sizeimage = VGA_WIDTH*VGA_HEIGHT*2,
+};
+
+static int cafe_vidioc_enum_fmt_cap(struct file *filp,
+ void *priv, struct v4l2_fmtdesc *fmt)
+{
+ struct cafe_camera *cam = priv;
+ int ret;
+
+ if (fmt->type != V4L2_BUF_TYPE_VIDEO_CAPTURE)
+ return -EINVAL;
+ mutex_lock(&cam->s_mutex);
+ ret = __cafe_cam_cmd(cam, VIDIOC_ENUM_FMT, fmt);
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+
+static int cafe_vidioc_try_fmt_cap (struct file *filp, void *priv,
+ struct v4l2_format *fmt)
+{
+ struct cafe_camera *cam = priv;
+ int ret;
+
+ mutex_lock(&cam->s_mutex);
+ ret = __cafe_cam_cmd(cam, VIDIOC_TRY_FMT, fmt);
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+static int cafe_vidioc_s_fmt_cap(struct file *filp, void *priv,
+ struct v4l2_format *fmt)
+{
+ struct cafe_camera *cam = priv;
+ int ret;
+
+ /*
+ * Can't do anything if the device is not idle
+ * Also can't if there are streaming buffers in place.
+ */
+ if (cam->state != S_IDLE || cam->n_sbufs > 0)
+ return -EBUSY;
+ /*
+ * See if the formatting works in principle.
+ */
+ ret = cafe_vidioc_try_fmt_cap(filp, priv, fmt);
+ if (ret)
+ return ret;
+ /*
+ * Now we start to change things for real, so let's do it
+ * under lock.
+ */
+ mutex_lock(&cam->s_mutex);
+ cam->pix_format = fmt->fmt.pix;
+ /*
+ * Make sure we have appropriate DMA buffers.
+ */
+ ret = -ENOMEM;
+ if (cam->nbufs > 0 && cam->dma_buf_size < cam->pix_format.sizeimage)
+ cafe_free_dma_bufs(cam);
+ if (cam->nbufs == 0) {
+ if (cafe_alloc_dma_bufs(cam, 0))
+ goto out;
+ }
+ /*
+ * It looks like this might work, so let's program the sensor.
+ */
+ ret = cafe_cam_configure(cam);
+ if (! ret)
+ ret = cafe_ctlr_configure(cam);
+ out:
+ mutex_unlock(&cam->s_mutex);
+ return ret;
+}
+
+/*
+ * Return our stored notion of how the camera is/should be configured.
+ * The V4l2 spec wants us to be smarter, and actually get this from
+ * the camera (and not mess with it at open time). Someday.
+ */
+static int cafe_vidioc_g_fmt_cap(struct file *filp, void *priv,
+ struct v4l2_format *f)
+{
+ struct cafe_camera *cam = priv;
+
+ f->fmt.pix = cam->pix_format;
+ return 0;
+}
+
+/*
+ * We only have one input - the sensor - so minimize the nonsense here.
+ */
+static int cafe_vidioc_enum_input(struct file *filp, void *priv,
+ struct v4l2_input *input)
+{
+ if (input->index != 0)
+ return -EINVAL;
+
+ input->type = V4L2_INPUT_TYPE_CAMERA;
+ input->std = V4L2_STD_ALL; /* Not sure what should go here */
+ strcpy(input->name, "Camera");
+ return 0;
+}
+
+static int cafe_vidioc_g_input(struct file *filp, void *priv, unsigned int *i)
+{
+ *i = 0;
+ return 0;
+}
+
+static int cafe_vidioc_s_input(struct file *filp, void *priv, unsigned int i)
+{
+ if (i != 0)
+ return -EINVAL;
+ return 0;
+}
+
+/* from vivi.c */
+static int cafe_vidioc_s_std(struct file *filp, void *priv, v4l2_std_id *a)
+{
+ return 0;
+}
+
+/*
+ * G/S_PARM. Most of this is done by the sensor, but we are
+ * the level which controls the number of read buffers.
+ */
+static int cafe_vidioc_g_parm(struct file *filp, void *priv,
+ struct v4l2_streamparm *parms)
+{
+ struct cafe_camera *cam = priv;
+ int ret;
+
+ mutex_lock(&cam->s_mutex);
+ ret = __cafe_cam_cmd(cam, VIDIOC_G_PARM, parms);
+ mutex_unlock(&cam->s_mutex);
+ parms->parm.capture.readbuffers = n_dma_bufs;
+ return ret;
+}
+
+static int cafe_vidioc_s_parm(struct file *filp, void *priv,
+ struct v4l2_streamparm *parms)
+{
+ struct cafe_camera *cam = priv;
+ int ret;
+
+ mutex_lock(&cam->s_mutex);
+ ret = __cafe_cam_cmd(cam, VIDIOC_S_PARM, parms);
+ mutex_unlock(&cam->s_mutex);
+ parms->parm.capture.readbuffers = n_dma_bufs;
+ return ret;
+}
+
+
+static void cafe_v4l_dev_release(struct video_device *vd)
+{
+ struct cafe_camera *cam = container_of(vd, struct cafe_camera, v4ldev);
+
+ kfree(cam);
+}
+
+
+/*
+ * This template device holds all of those v4l2 methods; we
+ * clone it for specific real devices.
+ */
+
+static const struct file_operations cafe_v4l_fops = {
+ .owner = THIS_MODULE,
+ .open = cafe_v4l_open,
+ .release = cafe_v4l_release,
+ .read = cafe_v4l_read,
+ .poll = cafe_v4l_poll,
+ .mmap = cafe_v4l_mmap,
+ .ioctl = video_ioctl2,
+ .llseek = no_llseek,
+};
+
+static struct video_device cafe_v4l_template = {
+ .name = "cafe",
+ .type = VFL_TYPE_GRABBER,
+ .type2 = VID_TYPE_CAPTURE,
+ .minor = -1, /* Get one dynamically */
+ .tvnorms = V4L2_STD_NTSC_M,
+ .current_norm = V4L2_STD_NTSC_M, /* make mplayer happy */
+
+ .fops = &cafe_v4l_fops,
+ .release = cafe_v4l_dev_release,
+
+ .vidioc_querycap = cafe_vidioc_querycap,
+ .vidioc_enum_fmt_cap = cafe_vidioc_enum_fmt_cap,
+ .vidioc_try_fmt_cap = cafe_vidioc_try_fmt_cap,
+ .vidioc_s_fmt_cap = cafe_vidioc_s_fmt_cap,
+ .vidioc_g_fmt_cap = cafe_vidioc_g_fmt_cap,
+ .vidioc_enum_input = cafe_vidioc_enum_input,
+ .vidioc_g_input = cafe_vidioc_g_input,
+ .vidioc_s_input = cafe_vidioc_s_input,
+ .vidioc_s_std = cafe_vidioc_s_std,
+ .vidioc_reqbufs = cafe_vidioc_reqbufs,
+ .vidioc_querybuf = cafe_vidioc_querybuf,
+ .vidioc_qbuf = cafe_vidioc_qbuf,
+ .vidioc_dqbuf = cafe_vidioc_dqbuf,
+ .vidioc_streamon = cafe_vidioc_streamon,
+ .vidioc_streamoff = cafe_vidioc_streamoff,
+ .vidioc_queryctrl = cafe_vidioc_queryctrl,
+ .vidioc_g_ctrl = cafe_vidioc_g_ctrl,
+ .vidioc_s_ctrl = cafe_vidioc_s_ctrl,
+ .vidioc_g_parm = cafe_vidioc_g_parm,
+ .vidioc_s_parm = cafe_vidioc_s_parm,
+};
+
+
+
+
+
+
+
+/* ---------------------------------------------------------------------- */
+/*
+ * Interrupt handler stuff
+ */
+
+
+
+static void cafe_frame_tasklet(unsigned long data)
+{
+ struct cafe_camera *cam = (struct cafe_camera *) data;
+ int i;
+ unsigned long flags;
+ struct cafe_sio_buffer *sbuf;
+
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ for (i = 0; i < cam->nbufs; i++) {
+ int bufno = cam->next_buf;
+ if (bufno < 0) { /* "will never happen" */
+ cam_err(cam, "No valid bufs in tasklet!\n");
+ break;
+ }
+ if (++(cam->next_buf) >= cam->nbufs)
+ cam->next_buf = 0;
+ if (! test_bit(bufno, &cam->flags))
+ continue;
+ if (list_empty(&cam->sb_avail))
+ break; /* Leave it valid, hope for better later */
+ clear_bit(bufno, &cam->flags);
+ sbuf = list_entry(cam->sb_avail.next,
+ struct cafe_sio_buffer, list);
+ /*
+ * Drop the lock during the big copy. This *should* be safe...
+ */
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+ memcpy(sbuf->buffer, cam->dma_bufs[bufno],
+ cam->pix_format.sizeimage);
+ sbuf->v4lbuf.bytesused = cam->pix_format.sizeimage;
+ sbuf->v4lbuf.sequence = cam->buf_seq[bufno];
+ sbuf->v4lbuf.flags &= ~V4L2_BUF_FLAG_QUEUED;
+ sbuf->v4lbuf.flags |= V4L2_BUF_FLAG_DONE;
+ spin_lock_irqsave(&cam->dev_lock, flags);
+ list_move_tail(&sbuf->list, &cam->sb_full);
+ }
+ if (! list_empty(&cam->sb_full))
+ wake_up(&cam->iowait);
+ spin_unlock_irqrestore(&cam->dev_lock, flags);
+}
+
+
+
+static void cafe_frame_complete(struct cafe_camera *cam, int frame)
+{
+ /*
+ * Basic frame housekeeping.
+ */
+ if (test_bit(frame, &cam->flags) && printk_ratelimit())
+ cam_err(cam, "Frame overrun on %d, frames lost\n", frame);
+ set_bit(frame, &cam->flags);
+ clear_bit(CF_DMA_ACTIVE, &cam->flags);
+ if (cam->next_buf < 0)
+ cam->next_buf = frame;
+ cam->buf_seq[frame] = ++(cam->sequence);
+
+ switch (cam->state) {
+ /*
+ * If in single read mode, try going speculative.
+ */
+ case S_SINGLEREAD:
+ cam->state = S_SPECREAD;
+ cam->specframes = 0;
+ wake_up(&cam->iowait);
+ break;
+
+ /*
+ * If we are already doing speculative reads, and nobody is
+ * reading them, just stop.
+ */
+ case S_SPECREAD:
+ if (++(cam->specframes) >= cam->nbufs) {
+ cafe_ctlr_stop(cam);
+ cafe_ctlr_irq_disable(cam);
+ cam->state = S_IDLE;
+ }
+ wake_up(&cam->iowait);
+ break;
+ /*
+ * For the streaming case, we defer the real work to the
+ * camera tasklet.
+ *
+ * FIXME: if the application is not consuming the buffers,
+ * we should eventually put things on hold and restart in
+ * vidioc_dqbuf().
+ */
+ case S_STREAMING:
+ tasklet_schedule(&cam->s_tasklet);
+ break;
+
+ default:
+ cam_err(cam, "Frame interrupt in non-operational state\n");
+ break;
+ }
+}
+
+
+
+
+static void cafe_frame_irq(struct cafe_camera *cam, unsigned int irqs)
+{
+ unsigned int frame;
+
+ cafe_reg_write(cam, REG_IRQSTAT, FRAMEIRQS); /* Clear'em all */
+ /*
+ * Handle any frame completions. There really should
+ * not be more than one of these, or we have fallen
+ * far behind.
+ */
+ for (frame = 0; frame < cam->nbufs; frame++)
+ if (irqs & (IRQ_EOF0 << frame))
+ cafe_frame_complete(cam, frame);
+ /*
+ * If a frame starts, note that we have DMA active. This
+ * code assumes that we won't get multiple frame interrupts
+ * at once; may want to rethink that.
+ */
+ if (irqs & (IRQ_SOF0 | IRQ_SOF1 | IRQ_SOF2))
+ set_bit(CF_DMA_ACTIVE, &cam->flags);
+}
+
+
+
+static irqreturn_t cafe_irq(int irq, void *data)
+{
+ struct cafe_camera *cam = data;
+ unsigned int irqs;
+
+ spin_lock(&cam->dev_lock);
+ irqs = cafe_reg_read(cam, REG_IRQSTAT);
+ if ((irqs & ALLIRQS) == 0) {
+ spin_unlock(&cam->dev_lock);
+ return IRQ_NONE;
+ }
+ if (irqs & FRAMEIRQS)
+ cafe_frame_irq(cam, irqs);
+ if (irqs & TWSIIRQS) {
+ cafe_reg_write(cam, REG_IRQSTAT, TWSIIRQS);
+ wake_up(&cam->smbus_wait);
+ }
+ spin_unlock(&cam->dev_lock);
+ return IRQ_HANDLED;
+}
+
+
+/* -------------------------------------------------------------------------- */
+#ifdef CONFIG_VIDEO_ADV_DEBUG
+/*
+ * Debugfs stuff.
+ */
+
+static char cafe_debug_buf[1024];
+static struct dentry *cafe_dfs_root;
+
+static void cafe_dfs_setup(void)
+{
+ cafe_dfs_root = debugfs_create_dir("cafe_ccic", NULL);
+ if (IS_ERR(cafe_dfs_root)) {
+ cafe_dfs_root = NULL; /* Never mind */
+ printk(KERN_NOTICE "cafe_ccic unable to set up debugfs\n");
+ }
+}
+
+static void cafe_dfs_shutdown(void)
+{
+ if (cafe_dfs_root)
+ debugfs_remove(cafe_dfs_root);
+}
+
+static int cafe_dfs_open(struct inode *inode, struct file *file)
+{
+ file->private_data = inode->i_private;
+ return 0;
+}
+
+static ssize_t cafe_dfs_read_regs(struct file *file,
+ char __user *buf, size_t count, loff_t *ppos)
+{
+ struct cafe_camera *cam = file->private_data;
+ char *s = cafe_debug_buf;
+ int offset;
+
+ for (offset = 0; offset < 0x44; offset += 4)
+ s += sprintf(s, "%02x: %08x\n", offset,
+ cafe_reg_read(cam, offset));
+ for (offset = 0x88; offset <= 0x90; offset += 4)
+ s += sprintf(s, "%02x: %08x\n", offset,
+ cafe_reg_read(cam, offset));
+ for (offset = 0xb4; offset <= 0xbc; offset += 4)
+ s += sprintf(s, "%02x: %08x\n", offset,
+ cafe_reg_read(cam, offset));
+ for (offset = 0x3000; offset <= 0x300c; offset += 4)
+ s += sprintf(s, "%04x: %08x\n", offset,
+ cafe_reg_read(cam, offset));
+ return simple_read_from_buffer(buf, count, ppos, cafe_debug_buf,
+ s - cafe_debug_buf);
+}
+
+static const struct file_operations cafe_dfs_reg_ops = {
+ .owner = THIS_MODULE,
+ .read = cafe_dfs_read_regs,
+ .open = cafe_dfs_open
+};
+
+static ssize_t cafe_dfs_read_cam(struct file *file,
+ char __user *buf, size_t count, loff_t *ppos)
+{
+ struct cafe_camera *cam = file->private_data;
+ char *s = cafe_debug_buf;
+ int offset;
+
+ if (! cam->sensor)
+ return -EINVAL;
+ for (offset = 0x0; offset < 0x8a; offset++)
+ {
+ u8 v;
+
+ cafe_smbus_read_data(cam, cam->sensor->addr, offset, &v);
+ s += sprintf(s, "%02x: %02x\n", offset, v);
+ }
+ return simple_read_from_buffer(buf, count, ppos, cafe_debug_buf,
+ s - cafe_debug_buf);
+}
+
+static const struct file_operations cafe_dfs_cam_ops = {
+ .owner = THIS_MODULE,
+ .read = cafe_dfs_read_cam,
+ .open = cafe_dfs_open
+};
+
+
+
+static void cafe_dfs_cam_setup(struct cafe_camera *cam)
+{
+ char fname[40];
+
+ if (!cafe_dfs_root)
+ return;
+ sprintf(fname, "regs-%d", cam->v4ldev.minor);
+ cam->dfs_regs = debugfs_create_file(fname, 0444, cafe_dfs_root,
+ cam, &cafe_dfs_reg_ops);
+ sprintf(fname, "cam-%d", cam->v4ldev.minor);
+ cam->dfs_cam_regs = debugfs_create_file(fname, 0444, cafe_dfs_root,
+ cam, &cafe_dfs_cam_ops);
+}
+
+
+static void cafe_dfs_cam_shutdown(struct cafe_camera *cam)
+{
+ if (! IS_ERR(cam->dfs_regs))
+ debugfs_remove(cam->dfs_regs);
+ if (! IS_ERR(cam->dfs_cam_regs))
+ debugfs_remove(cam->dfs_cam_regs);
+}
+
+#else
+
+#define cafe_dfs_setup()
+#define cafe_dfs_shutdown()
+#define cafe_dfs_cam_setup(cam)
+#define cafe_dfs_cam_shutdown(cam)
+#endif /* CONFIG_VIDEO_ADV_DEBUG */
+
+
+
+
+/* ------------------------------------------------------------------------*/
+/*
+ * PCI interface stuff.
+ */
+
+static int cafe_pci_probe(struct pci_dev *pdev,
+ const struct pci_device_id *id)
+{
+ int ret;
+ u16 classword;
+ struct cafe_camera *cam;
+ /*
+ * Make sure we have a camera here - we'll get calls for
+ * the other cafe devices as well.
+ */
+ pci_read_config_word(pdev, PCI_CLASS_DEVICE, &classword);
+ if (classword != PCI_CLASS_MULTIMEDIA_VIDEO)
+ return -ENODEV;
+ /*
+ * Start putting together one of our big camera structures.
+ */
+ ret = -ENOMEM;
+ cam = kzalloc(sizeof(struct cafe_camera), GFP_KERNEL);
+ if (cam == NULL)
+ goto out;
+ mutex_init(&cam->s_mutex);
+ mutex_lock(&cam->s_mutex);
+ spin_lock_init(&cam->dev_lock);
+ cam->state = S_NOTREADY;
+ cafe_set_config_needed(cam, 1);
+ init_waitqueue_head(&cam->smbus_wait);
+ init_waitqueue_head(&cam->iowait);
+ cam->pdev = pdev;
+ cam->pix_format = cafe_def_pix_format;
+ INIT_LIST_HEAD(&cam->dev_list);
+ INIT_LIST_HEAD(&cam->sb_avail);
+ INIT_LIST_HEAD(&cam->sb_full);
+ tasklet_init(&cam->s_tasklet, cafe_frame_tasklet, (unsigned long) cam);
+ /*
+ * Get set up on the PCI bus.
+ */
+ ret = pci_enable_device(pdev);
+ if (ret)
+ goto out_free;
+ pci_set_master(pdev);
+
+ ret = -EIO;
+ cam->regs = pci_iomap(pdev, 0, 0);
+ if (! cam->regs) {
+ printk(KERN_ERR "Unable to ioremap cafe-ccic regs\n");
+ goto out_free;
+ }
+ ret = request_irq(pdev->irq, cafe_irq, IRQF_SHARED, "cafe-ccic", cam);
+ if (ret)
+ goto out_iounmap;
+ /*
+ * Initialize the controller and leave it powered up. It will
+ * stay that way until the sensor driver shows up.
+ */
+ cafe_ctlr_init(cam);
+ cafe_ctlr_power_up(cam);
+ /*
+ * Set up I2C/SMBUS communications. We have to drop the mutex here
+ * because the sensor could attach in this call chain, leading to
+ * unsightly deadlocks.
+ */
+ mutex_unlock(&cam->s_mutex); /* attach can deadlock */
+ ret = cafe_smbus_setup(cam);
+ if (ret)
+ goto out_freeirq;
+ /*
+ * Get the v4l2 setup done.
+ */
+ mutex_lock(&cam->s_mutex);
+ cam->v4ldev = cafe_v4l_template;
+ cam->v4ldev.debug = 0;
+// cam->v4ldev.debug = V4L2_DEBUG_IOCTL_ARG;
+ cam->v4ldev.dev = &pdev->dev;
+ ret = video_register_device(&cam->v4ldev, VFL_TYPE_GRABBER, -1);
+ if (ret)
+ goto out_smbus;
+ /*
+ * If so requested, try to get our DMA buffers now.
+ */
+ if (!alloc_bufs_at_read) {
+ if (cafe_alloc_dma_bufs(cam, 1))
+ cam_warn(cam, "Unable to alloc DMA buffers at load"
+ " will try again later.");
+ }
+
+ cafe_dfs_cam_setup(cam);
+ mutex_unlock(&cam->s_mutex);
+ cafe_add_dev(cam);
+ return 0;
+
+ out_smbus:
+ cafe_smbus_shutdown(cam);
+ out_freeirq:
+ cafe_ctlr_power_down(cam);
+ free_irq(pdev->irq, cam);
+ out_iounmap:
+ pci_iounmap(pdev, cam->regs);
+ out_free:
+ kfree(cam);
+ out:
+ return ret;
+}
+
+
+/*
+ * Shut down an initialized device
+ */
+static void cafe_shutdown(struct cafe_camera *cam)
+{
+/* FIXME: Make sure we take care of everything here */
+ cafe_dfs_cam_shutdown(cam);
+ if (cam->n_sbufs > 0)
+ /* What if they are still mapped? Shouldn't be, but... */
+ cafe_free_sio_buffers(cam);
+ cafe_remove_dev(cam);
+ cafe_ctlr_stop_dma(cam);
+ cafe_ctlr_power_down(cam);
+ cafe_smbus_shutdown(cam);
+ cafe_free_dma_bufs(cam);
+ free_irq(cam->pdev->irq, cam);
+ pci_iounmap(cam->pdev, cam->regs);
+ video_unregister_device(&cam->v4ldev);
+ /* kfree(cam); done in v4l_release () */
+}
+
+
+static void cafe_pci_remove(struct pci_dev *pdev)
+{
+ struct cafe_camera *cam = cafe_find_by_pdev(pdev);
+
+ if (cam == NULL) {
+ printk(KERN_WARNING "pci_remove on unknown pdev %p\n", pdev);
+ return;
+ }
+ mutex_lock(&cam->s_mutex);
+ if (cam->users > 0)
+ cam_warn(cam, "Removing a device with users!\n");
+ cafe_shutdown(cam);
+/* No unlock - it no longer exists */
+}
+
+
+#ifdef CONFIG_PM
+/*
+ * Basic power management.
+ */
+static int cafe_pci_suspend(struct pci_dev *pdev, pm_message_t state)
+{
+ struct cafe_camera *cam = cafe_find_by_pdev(pdev);
+ int ret;
+ enum cafe_state cstate;
+
+ mutex_lock(&cam->s_mutex);
+ ret = pci_save_state(pdev);
+ if (ret) {
+ cam_warn(cam, "Unable to save PCI state\n");
+ return ret;
+ }
+ cstate = cam->state; /* HACK - stop_dma sets to idle */
+ cafe_ctlr_stop_dma(cam);
+ cafe_ctlr_power_down(cam);
+ pci_disable_device(pdev);
+ cam->state = cstate;
+ /* hold mutex until restore */
+ return 0;
+}
+
+
+static int cafe_pci_resume(struct pci_dev *pdev)
+{
+ struct cafe_camera *cam = cafe_find_by_pdev(pdev);
+ int ret = 0;
+
+ ret = pci_restore_state(pdev);
+ if (ret)
+ return ret;
+ ret = pci_enable_device(pdev);
+ if (ret) {
+ cam_warn(cam, "Unable to re-enable device on resume!\n");
+ return ret;
+ }
+ /* we're still holding mutex from suspend */
+ cafe_ctlr_init(cam);
+
+ if (cam->users > 0) {
+ cafe_ctlr_power_up(cam);
+ __cafe_cam_reset(cam);
+ }
+ else
+ cafe_ctlr_power_down(cam);
+ mutex_unlock(&cam->s_mutex);
+
+ set_bit(CF_CONFIG_NEEDED, &cam->flags);
+ if (cam->state == S_SPECREAD)
+ cam->state = S_IDLE; /* Don't bother restarting */
+ else if (cam->state == S_SINGLEREAD || cam->state == S_STREAMING)
+ ret = cafe_read_setup(cam, cam->state);
+ return ret;
+}
+
+#endif /* CONFIG_PM */
+
+
+static struct pci_device_id cafe_ids[] = {
+ { PCI_DEVICE(0x11ab, 0x4100) }, /* Eventual real ID */
+ { PCI_DEVICE(0x11ab, 0x4102) }, /* Really eventual real ID */
+ { 0, }
+};
+
+MODULE_DEVICE_TABLE(pci, cafe_ids);
+
+static struct pci_driver cafe_pci_driver = {
+ .name = "cafe1000-ccic",
+ .id_table = cafe_ids,
+ .probe = cafe_pci_probe,
+ .remove = cafe_pci_remove,
+#ifdef CONFIG_PM
+ .suspend = cafe_pci_suspend,
+ .resume = cafe_pci_resume,
+#endif
+};
+
+
+
+
+static int __init cafe_init(void)
+{
+ int ret;
+
+ printk(KERN_NOTICE "Marvell M88ALP01 'CAFE' Camera Controller version %d\n",
+ CAFE_VERSION);
+ cafe_dfs_setup();
+ ret = pci_register_driver(&cafe_pci_driver);
+ if (ret) {
+ printk(KERN_ERR "Unable to register cafe_ccic driver\n");
+ goto out;
+ }
+ request_module("ov7670"); /* FIXME want something more general */
+ ret = 0;
+
+ out:
+ return ret;
+}
+
+
+static void __exit cafe_exit(void)
+{
+ pci_unregister_driver(&cafe_pci_driver);
+ cafe_dfs_shutdown();
+}
+
+module_init(cafe_init);
+module_exit(cafe_exit);
--- /dev/null
+/* linux/drivers/mtd/mtdcore.h
+ *
+ * Header file for driver private mtdcore exports
+ *
+ */
+
+/* These are exported solely for the purpose of mtd_blkdevs.c. You
+ should not use them for _anything_ else */
+
+extern struct mutex mtd_table_mutex;
+extern struct mtd_info *mtd_table[MAX_MTD_DEVICES];
--- /dev/null
+/*
+ * MTD Oops/Panic logger
+ *
+ * Copyright (C) 2007 Nokia Corporation. All rights reserved.
+ *
+ * Author: Richard Purdie <rpurdie@openedhand.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ *
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/console.h>
+#include <linux/vmalloc.h>
+#include <linux/workqueue.h>
+#include <linux/sched.h>
+#include <linux/wait.h>
+#include <linux/mtd/mtd.h>
+
+#define OOPS_PAGE_SIZE 4096
+
+static struct mtdoops_context {
+ int mtd_index;
+ struct work_struct work;
+ struct mtd_info *mtd;
+ int oops_pages;
+ int nextpage;
+ int nextcount;
+
+ void *oops_buf;
+ int ready;
+ int writecount;
+} oops_cxt;
+
+static void mtdoops_erase_callback(struct erase_info *done)
+{
+ wait_queue_head_t *wait_q = (wait_queue_head_t *)done->priv;
+ wake_up(wait_q);
+}
+
+static int mtdoops_erase_block(struct mtd_info *mtd, int offset)
+{
+ struct erase_info erase;
+ DECLARE_WAITQUEUE(wait, current);
+ wait_queue_head_t wait_q;
+ int ret;
+
+ init_waitqueue_head(&wait_q);
+ erase.mtd = mtd;
+ erase.callback = mtdoops_erase_callback;
+ erase.addr = offset;
+ if (mtd->erasesize < OOPS_PAGE_SIZE)
+ erase.len = OOPS_PAGE_SIZE;
+ else
+ erase.len = mtd->erasesize;
+ erase.priv = (u_long)&wait_q;
+
+ set_current_state(TASK_INTERRUPTIBLE);
+ add_wait_queue(&wait_q, &wait);
+
+ ret = mtd->erase(mtd, &erase);
+ if (ret) {
+ set_current_state(TASK_RUNNING);
+ remove_wait_queue(&wait_q, &wait);
+ printk (KERN_WARNING "mtdoops: erase of region [0x%x, 0x%x] "
+ "on \"%s\" failed\n",
+ erase.addr, erase.len, mtd->name);
+ return ret;
+ }
+
+ schedule(); /* Wait for erase to finish. */
+ remove_wait_queue(&wait_q, &wait);
+
+ return 0;
+}
+
+static int mtdoops_inc_counter(struct mtdoops_context *cxt)
+{
+ struct mtd_info *mtd = cxt->mtd;
+ size_t retlen;
+ u32 count;
+ int ret;
+
+ cxt->nextpage++;
+ if (cxt->nextpage > cxt->oops_pages)
+ cxt->nextpage = 0;
+ cxt->nextcount++;
+ if (cxt->nextcount == 0xffffffff)
+ cxt->nextcount = 0;
+
+ ret = mtd->read(mtd, cxt->nextpage * OOPS_PAGE_SIZE, 4,
+ &retlen, (u_char *) &count);
+ if ((retlen != 4) || (ret < 0)) {
+ printk(KERN_ERR "mtdoops: Read failure at %d (%d of 4 read)"
+ ", err %d.\n", cxt->nextpage * OOPS_PAGE_SIZE,
+ retlen, ret);
+ return 1;
+ }
+
+ /* See if we need to erase the next block */
+ if (count != 0xffffffff)
+ return 1;
+
+ printk(KERN_DEBUG "mtdoops: Ready %d, %d (no erase)\n",
+ cxt->nextpage, cxt->nextcount);
+ cxt->ready = 1;
+ return 0;
+}
+
+static void mtdoops_prepare(struct mtdoops_context *cxt)
+{
+ struct mtd_info *mtd = cxt->mtd;
+ int i = 0, j, ret, mod;
+
+ /* We were unregistered */
+ if (!mtd)
+ return;
+
+ mod = (cxt->nextpage * OOPS_PAGE_SIZE) % mtd->erasesize;
+ if (mod != 0) {
+ cxt->nextpage = cxt->nextpage + ((mtd->erasesize - mod) / OOPS_PAGE_SIZE);
+ if (cxt->nextpage > cxt->oops_pages)
+ cxt->nextpage = 0;
+ }
+
+ while (mtd->block_isbad &&
+ mtd->block_isbad(mtd, cxt->nextpage * OOPS_PAGE_SIZE)) {
+badblock:
+ printk(KERN_WARNING "mtdoops: Bad block at %08x\n",
+ cxt->nextpage * OOPS_PAGE_SIZE);
+ i++;
+ cxt->nextpage = cxt->nextpage + (mtd->erasesize / OOPS_PAGE_SIZE);
+ if (cxt->nextpage > cxt->oops_pages)
+ cxt->nextpage = 0;
+ if (i == (cxt->oops_pages / (mtd->erasesize / OOPS_PAGE_SIZE))) {
+ printk(KERN_ERR "mtdoops: All blocks bad!\n");
+ return;
+ }
+ }
+
+ for (j = 0, ret = -1; (j < 3) && (ret < 0); j++)
+ ret = mtdoops_erase_block(mtd, cxt->nextpage * OOPS_PAGE_SIZE);
+
+ if (ret < 0) {
+ if (mtd->block_markbad)
+ mtd->block_markbad(mtd, cxt->nextpage * OOPS_PAGE_SIZE);
+ goto badblock;
+ }
+
+ printk(KERN_DEBUG "mtdoops: Ready %d, %d \n", cxt->nextpage, cxt->nextcount);
+
+ cxt->ready = 1;
+}
+
+static void mtdoops_workfunc(struct work_struct *work)
+{
+ struct mtdoops_context *cxt =
+ container_of(work, struct mtdoops_context, work);
+
+ mtdoops_prepare(cxt);
+}
+
+static int find_next_position(struct mtdoops_context *cxt)
+{
+ struct mtd_info *mtd = cxt->mtd;
+ int page, maxpos = 0;
+ u32 count, maxcount = 0xffffffff;
+ size_t retlen;
+
+ for (page = 0; page < cxt->oops_pages; page++) {
+ mtd->read(mtd, page * OOPS_PAGE_SIZE, 4, &retlen, (u_char *) &count);
+ if (count == 0xffffffff)
+ continue;
+ if (maxcount == 0xffffffff) {
+ maxcount = count;
+ maxpos = page;
+ } else if ((count < 0x40000000) && (maxcount > 0xc0000000)) {
+ maxcount = count;
+ maxpos = page;
+ } else if ((count > maxcount) && (count < 0xc0000000)) {
+ maxcount = count;
+ maxpos = page;
+ } else if ((count > maxcount) && (count > 0xc0000000)
+ && (maxcount > 0x80000000)) {
+ maxcount = count;
+ maxpos = page;
+ }
+ }
+ if (maxcount == 0xffffffff) {
+ cxt->nextpage = 0;
+ cxt->nextcount = 1;
+ cxt->ready = 1;
+ printk(KERN_DEBUG "mtdoops: Ready %d, %d (first init)\n",
+ cxt->nextpage, cxt->nextcount);
+ return 0;
+ }
+
+ cxt->nextpage = maxpos;
+ cxt->nextcount = maxcount;
+
+ return mtdoops_inc_counter(cxt);
+}
+
+
+static void mtdoops_notify_add(struct mtd_info *mtd)
+{
+ struct mtdoops_context *cxt = &oops_cxt;
+ int ret;
+
+ if ((mtd->index != cxt->mtd_index) || cxt->mtd_index < 0)
+ return;
+
+ if (mtd->size < (mtd->erasesize * 2)) {
+ printk(KERN_ERR "MTD partition %d not big enough for mtdoops\n",
+ mtd->index);
+ return;
+ }
+
+ cxt->mtd = mtd;
+ cxt->oops_pages = mtd->size / OOPS_PAGE_SIZE;
+
+ ret = find_next_position(cxt);
+ if (ret == 1)
+ mtdoops_prepare(cxt);
+
+ printk(KERN_DEBUG "mtdoops: Attached to MTD device %d\n", mtd->index);
+}
+
+static void mtdoops_notify_remove(struct mtd_info *mtd)
+{
+ struct mtdoops_context *cxt = &oops_cxt;
+
+ if ((mtd->index != cxt->mtd_index) || cxt->mtd_index < 0)
+ return;
+
+ cxt->mtd = NULL;
+ flush_scheduled_work();
+}
+
+
+static void
+mtdoops_console_write(struct console *co, const char *s, unsigned int count)
+{
+ struct mtdoops_context *cxt = co->data;
+ struct mtd_info *mtd = cxt->mtd;
+ int i, ret;
+
+ if (!cxt->ready || !mtd)
+ return;
+
+ if (!oops_in_progress && cxt->writecount != 0) {
+ size_t retlen;
+ if (cxt->writecount < OOPS_PAGE_SIZE)
+ memset(cxt->oops_buf + cxt->writecount, 0xff,
+ OOPS_PAGE_SIZE - cxt->writecount);
+
+ ret = mtd->write(mtd, cxt->nextpage * OOPS_PAGE_SIZE,
+ OOPS_PAGE_SIZE, &retlen, cxt->oops_buf);
+ cxt->ready = 0;
+ cxt->writecount = 0;
+
+ if ((retlen != OOPS_PAGE_SIZE) || (ret < 0))
+ printk(KERN_ERR "mtdoops: Write failure at %d (%d of %d"
+ " written), err %d.\n",
+ cxt->nextpage * OOPS_PAGE_SIZE, retlen,
+ OOPS_PAGE_SIZE, ret);
+
+ ret = mtdoops_inc_counter(cxt);
+ if (ret == 1)
+ schedule_work(&cxt->work);
+ }
+
+ if (!oops_in_progress)
+ return;
+
+ if (cxt->writecount == 0) {
+ u32 *stamp = cxt->oops_buf;
+ *stamp = cxt->nextcount;
+ cxt->writecount = 4;
+ }
+
+ if ((count + cxt->writecount) > OOPS_PAGE_SIZE)
+ count = OOPS_PAGE_SIZE - cxt->writecount;
+
+ for (i = 0; i < count; i++, s++)
+ *((char *)(cxt->oops_buf) + cxt->writecount + i) = *s;
+
+ cxt->writecount = cxt->writecount + count;
+}
+
+static int __init mtdoops_console_setup(struct console *co, char *options)
+{
+ struct mtdoops_context *cxt = co->data;
+
+ if (cxt->mtd_index != -1)
+ return -EBUSY;
+ if (co->index == -1)
+ return -EINVAL;
+
+ cxt->mtd_index = co->index;
+ return 0;
+}
+
+static struct mtd_notifier mtdoops_notifier = {
+ .add = mtdoops_notify_add,
+ .remove = mtdoops_notify_remove,
+};
+
+static struct console mtdoops_console = {
+ .name = "ttyMTD",
+ .write = mtdoops_console_write,
+ .setup = mtdoops_console_setup,
+ .flags = CON_PRINTBUFFER,
+ .index = -1,
+ .data = &oops_cxt,
+};
+
+static int __init mtdoops_console_init(void)
+{
+ struct mtdoops_context *cxt = &oops_cxt;
+
+ cxt->mtd_index = -1;
+ cxt->oops_buf = vmalloc(OOPS_PAGE_SIZE);
+
+ if (!cxt->oops_buf) {
+ printk(KERN_ERR "Failed to allocate oops buffer workspace\n");
+ return -ENOMEM;
+ }
+
+ INIT_WORK(&cxt->work, mtdoops_workfunc);
+
+ register_console(&mtdoops_console);
+ register_mtd_user(&mtdoops_notifier);
+ return 0;
+}
+
+static void __exit mtdoops_console_exit(void)
+{
+ struct mtdoops_context *cxt = &oops_cxt;
+
+ unregister_mtd_user(&mtdoops_notifier);
+ unregister_console(&mtdoops_console);
+ vfree(cxt->oops_buf);
+}
+
+
+subsys_initcall(mtdoops_console_init);
+module_exit(mtdoops_console_exit);
+
+MODULE_LICENSE("GPL");
+MODULE_AUTHOR("Richard Purdie <rpurdie@openedhand.com>");
+MODULE_DESCRIPTION("MTD Oops/Panic console logger/driver");
--- /dev/null
+/*
+ * linux/drivers/mtd/onenand/onenand_sim.c
+ *
+ * The OneNAND simulator
+ *
+ * Copyright © 2005-2007 Samsung Electronics
+ * Kyungmin Park <kyungmin.park@samsung.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/init.h>
+#include <linux/vmalloc.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/partitions.h>
+#include <linux/mtd/onenand.h>
+
+#include <linux/io.h>
+
+#ifndef CONFIG_ONENAND_SIM_MANUFACTURER
+#define CONFIG_ONENAND_SIM_MANUFACTURER 0xec
+#endif
+#ifndef CONFIG_ONENAND_SIM_DEVICE_ID
+#define CONFIG_ONENAND_SIM_DEVICE_ID 0x04
+#endif
+#ifndef CONFIG_ONENAND_SIM_VERSION_ID
+#define CONFIG_ONENAND_SIM_VERSION_ID 0x1e
+#endif
+
+static int manuf_id = CONFIG_ONENAND_SIM_MANUFACTURER;
+static int device_id = CONFIG_ONENAND_SIM_DEVICE_ID;
+static int version_id = CONFIG_ONENAND_SIM_VERSION_ID;
+
+struct onenand_flash {
+ void __iomem *base;
+ void __iomem *data;
+};
+
+#define ONENAND_CORE(flash) (flash->data)
+#define ONENAND_CORE_SPARE(flash, this, offset) \
+ ((flash->data) + (this->chipsize) + (offset >> 5))
+
+#define ONENAND_MAIN_AREA(this, offset) \
+ (this->base + ONENAND_DATARAM + offset)
+
+#define ONENAND_SPARE_AREA(this, offset) \
+ (this->base + ONENAND_SPARERAM + offset)
+
+#define ONENAND_GET_WP_STATUS(this) \
+ (readw(this->base + ONENAND_REG_WP_STATUS))
+
+#define ONENAND_SET_WP_STATUS(v, this) \
+ (writew(v, this->base + ONENAND_REG_WP_STATUS))
+
+/* It has all 0xff chars */
+#define MAX_ONENAND_PAGESIZE (2048 + 64)
+static unsigned char *ffchars;
+
+static struct mtd_partition os_partitions[] = {
+ {
+ .name = "OneNAND simulator partition",
+ .offset = 0,
+ .size = MTDPART_SIZ_FULL,
+ },
+};
+
+/*
+ * OneNAND simulator mtd
+ */
+struct onenand_info {
+ struct mtd_info mtd;
+ struct mtd_partition *parts;
+ struct onenand_chip onenand;
+ struct onenand_flash flash;
+};
+
+struct onenand_info *info;
+
+#define DPRINTK(format, args...) \
+do { \
+ printk(KERN_DEBUG "%s[%d]: " format "\n", __func__, \
+ __LINE__, ##args); \
+} while (0)
+
+/**
+ * onenand_lock_handle - Handle Lock scheme
+ * @param this OneNAND device structure
+ * @param cmd The command to be sent
+ *
+ * Send lock command to OneNAND device.
+ * The lock scheme is depends on chip type.
+ */
+static void onenand_lock_handle(struct onenand_chip *this, int cmd)
+{
+ int block_lock_scheme;
+ int status;
+
+ status = ONENAND_GET_WP_STATUS(this);
+ block_lock_scheme = !(this->options & ONENAND_HAS_CONT_LOCK);
+
+ switch (cmd) {
+ case ONENAND_CMD_UNLOCK:
+ if (block_lock_scheme)
+ ONENAND_SET_WP_STATUS(ONENAND_WP_US, this);
+ else
+ ONENAND_SET_WP_STATUS(status | ONENAND_WP_US, this);
+ break;
+
+ case ONENAND_CMD_LOCK:
+ if (block_lock_scheme)
+ ONENAND_SET_WP_STATUS(ONENAND_WP_LS, this);
+ else
+ ONENAND_SET_WP_STATUS(status | ONENAND_WP_LS, this);
+ break;
+
+ case ONENAND_CMD_LOCK_TIGHT:
+ if (block_lock_scheme)
+ ONENAND_SET_WP_STATUS(ONENAND_WP_LTS, this);
+ else
+ ONENAND_SET_WP_STATUS(status | ONENAND_WP_LTS, this);
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * onenand_bootram_handle - Handle BootRAM area
+ * @param this OneNAND device structure
+ * @param cmd The command to be sent
+ *
+ * Emulate BootRAM area. It is possible to do basic operation using BootRAM.
+ */
+static void onenand_bootram_handle(struct onenand_chip *this, int cmd)
+{
+ switch (cmd) {
+ case ONENAND_CMD_READID:
+ writew(manuf_id, this->base);
+ writew(device_id, this->base + 2);
+ writew(version_id, this->base + 4);
+ break;
+
+ default:
+ /* REVIST: Handle other commands */
+ break;
+ }
+}
+
+/**
+ * onenand_update_interrupt - Set interrupt register
+ * @param this OneNAND device structure
+ * @param cmd The command to be sent
+ *
+ * Update interrupt register. The status is depends on command.
+ */
+static void onenand_update_interrupt(struct onenand_chip *this, int cmd)
+{
+ int interrupt = ONENAND_INT_MASTER;
+
+ switch (cmd) {
+ case ONENAND_CMD_READ:
+ case ONENAND_CMD_READOOB:
+ interrupt |= ONENAND_INT_READ;
+ break;
+
+ case ONENAND_CMD_PROG:
+ case ONENAND_CMD_PROGOOB:
+ interrupt |= ONENAND_INT_WRITE;
+ break;
+
+ case ONENAND_CMD_ERASE:
+ interrupt |= ONENAND_INT_ERASE;
+ break;
+
+ case ONENAND_CMD_RESET:
+ interrupt |= ONENAND_INT_RESET;
+ break;
+
+ default:
+ break;
+ }
+
+ writew(interrupt, this->base + ONENAND_REG_INTERRUPT);
+}
+
+/**
+ * onenand_check_overwrite - Check over-write if happend
+ * @param dest The destination pointer
+ * @param src The source pointer
+ * @param count The length to be check
+ * @return 0 on same, otherwise 1
+ *
+ * Compare the source with destination
+ */
+static int onenand_check_overwrite(void *dest, void *src, size_t count)
+{
+ unsigned int *s = (unsigned int *) src;
+ unsigned int *d = (unsigned int *) dest;
+ int i;
+
+ count >>= 2;
+ for (i = 0; i < count; i++)
+ if ((*s++ ^ *d++) != 0)
+ return 1;
+
+ return 0;
+}
+
+/**
+ * onenand_data_handle - Handle OneNAND Core and DataRAM
+ * @param this OneNAND device structure
+ * @param cmd The command to be sent
+ * @param dataram Which dataram used
+ * @param offset The offset to OneNAND Core
+ *
+ * Copy data from OneNAND Core to DataRAM (read)
+ * Copy data from DataRAM to OneNAND Core (write)
+ * Erase the OneNAND Core (erase)
+ */
+static void onenand_data_handle(struct onenand_chip *this, int cmd,
+ int dataram, unsigned int offset)
+{
+ struct mtd_info *mtd = &info->mtd;
+ struct onenand_flash *flash = this->priv;
+ int main_offset, spare_offset;
+ void __iomem *src;
+ void __iomem *dest;
+ unsigned int i;
+
+ if (dataram) {
+ main_offset = mtd->writesize;
+ spare_offset = mtd->oobsize;
+ } else {
+ main_offset = 0;
+ spare_offset = 0;
+ }
+
+ switch (cmd) {
+ case ONENAND_CMD_READ:
+ src = ONENAND_CORE(flash) + offset;
+ dest = ONENAND_MAIN_AREA(this, main_offset);
+ memcpy(dest, src, mtd->writesize);
+ /* Fall through */
+
+ case ONENAND_CMD_READOOB:
+ src = ONENAND_CORE_SPARE(flash, this, offset);
+ dest = ONENAND_SPARE_AREA(this, spare_offset);
+ memcpy(dest, src, mtd->oobsize);
+ break;
+
+ case ONENAND_CMD_PROG:
+ src = ONENAND_MAIN_AREA(this, main_offset);
+ dest = ONENAND_CORE(flash) + offset;
+ /* To handle partial write */
+ for (i = 0; i < (1 << mtd->subpage_sft); i++) {
+ int off = i * this->subpagesize;
+ if (!memcmp(src + off, ffchars, this->subpagesize))
+ continue;
+ if (memcmp(dest + off, ffchars, this->subpagesize) &&
+ onenand_check_overwrite(dest + off, src + off, this->subpagesize))
+ printk(KERN_ERR "over-write happend at 0x%08x\n", offset);
+ memcpy(dest + off, src + off, this->subpagesize);
+ }
+ /* Fall through */
+
+ case ONENAND_CMD_PROGOOB:
+ src = ONENAND_SPARE_AREA(this, spare_offset);
+ /* Check all data is 0xff chars */
+ if (!memcmp(src, ffchars, mtd->oobsize))
+ break;
+
+ dest = ONENAND_CORE_SPARE(flash, this, offset);
+ if (memcmp(dest, ffchars, mtd->oobsize) &&
+ onenand_check_overwrite(dest, src, mtd->oobsize))
+ printk(KERN_ERR "OOB: over-write happend at 0x%08x\n",
+ offset);
+ memcpy(dest, src, mtd->oobsize);
+ break;
+
+ case ONENAND_CMD_ERASE:
+ memset(ONENAND_CORE(flash) + offset, 0xff, mtd->erasesize);
+ memset(ONENAND_CORE_SPARE(flash, this, offset), 0xff,
+ (mtd->erasesize >> 5));
+ break;
+
+ default:
+ break;
+ }
+}
+
+/**
+ * onenand_command_handle - Handle command
+ * @param this OneNAND device structure
+ * @param cmd The command to be sent
+ *
+ * Emulate OneNAND command.
+ */
+static void onenand_command_handle(struct onenand_chip *this, int cmd)
+{
+ unsigned long offset = 0;
+ int block = -1, page = -1, bufferram = -1;
+ int dataram = 0;
+
+ switch (cmd) {
+ case ONENAND_CMD_UNLOCK:
+ case ONENAND_CMD_LOCK:
+ case ONENAND_CMD_LOCK_TIGHT:
+ case ONENAND_CMD_UNLOCK_ALL:
+ onenand_lock_handle(this, cmd);
+ break;
+
+ case ONENAND_CMD_BUFFERRAM:
+ /* Do nothing */
+ return;
+
+ default:
+ block = (int) readw(this->base + ONENAND_REG_START_ADDRESS1);
+ if (block & (1 << ONENAND_DDP_SHIFT)) {
+ block &= ~(1 << ONENAND_DDP_SHIFT);
+ /* The half of chip block */
+ block += this->chipsize >> (this->erase_shift + 1);
+ }
+ if (cmd == ONENAND_CMD_ERASE)
+ break;
+
+ page = (int) readw(this->base + ONENAND_REG_START_ADDRESS8);
+ page = (page >> ONENAND_FPA_SHIFT);
+ bufferram = (int) readw(this->base + ONENAND_REG_START_BUFFER);
+ bufferram >>= ONENAND_BSA_SHIFT;
+ bufferram &= ONENAND_BSA_DATARAM1;
+ dataram = (bufferram == ONENAND_BSA_DATARAM1) ? 1 : 0;
+ break;
+ }
+
+ if (block != -1)
+ offset += block << this->erase_shift;
+
+ if (page != -1)
+ offset += page << this->page_shift;
+
+ onenand_data_handle(this, cmd, dataram, offset);
+
+ onenand_update_interrupt(this, cmd);
+}
+
+/**
+ * onenand_writew - [OneNAND Interface] Emulate write operation
+ * @param value value to write
+ * @param addr address to write
+ *
+ * Write OneNAND register with value
+ */
+static void onenand_writew(unsigned short value, void __iomem * addr)
+{
+ struct onenand_chip *this = info->mtd.priv;
+
+ /* BootRAM handling */
+ if (addr < this->base + ONENAND_DATARAM) {
+ onenand_bootram_handle(this, value);
+ return;
+ }
+ /* Command handling */
+ if (addr == this->base + ONENAND_REG_COMMAND)
+ onenand_command_handle(this, value);
+
+ writew(value, addr);
+}
+
+/**
+ * flash_init - Initialize OneNAND simulator
+ * @param flash OneNAND simulaotr data strucutres
+ *
+ * Initialize OneNAND simulator.
+ */
+static int __init flash_init(struct onenand_flash *flash)
+{
+ int density, size;
+ int buffer_size;
+
+ flash->base = kzalloc(131072, GFP_KERNEL);
+ if (!flash->base) {
+ printk(KERN_ERR "Unable to allocate base address.\n");
+ return -ENOMEM;
+ }
+
+ density = device_id >> ONENAND_DEVICE_DENSITY_SHIFT;
+ size = ((16 << 20) << density);
+
+ ONENAND_CORE(flash) = vmalloc(size + (size >> 5));
+ if (!ONENAND_CORE(flash)) {
+ printk(KERN_ERR "Unable to allocate nand core address.\n");
+ kfree(flash->base);
+ return -ENOMEM;
+ }
+
+ memset(ONENAND_CORE(flash), 0xff, size + (size >> 5));
+
+ /* Setup registers */
+ writew(manuf_id, flash->base + ONENAND_REG_MANUFACTURER_ID);
+ writew(device_id, flash->base + ONENAND_REG_DEVICE_ID);
+ writew(version_id, flash->base + ONENAND_REG_VERSION_ID);
+
+ if (density < 2)
+ buffer_size = 0x0400; /* 1KiB page */
+ else
+ buffer_size = 0x0800; /* 2KiB page */
+ writew(buffer_size, flash->base + ONENAND_REG_DATA_BUFFER_SIZE);
+
+ return 0;
+}
+
+/**
+ * flash_exit - Clean up OneNAND simulator
+ * @param flash OneNAND simulaotr data strucutres
+ *
+ * Clean up OneNAND simulator.
+ */
+static void flash_exit(struct onenand_flash *flash)
+{
+ vfree(ONENAND_CORE(flash));
+ kfree(flash->base);
+ kfree(flash);
+}
+
+static int __init onenand_sim_init(void)
+{
+ /* Allocate all 0xff chars pointer */
+ ffchars = kmalloc(MAX_ONENAND_PAGESIZE, GFP_KERNEL);
+ if (!ffchars) {
+ printk(KERN_ERR "Unable to allocate ff chars.\n");
+ return -ENOMEM;
+ }
+ memset(ffchars, 0xff, MAX_ONENAND_PAGESIZE);
+
+ /* Allocate OneNAND simulator mtd pointer */
+ info = kzalloc(sizeof(struct onenand_info), GFP_KERNEL);
+ if (!info) {
+ printk(KERN_ERR "Unable to allocate core structures.\n");
+ kfree(ffchars);
+ return -ENOMEM;
+ }
+
+ /* Override write_word function */
+ info->onenand.write_word = onenand_writew;
+
+ if (flash_init(&info->flash)) {
+ printk(KERN_ERR "Unable to allocat flash.\n");
+ kfree(ffchars);
+ kfree(info);
+ return -ENOMEM;
+ }
+
+ info->parts = os_partitions;
+
+ info->onenand.base = info->flash.base;
+ info->onenand.priv = &info->flash;
+
+ info->mtd.name = "OneNAND simulator";
+ info->mtd.priv = &info->onenand;
+ info->mtd.owner = THIS_MODULE;
+
+ if (onenand_scan(&info->mtd, 1)) {
+ flash_exit(&info->flash);
+ kfree(ffchars);
+ kfree(info);
+ return -ENXIO;
+ }
+
+ add_mtd_partitions(&info->mtd, info->parts, ARRAY_SIZE(os_partitions));
+
+ return 0;
+}
+
+static void __exit onenand_sim_exit(void)
+{
+ struct onenand_chip *this = info->mtd.priv;
+ struct onenand_flash *flash = this->priv;
+
+ onenand_release(&info->mtd);
+ flash_exit(flash);
+ kfree(ffchars);
+ kfree(info);
+}
+
+module_init(onenand_sim_init);
+module_exit(onenand_sim_exit);
+
+MODULE_AUTHOR("Kyungmin Park <kyungmin.park@samsung.com>");
+MODULE_DESCRIPTION("The OneNAND flash simulator");
+MODULE_LICENSE("GPL");
--- /dev/null
+/* This header file defines the registers and suspend/resume
+ structures for the Geode GX and LX. The lxfb driver defines
+ _GEODELX_ before including this file, which will unlock the
+ extra registers that are only valid for LX.
+*/
+
+#ifndef _GEODE_REGS_H_
+#define _GEODE_REGS_H_
+
+/* MSRs */
+
+#define GX_VP_MSR_PAD_SELECT 0xC0002011
+#define LX_VP_MSR_PAD_SELECT 0x48000011
+
+#define GEODE_MSR_GLCP_DOTPLL 0x4c000015
+
+#define GLCP_DOTPLL_RESET (1 << 0)
+#define GLCP_DOTPLL_BYPASS (1 << 15)
+#define GLCP_DOTPLL_HALFPIX (1 << 24)
+#define GLCP_DOTPLL_LOCK (1 << 25)
+
+/* Registers */
+#define VP_FP_START 0x400
+
+
+#ifdef _GEODELX_
+
+#define GP_REG_SIZE 0x7C
+#define DC_REG_SIZE 0xF0
+#define VP_REG_SIZE 0x158
+#define FP_REG_SIZE 0x70
+
+#else
+
+#define GP_REG_SIZE 0x50
+#define DC_REG_SIZE 0x90
+#define VP_REG_SIZE 0x138
+#define FP_REG_SIZE 0x70
+
+#endif
+
+#define DC_PAL_SIZE 0x105
+
+struct geoderegs {
+
+ struct {
+ u64 padsel;
+ u64 dotpll;
+
+#ifdef _GEODELX_
+ u64 dfglcfg;
+ u64 dcspare;
+#else
+ u64 rstpll;
+#endif
+ } msr;
+
+ union {
+ unsigned char b[GP_REG_SIZE];
+ struct {
+ u32 dst_offset; /* 0x00 */
+ u32 src_offset; /* 0x04 */
+ u32 stride; /* 0x08 */
+ u32 wid_height; /* 0x0C */
+ u32 src_color_fg; /* 0x10 */
+ u32 src_color_bg; /* 0x14 */
+ u32 pat_color_0; /* 0x18 */
+ u32 pat_color_1; /* 0x1C */
+ u32 pat_color_2; /* 0x20 */
+ u32 pat_color_3; /* 0x24 */
+ u32 pat_color_4; /* 0x28 */
+ u32 pat_color_5; /* 0x2C */
+ u32 pat_data_0; /* 0x30 */
+ u32 pat_data_1; /* 0x34 */
+ u32 raster_mode; /* 0x38 */
+ u32 vector_mode; /* 0x3C */
+ u32 blt_mode; /* 0x40 */
+ u32 blit_status; /* 0x4C */
+ u32 hst_src; /* 0x48 */
+ u32 base_offset; /* 0x4C */
+
+#ifdef _GEODELX_
+ u32 cmd_top; /* 0x50 */
+ u32 cmd_bot; /* 0x54 */
+ u32 cmd_read; /* 0x58 */
+ u32 cmd_write; /* 0x5C */
+ u32 ch3_offset; /* 0x60 */
+ u32 ch3_mode_str; /* 0x64 */
+ u32 ch3_width; /* 0x68 */
+ u32 ch3_hsrc; /* 0x6C */
+ u32 lut_index; /* 0x70 */
+ u32 lut_data; /* 0x74 */
+ u32 int_cntrl; /* 0x78 */
+#endif
+ } r;
+ } gp;
+
+ union {
+ unsigned char b[DC_REG_SIZE];
+
+ struct {
+ u32 unlock; /* 0x00 */
+ u32 gcfg; /* 0x04 */
+ u32 dcfg; /* 0x08 */
+ u32 arb; /* 0x0C */
+ u32 fb_st_offset; /* 0x10 */
+ u32 cb_st_offset; /* 0x14 */
+ u32 curs_st_offset; /* 0x18 */
+ u32 icon_st_offset; /* 0x1C */
+ u32 vid_y_st_offset; /* 0x20 */
+ u32 vid_u_st_offset; /* 0x24 */
+ u32 vid_v_st_offset; /* 0x28 */
+ u32 dctop; /* 0x2c */
+ u32 line_size; /* 0x30 */
+ u32 gfx_pitch; /* 0x34 */
+ u32 vid_yuv_pitch; /* 0x38 */
+ u32 rsvd2; /* 0x3C */
+ u32 h_active_timing; /* 0x40 */
+ u32 h_blank_timing; /* 0x44 */
+ u32 h_sync_timing; /* 0x48 */
+ u32 rsvd3; /* 0x4C */
+ u32 v_active_timing; /* 0x50 */
+ u32 v_blank_timing; /* 0x54 */
+ u32 v_sync_timing; /* 0x58 */
+ u32 fbactive; /* 0x5C */
+ u32 dc_cursor_x; /* 0x60 */
+ u32 dc_cursor_y; /* 0x64 */
+ u32 dc_icon_x; /* 0x68 */
+ u32 dc_line_cnt; /* 0x6C */
+ u32 rsvd5; /* 0x70 - palette address */
+ u32 rsvd6; /* 0x74 - palette data */
+ u32 dfifo_diag; /* 0x78 */
+ u32 cfifo_diag; /* 0x7C */
+ u32 dc_vid_ds_delta; /* 0x80 */
+ u32 gliu0_mem_offset; /* 0x84 */
+ u32 dv_ctl; /* 0x88 - added by LX */
+ u32 dv_acc; /* 0x8C */
+
+#ifdef _GEODELX_
+ u32 gfx_scale;
+ u32 irq_filt_ctl;
+ u32 filt_coeff1;
+ u32 filt_coeff2;
+ u32 vbi_event_ctl;
+ u32 vbi_odd_ctl;
+ u32 vbi_hor;
+ u32 vbi_ln_odd;
+ u32 vbi_ln_event;
+ u32 vbi_pitch;
+ u32 clr_key;
+ u32 clr_key_mask;
+ u32 clr_key_x;
+ u32 clr_key_y;
+ u32 irq;
+ u32 rsvd8;
+ u32 genlk_ctrl;
+ u32 vid_even_y_st_offset; /* 0xD8 */
+ u32 vid_even_u_st_offset; /* 0xDC */
+ u32 vid_even_v_st_offset; /* 0xE0 */
+ u32 v_active_even_timing; /* 0xE4 */
+ u32 v_blank_even_timing; /* 0xE8 */
+ u32 v_sync_even_timing; /* 0xEC */
+#endif
+ } r;
+ } dc;
+
+ union {
+ unsigned char b[VP_REG_SIZE];
+
+ struct {
+ u64 vcfg; /* 0x00 */
+ u64 dcfg; /* 0x08 */
+ u64 vx; /* 0x10 */
+ u64 vy; /* 0x18 */
+ u64 vs; /* 0x20 */
+ u64 vck; /* 0x28 */
+ u64 vcm; /* 0x30 */
+ u64 rsvd1; /* 0x38 - Gamma address*/
+ u64 rsvd2; /* 0x40 - Gamma data*/
+ u64 rsvd3; /* 0x48 */
+ u64 misc; /* 0x50 */
+ u64 ccs; /* 0x58 */
+ u64 rsvd4[3]; /* 0x60-0x70 */
+ u64 vdc; /* 0x78 */
+ u64 vco; /* 0x80 */
+ u64 crc; /* 0x88 */
+ u64 crc32; /* 0x90 */
+ u64 vde; /* 0x98 */
+ u64 cck; /* 0xA0 */
+ u64 ccm; /* 0xA8 */
+ u64 cc1; /* 0xB0 */
+ u64 cc2; /* 0xB8 */
+ u64 a1x; /* 0xC0 */
+ u64 a1y; /* 0xC8 */
+ u64 a1c; /* 0xD0 */
+ u64 a1t; /* 0xD8 */
+ u64 a2x; /* 0xE0 */
+ u64 a2y; /* 0xE8 */
+ u64 a2c; /* 0xF0 */
+ u64 a2t; /* 0xF8 */
+ u64 a3x; /* 0x100 */
+ u64 a3y; /* 0x108 */
+ u64 a3c; /* 0x110 */
+ u64 a3t; /* 0x118 */
+ u64 vrr; /* 0x120 */
+ u64 awt; /* 0x128 */
+ u64 vtm; /* 0x130 */
+#ifdef _GEODELX_
+ u64 vye; /* 0x138 */
+ u64 a1ye; /* 0x140 */
+ u32 a2ye; /* 0x148 */
+ u32 a3ye; /* 0x150 */
+#endif
+ } r;
+ } vp;
+
+ union {
+ unsigned char b[FP_REG_SIZE];
+
+ struct {
+ u64 pt1; /* 0x400 */
+ u64 pt2; /* 0x408 */
+ u64 pm; /* 0x410 */
+ u64 dfc; /* 0x418 */
+ u64 blfsr; /* 0x420 */
+ u64 rlfsr; /* 0x428 */
+ u64 fmi; /* 0x430 */
+ u64 fmd; /* 0x438 */
+ u64 rsvd; /* 0x440 */
+ u64 dca; /* 0x448 */
+ u64 dmd; /* 0x450 */
+ u64 crc; /* 0x458 */
+ u64 fbb; /* 0x460 */
+ u64 crc32; /* 0x468 */
+ } r;
+ } fp;
+
+ u32 pal[DC_PAL_SIZE];
+ u32 gamma[256];
+};
+
+#endif
--- /dev/null
+#include <linux/fb.h>
+#include <asm/io.h>
+#include <asm/msr.h>
+
+#include "geodefb.h"
+#include "video_gx.h"
+
+void gx_set_dotpll(struct fb_info *info, struct geoderegs *regs)
+{
+ int timeout = 1000;
+
+ u64 rstpll, dotpll;
+
+ rdmsrl(MSR_GLCP_SYS_RSTPLL, rstpll);
+ rdmsrl(MSR_GLCP_DOTPLL, dotpll);
+
+ dotpll &= 0x00000000ffffffffull;
+ dotpll |= regs->msr.dotpll & 0xffffffff00000000ull;
+
+ dotpll |= MSR_GLCP_DOTPLL_DOTRESET;
+ dotpll &= ~MSR_GLCP_DOTPLL_BYPASS;
+
+ wrmsrl(MSR_GLCP_DOTPLL, dotpll);
+
+ rstpll |= (regs->msr.rstpll &
+ ( MSR_GLCP_SYS_RSTPLL_DOTPREDIV2 |
+ MSR_GLCP_SYS_RSTPLL_DOTPREMULT2 |
+ MSR_GLCP_SYS_RSTPLL_DOTPOSTDIV3));
+
+ wrmsrl(MSR_GLCP_SYS_RSTPLL, rstpll);
+ dotpll &= ~(MSR_GLCP_DOTPLL_DOTRESET);
+ wrmsrl(MSR_GLCP_DOTPLL, dotpll);
+
+ do {
+ rdmsrl(MSR_GLCP_DOTPLL, dotpll);
+ } while (timeout-- && !(dotpll & MSR_GLCP_DOTPLL_LOCK));
+}
+
+/* FIXME: Make sure nothing is read to clear */
+
+void gx_save_regs(struct fb_info *info, struct geoderegs *regs)
+{
+ struct geodefb_par *par = info->par;
+ int i;
+
+ /* Wait for the BLT engine to stop being busy */
+ while(readl(par->gp_regs + 0x44) & 0x05);
+
+ rdmsrl(GX_VP_MSR_PAD_SELECT, regs->msr.padsel);
+ rdmsrl(MSR_GLCP_DOTPLL, regs->msr.dotpll);
+ rdmsrl(MSR_GLCP_SYS_RSTPLL, regs->msr.rstpll);
+
+ writel(0x4758, par->dc_regs + 0x00);
+
+ memcpy(regs->gp.b, par->gp_regs, GP_REG_SIZE);
+ memcpy(regs->dc.b, par->dc_regs, DC_REG_SIZE);
+ memcpy(regs->vp.b, par->vid_regs, VP_REG_SIZE);
+ memcpy(regs->fp.b, par->vid_regs + 0x400, FP_REG_SIZE);
+
+ /* Save the palettes */
+ writel(0, par->dc_regs + 0x70);
+
+ for(i = 0; i < DC_PAL_SIZE; i++)
+ regs->pal[i] = readl(par->dc_regs + 0x74);
+
+ writel(0, par->vid_regs + 0x38);
+
+ for(i = 0; i < 0xFF; i++)
+ regs->gamma[i] = readl(par->vid_regs + 0x40);
+}
+
+void gx_restore_regs(struct fb_info *info, struct geoderegs *regs)
+{
+ struct geodefb_par *par = info->par;
+ u32 val, i;
+
+ /* DOTPLL */
+ gx_set_dotpll(info, regs);
+
+ /* GP */
+
+ writel(regs->gp.r.dst_offset, par->gp_regs + 0x00);
+ writel(regs->gp.r.src_offset, par->gp_regs + 0x04);
+ writel(regs->gp.r.stride, par->gp_regs + 0x08);
+ writel(regs->gp.r.wid_height, par->gp_regs + 0x0C);
+ writel(regs->gp.r.src_color_fg, par->gp_regs + 0x10);
+ writel(regs->gp.r.src_color_bg, par->gp_regs + 0x14);
+ writel(regs->gp.r.pat_color_0, par->gp_regs + 0x18);
+ writel(regs->gp.r.pat_color_1, par->gp_regs + 0x1C);
+ writel(regs->gp.r.pat_color_2, par->gp_regs + 0x20);
+ writel(regs->gp.r.pat_color_3, par->gp_regs + 0x24);
+ writel(regs->gp.r.pat_color_4, par->gp_regs + 0x28);
+ writel(regs->gp.r.pat_color_5, par->gp_regs + 0x2C);
+ writel(regs->gp.r.pat_data_0, par->gp_regs + 0x30);
+ writel(regs->gp.r.pat_data_1, par->gp_regs + 0x34);
+
+ /* Don't write the raster / vector / blt mode regs */
+ /* status register is read only */
+
+ writel(regs->gp.r.hst_src, par->gp_regs + 0x48);
+ writel(regs->gp.r.base_offset, par->gp_regs + 0x4c);
+
+ /* DC */
+
+ /* Write the unlock value */
+ writel(0x4758, par->dc_regs + 0x00);
+
+ writel(0, par->dc_regs + 0x70);
+
+ for(i = 0; i < DC_PAL_SIZE; i++)
+ writel(regs->pal[i], par->dc_regs + 0x74);
+
+ /* Write the gcfg register without the enables */
+ writel(regs->dc.r.gcfg & ~0x0F, par->dc_regs + 0x04);
+
+ /* Write the vcfg register without the enables */
+ writel(regs->dc.r.dcfg & ~0x19, par->dc_regs + 0x08);
+
+ /* Write the rest of the active registers */
+
+ writel(regs->dc.r.fb_st_offset, par->dc_regs + 0x10);
+ writel(regs->dc.r.cb_st_offset, par->dc_regs + 0x14);
+ writel(regs->dc.r.curs_st_offset, par->dc_regs + 0x18);
+ writel(regs->dc.r.icon_st_offset, par->dc_regs + 0x1C);
+ writel(regs->dc.r.vid_y_st_offset, par->dc_regs + 0x20);
+ writel(regs->dc.r.vid_u_st_offset, par->dc_regs + 0x24);
+ writel(regs->dc.r.vid_v_st_offset, par->dc_regs + 0x28);
+ writel(regs->dc.r.line_size, par->dc_regs + 0x30);
+ writel(regs->dc.r.gfx_pitch, par->dc_regs + 0x34);
+ writel(regs->dc.r.vid_yuv_pitch, par->dc_regs + 0x38);
+ writel(regs->dc.r.h_active_timing, par->dc_regs + 0x40);
+ writel(regs->dc.r.h_blank_timing, par->dc_regs + 0x44);
+ writel(regs->dc.r.h_sync_timing, par->dc_regs + 0x48);
+ writel(regs->dc.r.v_active_timing, par->dc_regs + 0x50);
+ writel(regs->dc.r.v_blank_timing, par->dc_regs + 0x54);
+ writel(regs->dc.r.v_sync_timing, par->dc_regs + 0x58);
+ writel(regs->dc.r.dc_cursor_x, par->dc_regs + 0x60);
+ writel(regs->dc.r.dc_cursor_y, par->dc_regs + 0x64);
+ writel(regs->dc.r.dc_icon_x, par->dc_regs + 0x68);
+
+ /* Don't write the line_cnt or diag registers */
+
+ writel(regs->dc.r.dc_vid_ds_delta, par->dc_regs + 0x80);
+ writel(regs->dc.r.gliu0_mem_offset, par->dc_regs + 0x84);
+ writel(regs->dc.r.dv_acc, par->dc_regs + 0x8C);
+
+ /* VP */
+
+ /* MSR */
+ wrmsrl(GX_VP_MSR_PAD_SELECT, regs->msr.padsel);
+
+ writel(0, par->vid_regs + 0x38);
+
+ for(i = 0; i < 0xFF; i++)
+ writel((u32) regs->gamma[i], par->vid_regs + 0x40);
+
+ /* Don't enable video yet */
+ writel((u32) regs->vp.r.vcfg & ~0x01, par->vid_regs + 0x00);
+
+ /* Don't enable the CRT yet */
+ writel((u32) regs->vp.r.dcfg & ~0x0F, par->vid_regs + 0x08);
+
+ /* Write the rest of the VP registers */
+
+ writel((u32) regs->vp.r.vx, par->vid_regs + 0x10);
+ writel((u32) regs->vp.r.vy, par->vid_regs + 0x18);
+ writel((u32) regs->vp.r.vs, par->vid_regs + 0x20);
+ writel((u32) regs->vp.r.vck, par->vid_regs + 0x28);
+ writel((u32) regs->vp.r.vcm, par->vid_regs + 0x30);
+ writel((u32) regs->vp.r.misc, par->vid_regs + 0x50);
+ writel((u32) regs->vp.r.ccs, par->vid_regs + 0x58);
+ writel((u32) regs->vp.r.vdc, par->vid_regs + 0x78);
+ writel((u32) regs->vp.r.vco, par->vid_regs + 0x80);
+ writel((u32) regs->vp.r.crc, par->vid_regs + 0x88);
+ writel((u32) regs->vp.r.vde, par->vid_regs + 0x98);
+ writel((u32) regs->vp.r.cck, par->vid_regs + 0xA0);
+ writel((u32) regs->vp.r.ccm, par->vid_regs + 0xA8);
+ writel((u32) regs->vp.r.cc1, par->vid_regs + 0xB0);
+ writel((u32) regs->vp.r.cc2, par->vid_regs + 0xB8);
+ writel((u32) regs->vp.r.a1x, par->vid_regs + 0xC0);
+ writel((u32) regs->vp.r.a1y, par->vid_regs + 0xC8);
+ writel((u32) regs->vp.r.a1c, par->vid_regs + 0xD0);
+ writel((u32) regs->vp.r.a1t, par->vid_regs + 0xD8);
+ writel((u32) regs->vp.r.a2x, par->vid_regs + 0xE0);
+ writel((u32) regs->vp.r.a2y, par->vid_regs + 0xE8);
+ writel((u32) regs->vp.r.a2c, par->vid_regs + 0xF0);
+ writel((u32) regs->vp.r.a2t, par->vid_regs + 0xF8);
+ writel((u32) regs->vp.r.a3x, par->vid_regs + 0x100);
+ writel((u32) regs->vp.r.a3y, par->vid_regs + 0x108);
+ writel((u32) regs->vp.r.a3c, par->vid_regs + 0x110);
+ writel((u32) regs->vp.r.a3t, par->vid_regs + 0x118);
+ writel((u32) regs->vp.r.vrr, par->vid_regs + 0x120);
+
+
+ /* FP registers */
+
+ writel((u32) regs->fp.r.pt1, par->vid_regs + 0x400);
+ writel((u32) regs->fp.r.pt2, par->vid_regs + 0x408);
+
+ writel((u32) regs->fp.r.dfc, par->vid_regs + 0x418);
+ writel(regs->fp.r.blfsr, par->vid_regs + 0x420);
+ writel(regs->fp.r.rlfsr, par->vid_regs + 0x428);
+ writel(regs->fp.r.fmi, par->vid_regs + 0x430);
+ writel(regs->fp.r.fmd, par->vid_regs + 0x438);
+ writel(regs->fp.r.dca, par->vid_regs + 0x448);
+ writel(regs->fp.r.dmd, par->vid_regs + 0x450);
+ writel(regs->fp.r.crc, par->vid_regs + 0x458);
+ writel(regs->fp.r.fbb, par->vid_regs + 0x460);
+
+ /* Final enables */
+
+ val = readl(par->vid_regs + 0x410);
+
+ /* Control the panel */
+ if (regs->fp.r.pm & (1 << 24)) {
+
+ if (!(val & 0x09))
+ writel(regs->fp.r.pm, par->vid_regs + 0x410);
+ }
+ else {
+ if (!(val & 0x05))
+ writel(regs->fp.r.pm, par->vid_regs + 0x410);
+ }
+
+ /* Turn everything on */
+
+ writel(regs->dc.r.gcfg, par->dc_regs + 0x04);
+ writel((u32) regs->vp.r.vcfg, par->vid_regs + 0x00);
+ writel((u32) regs->vp.r.dcfg, par->vid_regs + 0x08);
+ writel(regs->dc.r.dcfg, par->dc_regs + 0x08);
+}
+
+
+#ifdef DEBUG
+
+void dump_regs(struct fb_info *info, int mode) {
+
+ struct geodefb_par *par = info->par;
+ u32 val;
+ int i;
+
+ if (mode == 0) {
+ for(i = 0; i < GP_REG_SIZE; i += 4) {
+ val = readl(par->gp_regs + i);
+ }
+ }
+
+ if (mode == 1) {
+ writel(0x4758, par->dc_regs + 0x00);
+
+ for(i = 0; i < DC_REG_SIZE; i += 4) {
+ val = readl(par->dc_regs + i);
+ printk("DC%x: %x\n", i, val);
+ }
+ }
+
+ if (mode == 2) {
+ for(i = 0; i < VP_REG_SIZE; i += 8) {
+ val = readl(par->vid_regs + i);
+ printk("VP%x: %x\n", i, val);
+ }
+ }
+
+ if (mode == 3) {
+ for(i = 0; i < FP_REG_SIZE; i += 8) {
+ val = readl(par->vid_regs + 0x400 + i);
+ printk("FP%x: %x\n", i, val);
+ }
+ }
+}
+
+#endif
--- /dev/null
+/*
+ * Mainly by David Woodhouse, somewhat modified by Jordan Crouse
+ *
+ * Copyright © 2006-2007 Red Hat, Inc.
+ * Copyright © 2006-2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software. You can redistribute it and/or
+ * modify it under the terms of version 2 of the GNU General Public
+ * License as published by the Free Software Foundation.
+ */
+
+
+#include <linux/kernel.h>
+#include <linux/fb.h>
+#include <linux/i2c.h>
+#include <linux/platform_device.h>
+#include <linux/i2c-id.h>
+#include <linux/pci.h>
+#include <linux/vt_kern.h>
+#include <linux/pci_ids.h>
+#include <linux/interrupt.h>
+#include <linux/delay.h>
+#include <linux/backlight.h>
+#include <linux/device.h>
+#include <asm/uaccess.h>
+#include <linux/ctype.h>
+#include <linux/reboot.h>
+#include <asm/tsc.h>
+#include <asm/olpc.h>
+
+#include "olpc_dcon.h"
+
+/* Module definitions */
+
+static int resumeline = 898;
+module_param(resumeline, int, 0444);
+
+static int noinit;
+module_param(noinit, int, 0444);
+
+/* Default off since it doesn't work on DCON ASIC in B-test OLPC board */
+static int useaa = 1;
+module_param(useaa, int, 0444);
+
+/* I2C structures */
+
+static struct i2c_driver dcon_driver;
+static struct i2c_client *dcon_client;
+
+/* Platform devices */
+static struct platform_device *dcon_device;
+
+/* Backlight device */
+static struct backlight_device *dcon_bl_dev;
+
+/* Base address of the GPIO registers */
+static unsigned long gpio_base;
+
+static struct fb_info *fbinfo;
+
+/* Current source, initialized at probe time */
+static int dcon_source;
+
+/* Desired source */
+static int dcon_pending;
+
+/* Current output type */
+static int dcon_output = DCON_OUTPUT_COLOR;
+
+/* Current sleep status (not yet implemented) */
+static int dcon_sleep_val = DCON_ACTIVE;
+
+/* Shadow register for the DCON_REG_MODE register */
+static unsigned short dcon_disp_mode;
+
+/* Variables used during switches */
+static int dcon_switched;
+
+static DECLARE_WAIT_QUEUE_HEAD(dcon_wait_queue);
+
+static unsigned short normal_i2c[] = { 0x0D, I2C_CLIENT_END };
+I2C_CLIENT_INSMOD;
+
+#define dcon_write(reg,val) i2c_smbus_write_word_data(dcon_client,reg,val)
+#define dcon_read(reg) i2c_smbus_read_word_data(dcon_client,reg)
+
+/* The current backlight value - this saves us some smbus traffic */
+static int bl_val = -1;
+
+/* ===== API functions - these are called by a variety of users ==== */
+
+/* Backlight notes - turning off the backlight enable bit in the DCON
+ * doesn't save us any power over just pushing the BL to zero, so we
+ * don't use that bit in this code.
+ */
+
+static int dcon_get_backlight(void)
+{
+ if (dcon_client == NULL)
+ return 0;
+
+ if (bl_val == -1)
+ bl_val = dcon_read(DCON_REG_BRIGHT) & 0x0F;
+
+ return bl_val;
+}
+
+static void dcon_set_backlight(int level)
+{
+ if (dcon_client == NULL)
+ return;
+
+ if (bl_val == (level & 0x0F))
+ return;
+
+ bl_val = level & 0x0F;
+ dcon_write(DCON_REG_BRIGHT, bl_val);
+
+ /* Purposely turn off the backlight when we go to level 0 */
+
+ if (bl_val == 0) {
+ dcon_disp_mode &= ~MODE_BL_ENABLE;
+ dcon_write(DCON_REG_MODE, dcon_disp_mode);
+ }
+ else if (!(dcon_disp_mode & MODE_BL_ENABLE)) {
+ dcon_disp_mode |= MODE_BL_ENABLE;
+ dcon_write(DCON_REG_MODE, dcon_disp_mode);
+ }
+}
+
+/* Set the output type to either color or mono */
+
+static int dcon_set_output(int arg)
+{
+ if (dcon_output == arg)
+ return 0;
+
+ dcon_output = arg;
+
+ if (arg == DCON_OUTPUT_MONO) {
+ dcon_disp_mode &= ~(MODE_CSWIZZLE | MODE_COL_AA);
+ dcon_disp_mode |= MODE_MONO_LUMA;
+ }
+ else {
+ dcon_disp_mode &= ~(MODE_MONO_LUMA);
+ dcon_disp_mode |= MODE_CSWIZZLE;
+ if (useaa)
+ dcon_disp_mode |= MODE_COL_AA;
+ }
+
+ dcon_write(DCON_REG_MODE, dcon_disp_mode);
+ return 0;
+}
+
+/* For now, this will be really stupid - we need to address how
+ * DCONLOAD works in a sleep and account for it accordingly
+ */
+
+static void dcon_sleep(int state)
+{
+ /* Turn off the backlight and put the DCON to sleep */
+
+ if (state == dcon_sleep_val)
+ return;
+
+ if (state == DCON_SLEEP) {
+ dcon_disp_mode &= ~MODE_BL_ENABLE;
+ dcon_disp_mode |= MODE_SLEEP;
+ }
+ else {
+ /* Only re-enable the backlight if the backlight value is set */
+
+ if (bl_val != 0)
+ dcon_disp_mode |= MODE_BL_ENABLE;
+
+ dcon_disp_mode &= ~MODE_SLEEP;
+ }
+
+ dcon_sleep_val = state;
+ dcon_write(DCON_REG_MODE, dcon_disp_mode);
+
+ /* We should turn off some stuff in the framebuffer - but what? */
+}
+
+/* Set the source of the display (CPU or DCON) */
+
+static void dcon_source_switch(struct work_struct *work)
+{
+ DECLARE_WAITQUEUE(wait, current);
+ int source = dcon_pending;
+
+ if (dcon_source == source)
+ return;
+
+ dcon_switched = 0;
+
+ switch (source) {
+ case DCON_SOURCE_CPU:
+
+ /* Enable the scanline interrupt bit */
+ if (dcon_write(DCON_REG_MODE, dcon_disp_mode | MODE_SCAN_INT))
+ printk(KERN_ERR "olpc-dcon: couldn't enable scanline interrupt!\n");
+ else {
+ /* Wait up to one second for the scanline interrupt */
+ wait_event_timeout(dcon_wait_queue, dcon_switched == 1, HZ);
+ }
+
+ if (!dcon_switched)
+ printk(KERN_ERR "olpc-dcon: Timeout entering CPU mode; expect a screen glitch.\n");
+
+ /*
+ * Ideally we'd like to disable interrupts here so that the
+ * fb_powerup and DCON turn on happen at a known time value;
+ * however, we can't do that right now with fb_set_suspend
+ * messing with semaphores.
+ *
+ * For now, we just hope..
+ */
+ if (fb_powerup(fbinfo)) {
+ printk(KERN_ERR "olpc-dcon: Failed to enter CPU mode\n");
+ dcon_pending = DCON_SOURCE_DCON;
+ return;
+ }
+
+ /* And turn off the DCON */
+ outl(1<<11, gpio_base + GPIOx_OUT_VAL);
+
+ /* Turn off the scanline interrupt */
+ if (dcon_write(DCON_REG_MODE, dcon_disp_mode))
+ printk(KERN_ERR "olpc-dcon: couldn't disable scanline interrupt!\n");
+
+ printk(KERN_INFO "olpc-dcon: The CPU has control\n");
+ break;
+ case DCON_SOURCE_DCON:
+ {
+ int t;
+
+ add_wait_queue(&dcon_wait_queue, &wait);
+ set_current_state(TASK_UNINTERRUPTIBLE);
+
+ /* Clear GPIO11 (DCONLOAD) - this implies that the DCON is in
+ control */
+
+ outl(1 << (11 + 16), gpio_base + GPIOx_OUT_VAL);
+
+ t = schedule_timeout(HZ/2);
+ remove_wait_queue(&dcon_wait_queue, &wait);
+ set_current_state(TASK_RUNNING);
+
+ if (!dcon_switched)
+ printk(KERN_ERR "olpc-dcon: Timeout entering DCON mode; expect a screen glitch.\n");
+
+ /* Turn off the graphics engine completely */
+ fb_powerdown(fbinfo);
+
+ printk(KERN_INFO "olpc-dcon: The DCON has control\n");
+ break;
+ }
+ default:
+ BUG();
+ }
+
+ dcon_source = source;
+}
+
+static DECLARE_WORK(dcon_work, dcon_source_switch);
+
+static int dcon_set_source(int arg)
+{
+ if (arg != DCON_SOURCE_CPU && arg != DCON_SOURCE_DCON)
+ return -EINVAL;
+
+ if (dcon_pending == arg)
+ return 0;
+
+ dcon_pending = arg;
+ if ((dcon_source != arg) && !work_pending(&dcon_work))
+ schedule_work(&dcon_work);
+
+ return 0;
+}
+
+static int dcon_set_source_sync(int arg)
+{
+ int ret = dcon_set_source(arg);
+ if (!ret)
+ flush_scheduled_work();
+ return ret;
+}
+
+static int dconbl_set(struct backlight_device *dev) {
+
+ int level = dev->props.brightness;
+
+ if (dev->props.power != FB_BLANK_UNBLANK)
+ level = 0;
+
+ dcon_set_backlight(level);
+ return 0;
+}
+
+static int dconbl_get(struct backlight_device *dev) {
+ return dcon_get_backlight();
+}
+
+static ssize_t dcon_mode_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%4.4X\n", dcon_disp_mode);
+}
+
+static ssize_t dcon_sleep_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", dcon_sleep_val);
+}
+
+static ssize_t /* __deprecated */ dcon_source_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ printk(KERN_WARNING "olpc-dcon: using deprecated sysfs 'source' interface; use 'freeze' instead!\n");
+ return sprintf(buf, "%d\n", dcon_source);
+}
+
+static ssize_t dcon_freeze_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", dcon_source == DCON_SOURCE_DCON ? 1 : 0);
+}
+
+static ssize_t dcon_output_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", dcon_output);
+}
+
+static ssize_t dcon_resumeline_show(struct device *dev,
+ struct device_attribute *attr, char *buf)
+{
+ return sprintf(buf, "%d\n", resumeline);
+}
+
+static int _strtoul(const char *buf, int len, unsigned int *val)
+{
+
+ char *endp;
+ unsigned int output = simple_strtoul(buf, &endp, 0);
+ int size = endp - buf;
+
+ if (*endp && isspace(*endp))
+ size++;
+
+ if (size != len)
+ return -EINVAL;
+
+ *val = output;
+ return 0;
+}
+
+static ssize_t dcon_output_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ int output;
+ int rc = -EINVAL;
+
+ if (_strtoul(buf, count, &output))
+ return -EINVAL;
+
+ if (output == DCON_OUTPUT_COLOR || output == DCON_OUTPUT_MONO) {
+ dcon_set_output(output);
+ rc = count;
+ }
+
+ return rc;
+}
+
+static ssize_t /* __deprecated */ dcon_source_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ int output;
+ int rc = -EINVAL;
+
+ printk(KERN_WARNING "olpc-dcon: using deprecated sysfs 'source' interface; use 'freeze' instead!\n");
+ if (_strtoul(buf, count, &output))
+ return -EINVAL;
+
+ dcon_set_source(output);
+ rc = count;
+
+ return rc;
+}
+
+static ssize_t dcon_freeze_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ int output;
+ int rc = -EINVAL;
+
+ if (_strtoul(buf, count, &output))
+ return rc;
+
+ dcon_set_source(output ? DCON_SOURCE_DCON : DCON_SOURCE_CPU);
+ rc = count;
+
+ return rc;
+}
+
+static ssize_t dcon_resumeline_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ int rl;
+ int rc = -EINVAL;
+
+ if (_strtoul(buf, count, &rl))
+ return rc;
+
+ resumeline = rl;
+ dcon_write(DCON_REG_SCAN_INT, resumeline);
+ rc = count;
+
+ return rc;
+}
+
+static ssize_t dcon_sleep_store(struct device *dev,
+ struct device_attribute *attr, const char *buf, size_t count)
+{
+ int output;
+
+ if (_strtoul(buf, count, &output))
+ return -EINVAL;
+
+ dcon_sleep(output ? DCON_SLEEP : DCON_ACTIVE);
+ return count;
+}
+
+static struct device_attribute dcon_device_files[] = {
+ __ATTR(mode, 0444, dcon_mode_show, NULL),
+ __ATTR(sleep, 0644, dcon_sleep_show, dcon_sleep_store),
+ __ATTR(source, 0644, dcon_source_show, dcon_source_store),
+ __ATTR(freeze, 0644, dcon_freeze_show, dcon_freeze_store),
+ __ATTR(output, 0644, dcon_output_show, dcon_output_store),
+ __ATTR(resumeline, 0644, dcon_resumeline_show, dcon_resumeline_store),
+};
+
+static struct backlight_ops dcon_bl_ops = {
+ .get_brightness = dconbl_get,
+ .update_status = dconbl_set
+};
+
+/* List of GPIOs that we care about:
+ (in) GPIO12 -- DCONBLNK
+ (in) GPIO[56] -- DCONSTAT[01]
+ (out) GPIO11 -- DCONLOAD
+*/
+
+#define IN_GPIOS ((1<<5) | (1<<6) | (1<<7) | (1<<12))
+#define OUT_GPIOS (1<<11)
+
+static irqreturn_t dcon_interrupt(int, void *);
+
+static int dcon_request_irq(void)
+{
+ unsigned long lo, hi;
+ unsigned char lob;
+
+ rdmsr(MSR_LBAR_GPIO, lo, hi);
+
+ /* Check the mask and whether GPIO is enabled (sanity check) */
+ if (hi != 0x0000f001) {
+ printk(KERN_ERR "GPIO not enabled -- cannot use DCON\n");
+ return -ENODEV;
+ }
+
+ /* Mask off the IO base address */
+ gpio_base = lo & 0x0000ff00;
+
+ /* Turn off the event enable for GPIO7 just to be safe */
+ outl(1 << (16+7), gpio_base + GPIOx_EVNT_EN);
+
+ /* Set the directions for the GPIO pins */
+ outl(OUT_GPIOS | (IN_GPIOS << 16), gpio_base + GPIOx_OUT_EN);
+ outl(IN_GPIOS | (OUT_GPIOS << 16), gpio_base + GPIOx_IN_EN);
+
+ /* Set up the interrupt mappings */
+
+ /* Set the IRQ to pair 2 */
+ geode_gpio_event_irq(OLPC_GPIO_DCON_IRQ, 2);
+
+ /* Enable group 2 to trigger the DCON interrupt */
+ geode_gpio_set_irq(2, DCON_IRQ);
+
+ /* Select edge level for interrupt (in PIC) */
+
+ lob = inb(0x4d0);
+ lob &= ~(1 << DCON_IRQ);
+ outb(lob, 0x4d0);
+
+ /* Register the interupt handler */
+ if (request_irq(DCON_IRQ, &dcon_interrupt, 0, "DCON", &dcon_driver))
+ return -EIO;
+
+ /* Clear INV_EN for GPIO7 (DCONIRQ) */
+ outl((1<<(16+7)), gpio_base + GPIOx_INV_EN);
+
+ /* Enable filter for GPIO12 (DCONBLANK) */
+ outl(1<<(12), gpio_base + GPIOx_IN_FLTR_EN);
+
+ /* Disable filter for GPIO7 */
+ outl(1<<(16+7), gpio_base + GPIOx_IN_FLTR_EN);
+
+ /* Disable event counter for GPIO7 (DCONIRQ) and GPIO12 (DCONBLANK) */
+
+ outl(1<<(16+7), gpio_base + GPIOx_EVNTCNT_EN);
+ outl(1<<(16+12), gpio_base + GPIOx_EVNTCNT_EN);
+
+ /* Add GPIO12 to the Filter Event Pair #7 */
+ outb(12, gpio_base + GPIO_FE7_SEL);
+
+ /* Turn off negative Edge Enable for GPIO12 */
+ outl(1<<(16+12), gpio_base + GPIOx_NEGEDGE_EN);
+
+ /* Enable negative Edge Enable for GPIO7 */
+ outl(1<<7, gpio_base + GPIOx_NEGEDGE_EN);
+
+ /* Zero the filter amount for Filter Event Pair #7 */
+ outw(0, gpio_base + GPIO_FLT7_AMNT);
+
+ /* Clear the negative edge status for GPIO7 and GPIO12 */
+ outl((1<<7) | (1<<12), gpio_base+0x4c);
+
+ /* FIXME: Clear the posiitive status as well, just to be sure */
+ outl((1<<7) | (1<<12), gpio_base+0x48);
+
+ /* Enable events for GPIO7 (DCONIRQ) and GPIO12 (DCONBLANK) */
+ outl((1<<(7))|(1<<12), gpio_base + GPIOx_EVNT_EN);
+
+ /* Determine the current state by reading the GPIO bit */
+ /* Earlier stages of the boot process have established the state */
+ dcon_source = inl(gpio_base + GPIOx_OUT_VAL) & (1<<11)
+ ? DCON_SOURCE_CPU
+ : DCON_SOURCE_DCON;
+ dcon_pending = dcon_source;
+
+ return 0;
+}
+
+static int dcon_reboot_notify(struct notifier_block *nb, unsigned long foo, void *bar)
+{
+ if (dcon_client == NULL)
+ return 0;
+
+ /* Turn off the DCON. Entirely. */
+ dcon_write(DCON_REG_MODE, 0x39);
+ dcon_write(DCON_REG_MODE, 0x32);
+ return 0;
+}
+
+static int dcon_conswitch_notify(struct notifier_block *nb,
+ unsigned long mode, void *dummy)
+{
+ if (mode == CONSOLE_EVENT_SWITCH_TEXT)
+ dcon_sleep(DCON_ACTIVE);
+
+ return 0;
+}
+
+static struct notifier_block dcon_nb = {
+ .notifier_call = dcon_reboot_notify,
+ .priority = -1,
+};
+
+static struct notifier_block dcon_console_nb = {
+ .notifier_call = dcon_conswitch_notify,
+ .priority = -1,
+};
+
+static int dcon_probe(struct i2c_adapter *adap, int addr, int kind)
+{
+ struct i2c_client *client;
+ uint16_t ver;
+ int rc, i;
+
+ if (!olpc_has_dcon()) {
+ printk("olpc-dcon: No DCON is attached.\n");
+ return -ENODEV;
+ }
+
+ if (num_registered_fb >= 1)
+ fbinfo = registered_fb[0];
+
+ if (adap->id != I2C_HW_SMBUS_SCX200) {
+ printk(KERN_ERR "olpc-dcon: Invalid I2C bus (%d not %d)\n",
+ adap->id, I2C_HW_SMBUS_SCX200);
+ return -ENXIO;
+ }
+
+ client = kzalloc(sizeof(struct i2c_client), GFP_KERNEL);
+ if (client == NULL)
+ return -ENOMEM;
+
+ strncpy(client->name, "OLPC-DCON", I2C_NAME_SIZE);
+ client->addr = addr;
+ client->adapter = adap;
+ client->driver = &dcon_driver;
+
+ if ((rc = i2c_attach_client(client)) != 0) {
+ printk(KERN_ERR "olpc-dcon: Unable to attach the I2C client.\n");
+ goto eclient;
+ }
+
+ ver = i2c_smbus_read_word_data(client, DCON_REG_ID);
+
+ if ((ver >> 8) != 0xDC) {
+ printk(KERN_ERR "olpc-dcon: DCON ID not 0xDCxx: 0x%04x instead.\n", ver);
+ rc = -ENXIO;
+ goto ei2c;
+ }
+
+ if ((rc = dcon_request_irq())) {
+ printk(KERN_ERR "olpc-dcon: Unable to grab IRQ.\n");
+ goto ei2c;
+ }
+
+ if (ver < 0xdc02 && !noinit) {
+ /* Initialize the DCON registers */
+
+ /* Start with work-arounds for DCON ASIC */
+ i2c_smbus_write_word_data(client, 0x4b, 0x00cc);
+ i2c_smbus_write_word_data(client, 0x4b, 0x00cc);
+ i2c_smbus_write_word_data(client, 0x4b, 0x00cc);
+ i2c_smbus_write_word_data(client, 0x0b, 0x007a);
+ i2c_smbus_write_word_data(client, 0x36, 0x025c);
+ i2c_smbus_write_word_data(client, 0x37, 0x025e);
+
+ /* Initialise SDRAM */
+
+ i2c_smbus_write_word_data(client, 0x3b, 0x002b);
+ i2c_smbus_write_word_data(client, 0x41, 0x0101);
+ i2c_smbus_write_word_data(client, 0x42, 0x0101);
+ }
+
+ /* Colour swizzle, AA, no passthrough, backlight */
+
+ dcon_disp_mode = MODE_PASSTHRU | MODE_BL_ENABLE | MODE_CSWIZZLE;
+ if (useaa)
+ dcon_disp_mode |= MODE_COL_AA;
+ i2c_smbus_write_word_data(client, DCON_REG_MODE, dcon_disp_mode);
+
+
+ /* Set the scanline to interrupt on during resume */
+
+ i2c_smbus_write_word_data(client, DCON_REG_SCAN_INT, resumeline);
+
+ /* Add the DCON device */
+
+ dcon_device = platform_device_alloc("dcon", -1);
+
+ if (dcon_device == NULL) {
+ printk(KERN_ERR "dcon: Unable to create the DCON device\n");
+ rc = -ENOMEM;
+ goto eirq;
+ }
+
+ if ((rc = platform_device_add(dcon_device))) {
+ printk(KERN_ERR "dcon: Unable to add the DCON device\n");
+ goto edev;
+ }
+
+ for(i = 0; i < ARRAY_SIZE(dcon_device_files); i++)
+ device_create_file(&dcon_device->dev, &dcon_device_files[i]);
+
+ /* Add the backlight device for the DCON */
+
+ dcon_client = client;
+
+ dcon_bl_dev = backlight_device_register("dcon-bl", &dcon_device->dev,
+ NULL, &dcon_bl_ops);
+
+ if (IS_ERR(dcon_bl_dev)) {
+ printk(KERN_INFO "Could not register the backlight device for the DCON (%ld)\n", PTR_ERR(dcon_bl_dev));
+ dcon_bl_dev = NULL;
+ }
+ else {
+ dcon_bl_dev->props.max_brightness = 15;
+ dcon_bl_dev->props.power = FB_BLANK_UNBLANK;
+ dcon_bl_dev->props.brightness = dcon_get_backlight();
+
+ backlight_update_status(dcon_bl_dev);
+ }
+
+ register_reboot_notifier(&dcon_nb);
+ console_event_register(&dcon_console_nb);
+
+ printk(KERN_INFO "olpc-dcon: Discovered DCON version %x\n", ver & 0xFF);
+
+ return 0;
+
+ edev:
+ platform_device_unregister(dcon_device);
+ dcon_device = NULL;
+ eirq:
+ free_irq(DCON_IRQ, &dcon_driver);
+ ei2c:
+ i2c_detach_client(client);
+ eclient:
+ kfree(client);
+
+ return rc;
+}
+
+static int dcon_attach(struct i2c_adapter *adap)
+{
+ int ret;
+
+ ret = i2c_probe(adap, &addr_data, dcon_probe);
+
+ if (dcon_client == NULL)
+ printk(KERN_ERR "olpc-dcon: No DCON found on SMBus\n");
+
+ return ret;
+}
+
+static int dcon_detach(struct i2c_client *client)
+{
+ int rc;
+ dcon_client = NULL;
+
+ unregister_reboot_notifier(&dcon_nb);
+ console_event_unregister(&dcon_console_nb);
+
+ free_irq(DCON_IRQ, &dcon_driver);
+
+ if ((rc = i2c_detach_client(client)) == 0)
+ kfree(i2c_get_clientdata(client));
+
+ if (dcon_bl_dev != NULL)
+ backlight_device_unregister(dcon_bl_dev);
+
+ if (dcon_device != NULL)
+ platform_device_unregister(dcon_device);
+ cancel_work_sync(&dcon_work);
+
+ return rc;
+}
+
+
+#ifdef CONFIG_PM
+static int dcon_suspend(struct i2c_client *client, pm_message_t state)
+{
+ if (dcon_sleep_val != DCON_ACTIVE)
+ return 0;
+
+ /* Set up the DCON to have the source */
+ return dcon_set_source_sync(DCON_SOURCE_DCON);
+}
+
+static int dcon_resume(struct i2c_client *client)
+{
+ int x;
+ if (dcon_sleep_val != DCON_ACTIVE)
+ return 0;
+
+ /* HACK: ensure the bus is stable */
+ do {
+ x = dcon_read(DCON_REG_ID);
+ } while (x < 0);
+
+ return dcon_set_source(DCON_SOURCE_CPU);
+}
+
+#endif
+
+static irqreturn_t dcon_interrupt(int irq, void *id)
+{
+ int status = inl(gpio_base + GPIOx_READ_BACK) >> 5;
+
+ /* Clear the negative edge status for GPIO7 */
+ outl(1 << 7, gpio_base + GPIOx_NEGEDGE_STS);
+
+ switch (status & 3) {
+ case 3:
+ printk(KERN_DEBUG "olpc-dcon: DCONLOAD_MISSED interrupt\n");
+ break;
+ case 2: /* switch to DCON mode */
+ case 1: /* switch to CPU mode */
+ dcon_switched = 1;
+ wake_up(&dcon_wait_queue);
+ break;
+ case 0:
+ printk(KERN_DEBUG "olpc-dcon: scanline interrupt w/CPU\n");
+ }
+
+ return IRQ_HANDLED;
+}
+
+static struct i2c_driver dcon_driver = {
+ .driver = {
+ .name = "OLPC-DCON",
+ },
+ .id = I2C_DRIVERID_DCON,
+ .attach_adapter = dcon_attach,
+ .detach_client = dcon_detach,
+#ifdef CONFIG_PM
+ .suspend = dcon_suspend,
+ .resume = dcon_resume,
+#endif
+};
+
+
+static int __init olpc_dcon_init(void)
+{
+ i2c_add_driver(&dcon_driver);
+ return 0;
+}
+
+static void __exit olpc_dcon_exit(void)
+{
+ i2c_del_driver(&dcon_driver);
+}
+
+module_init(olpc_dcon_init);
+module_exit(olpc_dcon_exit);
+
+MODULE_LICENSE("GPL");
--- /dev/null
+#ifndef OLPC_DCON_H_
+#define OLPC_DCON_H_
+
+/* DCON registers */
+
+#define DCON_REG_ID 0
+#define DCON_REG_MODE 1
+
+#define MODE_PASSTHRU (1<<0)
+#define MODE_SLEEP (1<<1)
+#define MODE_SLEEP_AUTO (1<<2)
+#define MODE_BL_ENABLE (1<<3)
+#define MODE_BLANK (1<<4)
+#define MODE_CSWIZZLE (1<<5)
+#define MODE_COL_AA (1<<6)
+#define MODE_MONO_LUMA (1<<7)
+#define MODE_SCAN_INT (1<<8)
+#define MODE_CLOCKDIV (1<<9)
+#define MODE_DEBUG (1<<14)
+#define MODE_SELFTEST (1<<15)
+
+#define DCON_REG_HRES 2
+#define DCON_REG_HTOTAL 3
+#define DCON_REG_HSYNC_WIDTH 4
+#define DCON_REG_VRES 5
+#define DCON_REG_VTOTAL 6
+#define DCON_REG_VSYNC_WIDTH 7
+#define DCON_REG_TIMEOUT 8
+#define DCON_REG_SCAN_INT 9
+#define DCON_REG_BRIGHT 10
+
+/* GPIO registers (CS5536) */
+
+#define MSR_LBAR_GPIO 0x5140000C
+
+#define GPIOx_OUT_VAL 0x00
+#define GPIOx_OUT_EN 0x04
+#define GPIOx_IN_EN 0x20
+#define GPIOx_INV_EN 0x24
+#define GPIOx_IN_FLTR_EN 0x28
+#define GPIOx_EVNTCNT_EN 0x2C
+#define GPIOx_READ_BACK 0x30
+#define GPIOx_EVNT_EN 0x38
+#define GPIOx_NEGEDGE_EN 0x44
+#define GPIOx_NEGEDGE_STS 0x4C
+#define GPIO_FLT7_AMNT 0xD8
+#define GPIO_MAP_X 0xE0
+#define GPIO_MAP_Y 0xE4
+#define GPIO_FE7_SEL 0xF7
+
+
+/* Status values */
+
+#define DCONSTAT_SCANINT 0
+#define DCONSTAT_SCANINT_DCON 1
+#define DCONSTAT_DISPLAYLOAD 2
+#define DCONSTAT_MISSED 3
+
+/* Source values */
+
+#define DCON_SOURCE_DCON 0
+#define DCON_SOURCE_CPU 1
+
+/* Output values */
+#define DCON_OUTPUT_COLOR 0
+#define DCON_OUTPUT_MONO 1
+
+/* Sleep values */
+#define DCON_ACTIVE 0
+#define DCON_SLEEP 1
+
+/* Interrupt */
+#define DCON_IRQ 6
+
+#endif
--- /dev/null
+/*
+ * Definitions for Open Firmware client interface on 32-bit system.
+ * OF Cell size is 4. Integer properties are encoded big endian,
+ * as with all OF implementations.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#ifndef _OFW_H
+#define _OFW_H
+
+extern int ofw(char *, int, int, ...);
+
+#endif
--- /dev/null
+/* OLPC machine specific definitions */
+
+#ifndef ASM_OLPC_H_
+#define ASM_OLPC_H_
+
+#include <asm/geode.h>
+
+struct olpc_platform_t {
+ int flags;
+ int boardrev;
+ int ecver;
+};
+
+#define OLPC_F_PRESENT 0x01
+#define OLPC_F_DCON 0x02
+#define OLPC_F_VSA 0x04
+
+enum
+{
+ OLPC_REV_A = 0,
+
+ OLPC_REV_PRE_B1,
+ OLPC_REV_B1,
+ OLPC_REV_PRE_B2,
+ OLPC_REV_B2,
+ OLPC_REV_PRE_B3,
+ OLPC_REV_B3,
+ OLPC_REV_B4,
+ OLPC_REV_C1,
+ OLPC_REV_R1,
+ OLPC_REV_UNKNOWN /* this should always come last */
+};
+
+#ifndef CONFIG_OLPC
+
+static inline int machine_is_olpc(void) { return 0; }
+static inline int olpc_has_dcon(void) { return 0; }
+static inline int olpc_has_vsa(void) { return 0; }
+static inline int olpc_get_rev(void) { return OLPC_REV_UNKNOWN; }
+
+#else
+
+extern struct olpc_platform_t olpc_platform_info;
+
+static inline int
+machine_is_olpc(void)
+{
+ return (olpc_platform_info.flags & OLPC_F_PRESENT) ? 1 : 0;
+}
+
+static inline int
+olpc_has_dcon(void)
+{
+ return (olpc_platform_info.flags & OLPC_F_DCON) ? 1 : 0;
+}
+
+static inline int
+olpc_has_vsa(void)
+{
+ return (olpc_platform_info.flags & OLPC_F_VSA) ? 1 : 0;
+}
+
+static inline int
+olpc_get_rev(void)
+{
+ return olpc_platform_info.boardrev;
+}
+
+static inline int
+olpc_rev_after(int rev)
+{
+ return olpc_platform_info.boardrev > rev &&
+ olpc_platform_info.boardrev != OLPC_REV_UNKNOWN;
+}
+
+static inline int
+olpc_rev_before(int rev)
+{
+ return olpc_platform_info.boardrev < rev ||
+ olpc_platform_info.boardrev == OLPC_REV_UNKNOWN;
+}
+
+#endif
+
+/* EC functions */
+
+int olpc_ec_cmd(unsigned char cmd, unsigned char *inbuf, size_t inlen,
+ unsigned char *outbuf, size_t outlen);
+
+void olpc_register_battery_callback(void (*f)(unsigned long));
+void olpc_deregister_battery_callback(void);
+
+/* EC commands and responses */
+
+/* SCI source values */
+
+#define EC_SCI_SRC_EMPTY 0x00
+#define EC_SCI_SRC_GAME 0x01
+#define EC_SCI_SRC_BATTERY 0x02
+#define EC_SCI_SRC_BATSOC 0x04
+#define EC_SCI_SRC_BATERR 0x08
+#define EC_SCI_SRC_EBOOK 0x10
+#define EC_SCI_SRC_WLAN 0x20
+#define EC_SCI_SRC_ACPWR 0x40
+
+/* GPIO assignments */
+
+#define OLPC_GPIO_MIC_AC 1
+#define OLPC_GPIO_DCON_IRQ 7
+#define OLPC_GPIO_THRM_ALRM 10
+#define OLPC_GPIO_WORKAUX 24
+#define OLPC_GPIO_LID 26
+#define OLPC_GPIO_ECSCI 27
+
+#endif
+
--- /dev/null
+#ifndef _I386_PROM_H
+#define _I386_PROM_H
+#ifdef __KERNEL__
+
+
+/*
+ * Definitions for talking to the Open Firmware PROM on
+ * Power Macintosh computers.
+ *
+ * Copyright (C) 1996-2005 Paul Mackerras.
+ *
+ * Updates for PPC64 by Peter Bergner & David Engebretsen, IBM Corp.
+ * Updates for SPARC64 by David S. Miller
+ * Updates for i386/OLPC by Andres Salomon
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/types.h>
+#include <linux/proc_fs.h>
+#include <asm/atomic.h>
+
+typedef u32 phandle;
+typedef u32 ihandle;
+
+struct property {
+ char *name;
+ int length;
+ void *value;
+ struct property *next;
+};
+
+struct device_node {
+ const char *name;
+ const char *type;
+ phandle node;
+// phandle linux_phandle;
+ char *path_component_name;
+ char *full_name;
+
+ struct property *properties;
+ struct property *deadprops; /* removed properties */
+ struct device_node *parent;
+ struct device_node *child;
+ struct device_node *sibling;
+ struct device_node *next; /* next device of same type */
+ struct device_node *allnext; /* next in list of all nodes */
+ struct proc_dir_entry *pde; /* this node's proc directory */
+ struct kref kref;
+ unsigned long _flags;
+ void *data;
+};
+
+/* flag descriptions */
+#define OF_DYNAMIC 1 /* node and properties were allocated via kmalloc */
+
+#define OF_IS_DYNAMIC(x) test_bit(OF_DYNAMIC, &x->_flags)
+#define OF_MARK_DYNAMIC(x) set_bit(OF_DYNAMIC, &x->_flags)
+
+#define OF_BAD_ADDR ((u64)-1)
+
+static inline void set_node_proc_entry(struct device_node *dn, struct proc_dir_entry *de)
+{
+ dn->pde = de;
+}
+
+extern struct device_node *of_find_node_by_name(struct device_node *from,
+ const char *name);
+#define for_each_node_by_name(dn, name) \
+ for (dn = of_find_node_by_name(NULL, name); dn; \
+ dn = of_find_node_by_name(dn, name))
+extern struct device_node *of_find_node_by_type(struct device_node *from,
+ const char *type);
+#define for_each_node_by_type(dn, type) \
+ for (dn = of_find_node_by_type(NULL, type); dn; \
+ dn = of_find_node_by_type(dn, type))
+extern struct device_node *of_find_compatible_node(struct device_node *from,
+ const char *type, const char *compat);
+extern struct device_node *of_find_node_by_path(const char *path);
+extern struct device_node *of_find_node_by_phandle(phandle handle);
+extern struct device_node *of_get_parent(const struct device_node *node);
+extern struct device_node *of_get_next_child(const struct device_node *node,
+ struct device_node *prev);
+extern struct property *of_find_property(const struct device_node *np,
+ const char *name,
+ int *lenp);
+//extern struct device_node *of_node_get(struct device_node *node);
+//extern void of_node_put(struct device_node *node);
+extern int of_device_is_compatible(const struct device_node *device,
+ const char *);
+extern const void *of_get_property(const struct device_node *node,
+ const char *name,
+ int *lenp);
+#define get_property(node,name,lenp) of_get_property(node,name,lenp)
+extern int of_set_property(struct device_node *node, const char *name, void *val, int len);
+extern int of_getintprop_default(struct device_node *np,
+ const char *name,
+ int def);
+extern int of_n_addr_cells(struct device_node *np);
+extern int of_n_size_cells(struct device_node *np);
+
+extern void prom_build_devicetree(void);
+
+#endif /* __KERNEL__ */
+#endif
--- /dev/null
+/*
+ * Driver model for batteries
+ *
+ * © 2006 David Woodhouse <dwmw2@infradead.org>
+ *
+ * Based on LED Class support, by John Lenz and Richard Purdie:
+ *
+ * © 2005 John Lenz <lenz@cs.wisc.edu>
+ * © 2005-2006 Richard Purdie <rpurdie@openedhand.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+#ifndef __LINUX_BATTERY_H__
+#define __LINUX_BATTERY_H__
+
+struct device;
+struct class_device;
+
+/*
+ * Battery Core
+ */
+#define PWRDEV_TYPE_BATTERY 0
+#define PWRDEV_TYPE_AC 1
+
+#define BAT_STAT_PRESENT (1<<0)
+#define BAT_STAT_LOW (1<<1)
+#define BAT_STAT_FULL (1<<2)
+#define BAT_STAT_CHARGING (1<<3)
+#define BAT_STAT_DISCHARGING (1<<4)
+#define BAT_STAT_OVERTEMP (1<<5)
+#define BAT_STAT_CRITICAL (1<<6)
+#define BAT_STAT_FIRE (1<<7)
+#define BAT_STAT_CHARGE_DONE (1<<8)
+
+/* Thou shalt not export any attributes in sysfs except these, and
+ with these units: */
+#define BAT_INFO_STATUS "status" /* Not free-form. Use
+ provided function */
+#define BAT_INFO_TEMP1 "temp1" /* °C/1000 */
+#define BAT_INFO_TEMP1_NAME "temp1_name" /* string */
+
+#define BAT_INFO_TEMP2 "temp2" /* °C/1000 */
+#define BAT_INFO_TEMP2_NAME "temp2_name" /* string */
+
+#define BAT_INFO_VOLTAGE "voltage" /* mV */
+#define BAT_INFO_VOLTAGE_DESIGN "voltage_design" /* mV */
+
+#define BAT_INFO_CURRENT "current" /* mA */
+#define BAT_INFO_CURRENT_NOW "current_now" /* mA */
+
+#define BAT_INFO_POWER "power" /* mW */
+#define BAT_INFO_POWER_NOW "power_now" /* mW */
+
+/* The following capacity/charge properties are represented in either
+ mA or mW. The CAP_UNITS property MUST be provided if any of these are. */
+#define BAT_INFO_RATE "rate" /* CAP_UNITS */
+#define BAT_INFO_CAP_LEFT "capacity_left" /* CAP_UNITS*h */
+#define BAT_INFO_CAP_DESIGN "capacity_design" /* CAP_UNITS*h */
+#define BAT_INFO_CAP_LAST_FULL "capacity_last_full" /* CAP_UNITS*h */
+#define BAT_INFO_CAP_LOW "capacity_low_thresh" /* CAP_UNITS*h */
+#define BAT_INFO_CAP_WARN "capacity_warn_thresh" /* CAP_UNITS*h */
+#define BAT_INFO_CAP_UNITS "capacity_units" /* string: must be
+ either mA or mW */
+
+#define BAT_INFO_CAP_PCT "capacity_percentage" /* integer */
+
+#define BAT_INFO_TIME_EMPTY "time_to_empty" /* seconds */
+#define BAT_INFO_TIME_EMPTY_NOW "time_to_empty_now" /* seconds */
+#define BAT_INFO_TIME_FULL "time_to_full" /* seconds */
+#define BAT_INFO_TIME_FULL_NOW "time_to_full_now" /* seconds */
+
+#define BAT_INFO_MANUFACTURER "manufacturer" /* string */
+#define BAT_INFO_TECHNOLOGY "technology" /* string */
+#define BAT_INFO_MODEL "model" /* string */
+#define BAT_INFO_SERIAL "serial" /* string */
+#define BAT_INFO_OEM_INFO "oem_info" /* string */
+
+#define BAT_INFO_CYCLE_COUNT "cycle_count" /* integer */
+#define BAT_INFO_DATE_MFR "date_manufactured" /* YYYY[-MM[-DD]] */
+#define BAT_INFO_DATE_FIRST_USE "date_first_use" /* YYYY[-MM[-DD]] */
+
+struct battery_dev {
+ int status_cap;
+ int id;
+ int type;
+ const char *name;
+
+ struct device *dev;
+};
+
+int battery_device_register(struct device *parent,
+ struct battery_dev *battery_cdev);
+void battery_device_unregister(struct battery_dev *battery_cdev);
+
+
+ssize_t battery_attribute_show_status(char *buf, unsigned long status);
+ssize_t battery_attribute_show_ac_status(char *buf, unsigned long status);
+#endif /* __LINUX_BATTERY_H__ */
--- /dev/null
+#include <sound/driver.h>
+#include <sound/core.h>
+#include <sound/info.h>
+#include <sound/control.h>
+#include <sound/ac97_codec.h>
+
+#include <asm/olpc.h>
+#include "cs5535audio.h"
+
+/*
+ * OLPC has an additional feature on top of the regular AD1888 codec features.
+ * It has an Analog Input mode that is switched into (after disabling the
+ * High Pass Filter) via GPIO. It is only supported on B2 and later models.
+ */
+
+int olpc_ai_enable(struct snd_ac97 *ac97, u8 val)
+{
+ int err;
+
+ /*
+ * update the High Pass Filter (via AC97_AD_TEST2), and then set
+ * Analog Input mode through a GPIO.
+ */
+
+ if (val) {
+ err = snd_ac97_update_bits(ac97, AC97_AD_TEST2,
+ 1<<AC97_AD_HPFD_SHIFT, 1<<AC97_AD_HPFD_SHIFT);
+ geode_gpio_set(OLPC_GPIO_MIC_AC, GPIO_OUTPUT_VAL);
+ }
+ else {
+ err = snd_ac97_update_bits(ac97, AC97_AD_TEST2,
+ 1<<AC97_AD_HPFD_SHIFT, 0);
+ geode_gpio_clear(OLPC_GPIO_MIC_AC, GPIO_OUTPUT_VAL);
+ }
+ if (err < 0)
+ snd_printk(KERN_ERR "Error updating AD_TEST2: %d\n", err);
+
+ return err;
+}
+EXPORT_SYMBOL_GPL(olpc_ai_enable);
+
+static int snd_cs5535audio_ai_info(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_info *uinfo)
+{
+ uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
+ uinfo->count = 1;
+ uinfo->value.integer.min = 0;
+ uinfo->value.integer.max = 1;
+ return 0;
+}
+
+static int snd_cs5535audio_ai_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ ucontrol->value.integer.value[0] = geode_gpio_isset(OLPC_GPIO_MIC_AC,
+ GPIO_OUTPUT_VAL);
+ return 0;
+}
+
+static int snd_cs5535audio_ai_put(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct cs5535audio *cs5535au = snd_kcontrol_chip(kcontrol);
+ struct snd_ac97 *ac97 = cs5535au->ac97;
+
+ olpc_ai_enable(ac97, ucontrol->value.integer.value[0]);
+
+ return 1;
+}
+
+static struct snd_kcontrol_new snd_cs5535audio_controls __devinitdata =
+{
+ .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
+ .name = "DC Mode Enable",
+ .info = snd_cs5535audio_ai_info,
+ .get = snd_cs5535audio_ai_get,
+ .put = snd_cs5535audio_ai_put,
+ .private_value = 0
+};
+
+void __devinit olpc_prequirks(struct snd_card *card,
+ struct snd_ac97_template *ac97)
+{
+ /* Bail if this isn't an OLPC platform */
+ if (!machine_is_olpc())
+ return;
+
+ /* If on an OLPC B3 or higher, invert EAPD. */
+ if (olpc_rev_after(OLPC_REV_B2))
+ ac97->scaps |= AC97_SCAP_INV_EAPD;
+}
+
+int __devinit olpc_quirks(struct snd_card *card, struct snd_ac97 *ac97)
+{
+ struct snd_ctl_elem_id elem;
+
+ /* Bail if this isn't an OLPC platform */
+ if (!machine_is_olpc())
+ return 0;
+
+ /* drop the original ad1888 HPF control */
+ memset(&elem, 0, sizeof(elem));
+ elem.iface = SNDRV_CTL_ELEM_IFACE_MIXER;
+ strcpy(elem.name, "High Pass Filter Enable");
+ snd_ctl_remove_id(card, &elem);
+
+ /* add the override for OLPC's HPF */
+ return snd_ctl_add(card, snd_ctl_new1(&snd_cs5535audio_controls,
+ ac97->private_data));
+}
projects / openwrt / staging / florian.git / commitdiff