target/linux/at91/patches-5.10/146-pinctrl-at91-pio4-add-support-for-slew-rate.patch

   1 From bd819c78346012ae0627b1cd4f6ceb1b51162c71 Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Wed, 27 Jan 2021 13:45:44 +0200
   4 Subject: [PATCH 146/247] pinctrl: at91-pio4: add support for slew-rate
   5
   6 SAMA7G5 supports slew rate configuration. Adapt the driver for this.
   7 For output switching frequencies lower than 50MHz the slew rate needs to
   8 be enabled. Since most of the pins on SAMA7G5 fall into this category
   9 enabled the slew rate by default.
  10
  11 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  12 Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
  13 Link: https://lore.kernel.org/r/1611747945-29960-3-git-send-email-claudiu.beznea@microchip.com
  14 Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
  15 ---
  16  drivers/pinctrl/pinctrl-at91-pio4.c | 27 +++++++++++++++++++++++++++
  17  1 file changed, 27 insertions(+)
  18
  19 --- a/drivers/pinctrl/pinctrl-at91-pio4.c
  20 +++ b/drivers/pinctrl/pinctrl-at91-pio4.c
  21 @@ -36,6 +36,7 @@
  22  #define                ATMEL_PIO_DIR_MASK              BIT(8)
  23  #define                ATMEL_PIO_PUEN_MASK             BIT(9)
  24  #define                ATMEL_PIO_PDEN_MASK             BIT(10)
  25 +#define                ATMEL_PIO_SR_MASK               BIT(11)
  26  #define                ATMEL_PIO_IFEN_MASK             BIT(12)
  27  #define                ATMEL_PIO_IFSCEN_MASK           BIT(13)
  28  #define                ATMEL_PIO_OPD_MASK              BIT(14)
  29 @@ -76,10 +77,12 @@
  30   * @nbanks: number of PIO banks
  31   * @last_bank_count: number of lines in the last bank (can be less than
  32   *     the rest of the banks).
  33 + * @slew_rate_support: slew rate support
  34   */
  35  struct atmel_pioctrl_data {
  36         unsigned nbanks;
  37         unsigned last_bank_count;
  38 +       unsigned int slew_rate_support;
  39  };
  40
  41  struct atmel_group {
  42 @@ -117,6 +120,7 @@ struct atmel_pin {
  43   * @pm_suspend_backup: backup/restore register values on suspend/resume
  44   * @dev: device entry for the Atmel PIO controller.
  45   * @node: node of the Atmel PIO controller.
  46 + * @slew_rate_support: slew rate support
  47   */
  48  struct atmel_pioctrl {
  49         void __iomem            *reg_base;
  50 @@ -138,6 +142,7 @@ struct atmel_pioctrl {
  51         } *pm_suspend_backup;
  52         struct device           *dev;
  53         struct device_node      *node;
  54 +       unsigned int            slew_rate_support;
  55  };
  56
  57  static const char * const atmel_functions[] = {
  58 @@ -760,6 +765,13 @@ static int atmel_conf_pin_config_group_g
  59                         return -EINVAL;
  60                 arg = 1;
  61                 break;
  62 +       case PIN_CONFIG_SLEW_RATE:
  63 +               if (!atmel_pioctrl->slew_rate_support)
  64 +                       return -EOPNOTSUPP;
  65 +               if (!(res & ATMEL_PIO_SR_MASK))
  66 +                       return -EINVAL;
  67 +               arg = 1;
  68 +               break;
  69         case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
  70                 if (!(res & ATMEL_PIO_DRVSTR_MASK))
  71                         return -EINVAL;
  72 @@ -793,6 +805,10 @@ static int atmel_conf_pin_config_group_s
  73                 dev_dbg(pctldev->dev, "%s: pin=%u, config=0x%lx\n",
  74                         __func__, pin_id, configs[i]);
  75
  76 +               /* Keep slew rate enabled by default. */
  77 +               if (atmel_pioctrl->slew_rate_support)
  78 +                       conf |= ATMEL_PIO_SR_MASK;
  79 +
  80                 switch (param) {
  81                 case PIN_CONFIG_BIAS_DISABLE:
  82                         conf &= (~ATMEL_PIO_PUEN_MASK);
  83 @@ -850,6 +866,13 @@ static int atmel_conf_pin_config_group_s
  84                                         ATMEL_PIO_SODR);
  85                         }
  86                         break;
  87 +               case PIN_CONFIG_SLEW_RATE:
  88 +                       if (!atmel_pioctrl->slew_rate_support)
  89 +                               break;
  90 +                       /* And remove it if explicitly requested. */
  91 +                       if (arg == 0)
  92 +                               conf &= ~ATMEL_PIO_SR_MASK;
  93 +                       break;
  94                 case ATMEL_PIN_CONFIG_DRIVE_STRENGTH:
  95                         switch (arg) {
  96                         case ATMEL_PIO_DRVSTR_LO:
  97 @@ -901,6 +924,8 @@ static void atmel_conf_pin_config_dbg_sh
  98                 seq_printf(s, "%s ", "open-drain");
  99         if (conf & ATMEL_PIO_SCHMITT_MASK)
 100                 seq_printf(s, "%s ", "schmitt");
 101 +       if (atmel_pioctrl->slew_rate_support && (conf & ATMEL_PIO_SR_MASK))
 102 +               seq_printf(s, "%s ", "slew-rate");
 103         if (conf & ATMEL_PIO_DRVSTR_MASK) {
 104                 switch ((conf & ATMEL_PIO_DRVSTR_MASK) >> ATMEL_PIO_DRVSTR_OFFSET) {
 105                 case ATMEL_PIO_DRVSTR_ME:
 106 @@ -994,6 +1019,7 @@ static const struct atmel_pioctrl_data a
 107  static const struct atmel_pioctrl_data microchip_sama7g5_pioctrl_data = {
 108         .nbanks                 = 5,
 109         .last_bank_count        = 8, /* sama7g5 has only PE0 to PE7 */
 110 +       .slew_rate_support      = 1,
 111  };
 112
 113  static const struct of_device_id atmel_pctrl_of_match[] = {
 114 @@ -1039,6 +1065,7 @@ static int atmel_pinctrl_probe(struct pl
 115                 atmel_pioctrl->npins -= ATMEL_PIO_NPINS_PER_BANK;
 116                 atmel_pioctrl->npins += atmel_pioctrl_data->last_bank_count;
 117         }
 118 +       atmel_pioctrl->slew_rate_support = atmel_pioctrl_data->slew_rate_support;
 119
 120         atmel_pioctrl->reg_base = devm_platform_ioremap_resource(pdev, 0);
 121         if (IS_ERR(atmel_pioctrl->reg_base))