target/linux/at91/patches-5.10/173-media-atmel-atmel-isc-add-register-description-for-a.patch

   1 From 87b581b1197df5f77bd65819d0428f2404c6b764 Mon Sep 17 00:00:00 2001
   2 From: Eugen Hristev <eugen.hristev@microchip.com>
   3 Date: Tue, 13 Apr 2021 12:57:15 +0200
   4 Subject: [PATCH 173/247] media: atmel: atmel-isc: add register description for
   5  additional modules
   6
   7 Add register description for additional pipeline modules: the
   8 Defective Pixel Correction (DPC) and the Vertical and Horizontal Scaler(VHXS)
   9
  10 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
  11 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
  12 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
  13 ---
  14  drivers/media/platform/atmel/atmel-isc-regs.h | 67 +++++++++++++++++++
  15  1 file changed, 67 insertions(+)
  16
  17 --- a/drivers/media/platform/atmel/atmel-isc-regs.h
  18 +++ b/drivers/media/platform/atmel/atmel-isc-regs.h
  19 @@ -90,6 +90,46 @@
  20  #define ISC_INT_DDONE          BIT(8)
  21  #define ISC_INT_HISDONE                BIT(12)
  22
  23 +/* ISC DPC Control Register */
  24 +#define ISC_DPC_CTRL   0x40
  25 +
  26 +#define ISC_DPC_CTRL_DPCEN     BIT(0)
  27 +#define ISC_DPC_CTRL_GDCEN     BIT(1)
  28 +#define ISC_DPC_CTRL_BLCEN     BIT(2)
  29 +
  30 +/* ISC DPC Config Register */
  31 +#define ISC_DPC_CFG    0x44
  32 +
  33 +#define ISC_DPC_CFG_BAYSEL_SHIFT       0
  34 +
  35 +#define ISC_DPC_CFG_EITPOL             BIT(4)
  36 +
  37 +#define ISC_DPC_CFG_TA_ENABLE          BIT(14)
  38 +#define ISC_DPC_CFG_TC_ENABLE          BIT(13)
  39 +#define ISC_DPC_CFG_TM_ENABLE          BIT(12)
  40 +
  41 +#define ISC_DPC_CFG_RE_MODE            BIT(17)
  42 +
  43 +#define ISC_DPC_CFG_GDCCLP_SHIFT       20
  44 +#define ISC_DPC_CFG_GDCCLP_MASK                GENMASK(22, 20)
  45 +
  46 +#define ISC_DPC_CFG_BLOFF_SHIFT                24
  47 +#define ISC_DPC_CFG_BLOFF_MASK         GENMASK(31, 24)
  48 +
  49 +#define ISC_DPC_CFG_BAYCFG_SHIFT       0
  50 +#define ISC_DPC_CFG_BAYCFG_MASK                GENMASK(1, 0)
  51 +/* ISC DPC Threshold Median Register */
  52 +#define ISC_DPC_THRESHM        0x48
  53 +
  54 +/* ISC DPC Threshold Closest Register */
  55 +#define ISC_DPC_THRESHC        0x4C
  56 +
  57 +/* ISC DPC Threshold Average Register */
  58 +#define ISC_DPC_THRESHA        0x50
  59 +
  60 +/* ISC DPC STatus Register */
  61 +#define ISC_DPC_SR     0x54
  62 +
  63  /* ISC White Balance Control Register */
  64  #define ISC_WB_CTRL     0x00000058
  65
  66 @@ -153,6 +193,33 @@
  67  /* ISC_Gamma Correction Green Entry Register */
  68  #define ISC_GAM_RENTRY 0x00000298
  69
  70 +/* ISC VHXS Control Register */
  71 +#define ISC_VHXS_CTRL  0x398
  72 +
  73 +/* ISC VHXS Source Size Register */
  74 +#define ISC_VHXS_SS    0x39C
  75 +
  76 +/* ISC VHXS Destination Size Register */
  77 +#define ISC_VHXS_DS    0x3A0
  78 +
  79 +/* ISC Vertical Factor Register */
  80 +#define ISC_VXS_FACT   0x3a4
  81 +
  82 +/* ISC Horizontal Factor Register */
  83 +#define ISC_HXS_FACT   0x3a8
  84 +
  85 +/* ISC Vertical Config Register */
  86 +#define ISC_VXS_CFG    0x3ac
  87 +
  88 +/* ISC Horizontal Config Register */
  89 +#define ISC_HXS_CFG    0x3b0
  90 +
  91 +/* ISC Vertical Tap Register */
  92 +#define ISC_VXS_TAP    0x3b4
  93 +
  94 +/* ISC Horizontal Tap Register */
  95 +#define ISC_HXS_TAP    0x434
  96 +
  97  /* Offset for CSC register specific to sama5d2 product */
  98  #define ISC_SAMA5D2_CSC_OFFSET 0
  99