target/linux/at91/patches-5.10/205-ARM-at91-pm-add-support-for-waiting-MCK1.4.patch

   1 From 67face049c62cb37cf93da26b7fea037228d1d3d Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Thu, 15 Apr 2021 13:49:55 +0300
   4 Subject: [PATCH 205/247] ARM: at91: pm: add support for waiting MCK1..4
   5
   6 SAMA7G5 has 5 master clocks 0..4. MCK0 is controlled differently than
   7 MCK 1..4. MCK 1..4 should also be saved/restored in the last phase of
   8 suspend/resume. Thus, adapt wait_mckrdy to support also MCK1..4.
   9
  10 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  11 Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
  12 Link: https://lore.kernel.org/r/20210415105010.569620-10-claudiu.beznea@microchip.com
  13 ---
  14  arch/arm/mach-at91/pm_suspend.S | 48 ++++++++++++++++++++++++---------
  15  1 file changed, 35 insertions(+), 13 deletions(-)
  16
  17 --- a/arch/arm/mach-at91/pm_suspend.S
  18 +++ b/arch/arm/mach-at91/pm_suspend.S
  19 @@ -22,11 +22,23 @@ tmp3        .req    r6
  20
  21  /*
  22   * Wait until master clock is ready (after switching master clock source)
  23 + *
  24 + * @r_mckid:   register holding master clock identifier
  25 + *
  26 + * Side effects: overwrites r7, r8
  27   */
  28 -       .macro wait_mckrdy
  29 -1:     ldr     tmp1, [pmc, #AT91_PMC_SR]
  30 -       tst     tmp1, #AT91_PMC_MCKRDY
  31 -       beq     1b
  32 +       .macro wait_mckrdy r_mckid
  33 +#ifdef CONFIG_SOC_SAMA7
  34 +       cmp     \r_mckid, #0
  35 +       beq     1f
  36 +       mov     r7, #AT91_PMC_MCKXRDY
  37 +       b       2f
  38 +#endif
  39 +1:     mov     r7, #AT91_PMC_MCKRDY
  40 +2:     ldr     r8, [pmc, #AT91_PMC_SR]
  41 +       and     r8, r7
  42 +       cmp     r8, r7
  43 +       bne     2b
  44         .endm
  45
  46  /*
  47 @@ -231,7 +243,9 @@ sr_dis_exit:
  48         bic     tmp1, tmp1, #AT91_PMC_PRES
  49         orr     tmp1, tmp1, #AT91_PMC_PRES_64
  50         str     tmp1, [pmc, tmp3]
  51 -       wait_mckrdy
  52 +
  53 +       mov     tmp3, #0
  54 +       wait_mckrdy tmp3
  55         b       1f
  56
  57  0:
  58 @@ -267,10 +281,13 @@ sr_dis_exit:
  59         bne     5f
  60
  61         /* Set lowest prescaler for fast resume. */
  62 +       ldr     tmp3, .mckr_offset
  63         ldr     tmp1, [pmc, tmp3]
  64         bic     tmp1, tmp1, #AT91_PMC_PRES
  65         str     tmp1, [pmc, tmp3]
  66 -       wait_mckrdy
  67 +
  68 +       mov     tmp3, #0
  69 +       wait_mckrdy tmp3
  70         b       6f
  71
  72  5:     /* Restore RC oscillator state */
  73 @@ -307,6 +324,7 @@ sr_dis_exit:
  74  .macro at91_pm_ulp1_mode
  75         ldr     pmc, .pmc_base
  76         ldr     tmp2, .mckr_offset
  77 +       mov     tmp3, #0
  78
  79         /* Save RC oscillator state and check if it is enabled. */
  80         ldr     tmp1, [pmc, #AT91_PMC_SR]
  81 @@ -348,7 +366,7 @@ sr_dis_exit:
  82         orr     tmp1, tmp1, #AT91_PMC_CSS_MAIN
  83         str     tmp1, [pmc, tmp2]
  84
  85 -       wait_mckrdy
  86 +       wait_mckrdy tmp3
  87
  88         /* Enter the ULP1 mode by set WAITMODE bit in CKGR_MOR */
  89         ldr     tmp1, [pmc, #AT91_CKGR_MOR]
  90 @@ -361,7 +379,7 @@ sr_dis_exit:
  91         nop
  92         nop
  93
  94 -       wait_mckrdy
  95 +       wait_mckrdy tmp3
  96
  97         /* Enable the crystal oscillator */
  98         ldr     tmp1, [pmc, #AT91_CKGR_MOR]
  99 @@ -377,7 +395,7 @@ sr_dis_exit:
 100         bic     tmp1, tmp1, #AT91_PMC_CSS
 101         str     tmp1, [pmc, tmp2]
 102
 103 -       wait_mckrdy
 104 +       wait_mckrdy tmp3
 105
 106         /* Switch main clock source to crystal oscillator */
 107         ldr     tmp1, [pmc, #AT91_CKGR_MOR]
 108 @@ -394,7 +412,7 @@ sr_dis_exit:
 109         orr     tmp1, tmp1, #AT91_PMC_CSS_MAIN
 110         str     tmp1, [pmc, tmp2]
 111
 112 -       wait_mckrdy
 113 +       wait_mckrdy tmp3
 114
 115         /* Restore RC oscillator state */
 116         ldr     tmp1, .saved_osc_status
 117 @@ -573,10 +591,12 @@ sr_dis_exit:
 118  save_mck:
 119         str     tmp1, [pmc, tmp2]
 120
 121 -       wait_mckrdy
 122 +       mov     tmp3, #0
 123 +       wait_mckrdy tmp3
 124
 125         at91_plla_disable
 126
 127 +       ldr     tmp3, .pm_mode
 128         cmp     tmp3, #AT91_PM_ULP1
 129         beq     ulp1_mode
 130
 131 @@ -599,7 +619,8 @@ ulp_exit:
 132         ldr     tmp2, .saved_mckr
 133         str     tmp2, [pmc, tmp1]
 134
 135 -       wait_mckrdy
 136 +       mov     tmp3, #0
 137 +       wait_mckrdy tmp3
 138
 139  .endm
 140
 141 @@ -611,7 +632,8 @@ ulp_exit:
 142         bic     tmp1, tmp1, #AT91_PMC_CSS
 143         str     tmp1, [pmc, tmp2]
 144
 145 -       wait_mckrdy
 146 +       mov     tmp3, #0
 147 +       wait_mckrdy tmp3
 148
 149         /*BUMEN*/
 150         ldr     r0, .sfrbu