target/linux/ath79/patches-4.14/0016-MIPS-ath79-add-support-for-QCA953x-SoC.patch

   1 From cff23ba486e3c5d17c4d7e446f5eddead855c101 Mon Sep 17 00:00:00 2001
   2 From: John Crispin <john@phrozen.org>
   3 Date: Tue, 6 Mar 2018 08:45:55 +0100
   4 Subject: [PATCH 16/27] MIPS: ath79: add support for QCA953x SoC
   5
   6 Note that the clock calculation looks very similar to the QCA955x, but the
   7 meaning of the bits CPUCLK_FROM_CPUPLL and DDRCLK_FROM_DDRPLL is reversed.
   8
   9 Signed-off-by: Matthias Schiffer <mschiffer@universe-factory.net>
  10 ---
  11  arch/mips/ath79/Kconfig                  |  6 ++-
  12  arch/mips/ath79/clock.c                  | 87 ++++++++++++++++++++++++++++++++
  13  arch/mips/ath79/common.c                 |  4 ++
  14  arch/mips/ath79/dev-common.c             |  4 ++
  15  arch/mips/ath79/early_printk.c           |  2 +
  16  arch/mips/ath79/irq.c                    | 33 +++++++++++-
  17  arch/mips/ath79/setup.c                  | 21 ++++++--
  18  arch/mips/include/asm/mach-ath79/ath79.h | 11 ++++
  19  8 files changed, 162 insertions(+), 6 deletions(-)
  20
  21 diff --git a/arch/mips/ath79/Kconfig b/arch/mips/ath79/Kconfig
  22 index 9547cf1ea38d..b03f5c8b9d1e 100644
  23 --- a/arch/mips/ath79/Kconfig
  24 +++ b/arch/mips/ath79/Kconfig
  25 @@ -94,6 +94,10 @@ config SOC_AR934X
  26         select PCI_AR724X if PCI
  27         def_bool n
  28
  29 +config SOC_QCA953X
  30 +       select USB_ARCH_HAS_EHCI
  31 +       def_bool n
  32 +
  33  config SOC_QCA955X
  34         select HW_HAS_PCI
  35         select PCI_AR724X if PCI
  36 @@ -115,7 +119,7 @@ config ATH79_DEV_USB
  37         def_bool n
  38
  39  config ATH79_DEV_WMAC
  40 -       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA955X)
  41 +       depends on (SOC_AR913X || SOC_AR933X || SOC_AR934X || SOC_QCA953X || SOC_QCA955X)
  42         def_bool n
  43
  44  endif
  45 diff --git a/arch/mips/ath79/clock.c b/arch/mips/ath79/clock.c
  46 index 6b1000b6a6a6..b9595b2d1b65 100644
  47 --- a/arch/mips/ath79/clock.c
  48 +++ b/arch/mips/ath79/clock.c
  49 @@ -355,6 +355,91 @@ static void __init ar934x_clocks_init(void)
  50         iounmap(dpll_base);
  51  }
  52
  53 +static void __init qca953x_clocks_init(void)
  54 +{
  55 +       unsigned long ref_rate;
  56 +       unsigned long cpu_rate;
  57 +       unsigned long ddr_rate;
  58 +       unsigned long ahb_rate;
  59 +       u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
  60 +       u32 cpu_pll, ddr_pll;
  61 +       u32 bootstrap;
  62 +
  63 +       bootstrap = ath79_reset_rr(QCA953X_RESET_REG_BOOTSTRAP);
  64 +       if (bootstrap & QCA953X_BOOTSTRAP_REF_CLK_40)
  65 +               ref_rate = 40 * 1000 * 1000;
  66 +       else
  67 +               ref_rate = 25 * 1000 * 1000;
  68 +
  69 +       pll = ath79_pll_rr(QCA953X_PLL_CPU_CONFIG_REG);
  70 +       out_div = (pll >> QCA953X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
  71 +                 QCA953X_PLL_CPU_CONFIG_OUTDIV_MASK;
  72 +       ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
  73 +                 QCA953X_PLL_CPU_CONFIG_REFDIV_MASK;
  74 +       nint = (pll >> QCA953X_PLL_CPU_CONFIG_NINT_SHIFT) &
  75 +              QCA953X_PLL_CPU_CONFIG_NINT_MASK;
  76 +       frac = (pll >> QCA953X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
  77 +              QCA953X_PLL_CPU_CONFIG_NFRAC_MASK;
  78 +
  79 +       cpu_pll = nint * ref_rate / ref_div;
  80 +       cpu_pll += frac * (ref_rate >> 6) / ref_div;
  81 +       cpu_pll /= (1 << out_div);
  82 +
  83 +       pll = ath79_pll_rr(QCA953X_PLL_DDR_CONFIG_REG);
  84 +       out_div = (pll >> QCA953X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
  85 +                 QCA953X_PLL_DDR_CONFIG_OUTDIV_MASK;
  86 +       ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
  87 +                 QCA953X_PLL_DDR_CONFIG_REFDIV_MASK;
  88 +       nint = (pll >> QCA953X_PLL_DDR_CONFIG_NINT_SHIFT) &
  89 +              QCA953X_PLL_DDR_CONFIG_NINT_MASK;
  90 +       frac = (pll >> QCA953X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
  91 +              QCA953X_PLL_DDR_CONFIG_NFRAC_MASK;
  92 +
  93 +       ddr_pll = nint * ref_rate / ref_div;
  94 +       ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4);
  95 +       ddr_pll /= (1 << out_div);
  96 +
  97 +       clk_ctrl = ath79_pll_rr(QCA953X_PLL_CLK_CTRL_REG);
  98 +
  99 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
 100 +                 QCA953X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
 101 +
 102 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
 103 +               cpu_rate = ref_rate;
 104 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
 105 +               cpu_rate = cpu_pll / (postdiv + 1);
 106 +       else
 107 +               cpu_rate = ddr_pll / (postdiv + 1);
 108 +
 109 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
 110 +                 QCA953X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
 111 +
 112 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
 113 +               ddr_rate = ref_rate;
 114 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
 115 +               ddr_rate = ddr_pll / (postdiv + 1);
 116 +       else
 117 +               ddr_rate = cpu_pll / (postdiv + 1);
 118 +
 119 +       postdiv = (clk_ctrl >> QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
 120 +                 QCA953X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
 121 +
 122 +       if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
 123 +               ahb_rate = ref_rate;
 124 +       else if (clk_ctrl & QCA953X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
 125 +               ahb_rate = ddr_pll / (postdiv + 1);
 126 +       else
 127 +               ahb_rate = cpu_pll / (postdiv + 1);
 128 +
 129 +       ath79_add_sys_clkdev("ref", ref_rate);
 130 +       ath79_add_sys_clkdev("cpu", cpu_rate);
 131 +       ath79_add_sys_clkdev("ddr", ddr_rate);
 132 +       ath79_add_sys_clkdev("ahb", ahb_rate);
 133 +
 134 +       clk_add_alias("wdt", NULL, "ref", NULL);
 135 +       clk_add_alias("uart", NULL, "ref", NULL);
 136 +}
 137 +
 138  static void __init qca955x_clocks_init(void)
 139  {
 140         unsigned long ref_rate;
 141 @@ -450,6 +535,8 @@ void __init ath79_clocks_init(void)
 142                 ar933x_clocks_init();
 143         else if (soc_is_ar934x())
 144                 ar934x_clocks_init();
 145 +       else if (soc_is_qca953x())
 146 +               qca953x_clocks_init();
 147         else if (soc_is_qca955x())
 148                 qca955x_clocks_init();
 149         else
 150 diff --git a/arch/mips/ath79/common.c b/arch/mips/ath79/common.c
 151 index a32a9181a296..a485a7c35b9b 100644
 152 --- a/arch/mips/ath79/common.c
 153 +++ b/arch/mips/ath79/common.c
 154 @@ -103,6 +103,8 @@ void ath79_device_reset_set(u32 mask)
 155                 reg = AR933X_RESET_REG_RESET_MODULE;
 156         else if (soc_is_ar934x())
 157                 reg = AR934X_RESET_REG_RESET_MODULE;
 158 +       else if (soc_is_qca953x())
 159 +               reg = QCA953X_RESET_REG_RESET_MODULE;
 160         else if (soc_is_qca955x())
 161                 reg = QCA955X_RESET_REG_RESET_MODULE;
 162         else
 163 @@ -131,6 +133,8 @@ void ath79_device_reset_clear(u32 mask)
 164                 reg = AR933X_RESET_REG_RESET_MODULE;
 165         else if (soc_is_ar934x())
 166                 reg = AR934X_RESET_REG_RESET_MODULE;
 167 +       else if (soc_is_qca953x())
 168 +               reg = QCA953X_RESET_REG_RESET_MODULE;
 169         else if (soc_is_qca955x())
 170                 reg = QCA955X_RESET_REG_RESET_MODULE;
 171         else
 172 diff --git a/arch/mips/ath79/dev-common.c b/arch/mips/ath79/dev-common.c
 173 index 9d0172a4dc69..99d8b88f1e6d 100644
 174 --- a/arch/mips/ath79/dev-common.c
 175 +++ b/arch/mips/ath79/dev-common.c
 176 @@ -85,6 +85,7 @@ void __init ath79_register_uart(void)
 177             soc_is_ar724x() ||
 178             soc_is_ar913x() ||
 179             soc_is_ar934x() ||
 180 +           soc_is_qca953x() ||
 181             soc_is_qca955x()) {
 182                 ath79_uart_data[0].uartclk = uart_clk_rate;
 183                 platform_device_register(&ath79_uart_device);
 184 @@ -148,6 +149,9 @@ void __init ath79_gpio_init(void)
 185         } else if (soc_is_ar934x()) {
 186                 ath79_gpio_pdata.ngpios = AR934X_GPIO_COUNT;
 187                 ath79_gpio_pdata.oe_inverted = 1;
 188 +       } else if (soc_is_qca953x()) {
 189 +               ath79_gpio_pdata.ngpios = QCA953X_GPIO_COUNT;
 190 +               ath79_gpio_pdata.oe_inverted = 1;
 191         } else if (soc_is_qca955x()) {
 192                 ath79_gpio_pdata.ngpios = QCA955X_GPIO_COUNT;
 193                 ath79_gpio_pdata.oe_inverted = 1;
 194 diff --git a/arch/mips/ath79/early_printk.c b/arch/mips/ath79/early_printk.c
 195 index ec3978678653..cc00839b7181 100644
 196 --- a/arch/mips/ath79/early_printk.c
 197 +++ b/arch/mips/ath79/early_printk.c
 198 @@ -116,6 +116,8 @@ static void prom_putchar_init(void)
 199         case REV_ID_MAJOR_AR9341:
 200         case REV_ID_MAJOR_AR9342:
 201         case REV_ID_MAJOR_AR9344:
 202 +       case REV_ID_MAJOR_QCA9533:
 203 +       case REV_ID_MAJOR_QCA9533_V2:
 204         case REV_ID_MAJOR_QCA9556:
 205         case REV_ID_MAJOR_QCA9558:
 206                 _prom_putchar = prom_putchar_ar71xx;
 207 diff --git a/arch/mips/ath79/irq.c b/arch/mips/ath79/irq.c
 208 index 2dfff1f19004..756b5aee3500 100644
 209 --- a/arch/mips/ath79/irq.c
 210 +++ b/arch/mips/ath79/irq.c
 211 @@ -56,6 +56,34 @@ static void ar934x_ip2_irq_init(void)
 212         irq_set_chained_handler(ATH79_CPU_IRQ(2), ar934x_ip2_irq_dispatch);
 213  }
 214
 215 +static void qca953x_ip2_irq_dispatch(struct irq_desc *desc)
 216 +{
 217 +       u32 status;
 218 +
 219 +       status = ath79_reset_rr(QCA953X_RESET_REG_PCIE_WMAC_INT_STATUS);
 220 +
 221 +       if (status & QCA953X_PCIE_WMAC_INT_PCIE_ALL) {
 222 +               ath79_ddr_wb_flush(3);
 223 +               generic_handle_irq(ATH79_IP2_IRQ(0));
 224 +       } else if (status & QCA953X_PCIE_WMAC_INT_WMAC_ALL) {
 225 +               ath79_ddr_wb_flush(4);
 226 +               generic_handle_irq(ATH79_IP2_IRQ(1));
 227 +       } else {
 228 +               spurious_interrupt();
 229 +       }
 230 +}
 231 +
 232 +static void qca953x_irq_init(void)
 233 +{
 234 +       int i;
 235 +
 236 +       for (i = ATH79_IP2_IRQ_BASE;
 237 +            i < ATH79_IP2_IRQ_BASE + ATH79_IP2_IRQ_COUNT; i++)
 238 +               irq_set_chip_and_handler(i, &dummy_irq_chip, handle_level_irq);
 239 +
 240 +       irq_set_chained_handler(ATH79_CPU_IRQ(2), qca953x_ip2_irq_dispatch);
 241 +}
 242 +
 243  static void qca955x_ip2_irq_dispatch(struct irq_desc *desc)
 244  {
 245         u32 status;
 246 @@ -143,7 +171,7 @@ void __init arch_init_irq(void)
 247             soc_is_ar913x() || soc_is_ar933x()) {
 248                 irq_wb_chan2 = 3;
 249                 irq_wb_chan3 = 2;
 250 -       } else if (soc_is_ar934x()) {
 251 +       } else if (soc_is_ar934x() || soc_is_qca953x()) {
 252                 irq_wb_chan3 = 2;
 253         }
 254
 255 @@ -154,6 +182,7 @@ void __init arch_init_irq(void)
 256         else if (soc_is_ar724x() ||
 257                  soc_is_ar933x() ||
 258                  soc_is_ar934x() ||
 259 +                soc_is_qca953x() ||
 260                  soc_is_qca955x())
 261                 misc_is_ar71xx = false;
 262         else
 263 @@ -164,6 +193,8 @@ void __init arch_init_irq(void)
 264
 265         if (soc_is_ar934x())
 266                 ar934x_ip2_irq_init();
 267 +       else if (soc_is_qca953x())
 268 +               qca953x_irq_init();
 269         else if (soc_is_qca955x())
 270                 qca955x_irq_init();
 271  }
 272 diff --git a/arch/mips/ath79/setup.c b/arch/mips/ath79/setup.c
 273 index 26a058d58d37..f782ae6c77d6 100644
 274 --- a/arch/mips/ath79/setup.c
 275 +++ b/arch/mips/ath79/setup.c
 276 @@ -60,6 +60,7 @@ static void __init ath79_detect_sys_type(void)
 277         u32 major;
 278         u32 minor;
 279         u32 rev = 0;
 280 +       u32 ver = 1;
 281
 282         id = ath79_reset_rr(AR71XX_RESET_REG_REV_ID);
 283         major = id & REV_ID_MAJOR_MASK;
 284 @@ -152,6 +153,17 @@ static void __init ath79_detect_sys_type(void)
 285                 rev = id & AR934X_REV_ID_REVISION_MASK;
 286                 break;
 287
 288 +       case REV_ID_MAJOR_QCA9533_V2:
 289 +               ver = 2;
 290 +               ath79_soc_rev = 2;
 291 +               /* drop through */
 292 +
 293 +       case REV_ID_MAJOR_QCA9533:
 294 +               ath79_soc = ATH79_SOC_QCA9533;
 295 +               chip = "9533";
 296 +               rev = id & QCA953X_REV_ID_REVISION_MASK;
 297 +               break;
 298 +
 299         case REV_ID_MAJOR_QCA9556:
 300                 ath79_soc = ATH79_SOC_QCA9556;
 301                 chip = "9556";
 302 @@ -168,11 +180,12 @@ static void __init ath79_detect_sys_type(void)
 303                 panic("ath79: unknown SoC, id:0x%08x", id);
 304         }
 305
 306 -       ath79_soc_rev = rev;
 307 +       if (ver == 1)
 308 +               ath79_soc_rev = rev;
 309
 310 -       if (soc_is_qca955x())
 311 -               sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s rev %u",
 312 -                       chip, rev);
 313 +       if (soc_is_qca953x() || soc_is_qca955x())
 314 +               sprintf(ath79_sys_type, "Qualcomm Atheros QCA%s ver %u rev %u",
 315 +                       chip, ver, rev);
 316         else
 317                 sprintf(ath79_sys_type, "Atheros AR%s rev %u", chip, rev);
 318         pr_info("SoC: %s\n", ath79_sys_type);
 319 diff --git a/arch/mips/include/asm/mach-ath79/ath79.h b/arch/mips/include/asm/mach-ath79/ath79.h
 320 index 6e6c0fead776..98a7ccf3d358 100644
 321 --- a/arch/mips/include/asm/mach-ath79/ath79.h
 322 +++ b/arch/mips/include/asm/mach-ath79/ath79.h
 323 @@ -32,6 +32,7 @@ enum ath79_soc_type {
 324         ATH79_SOC_AR9341,
 325         ATH79_SOC_AR9342,
 326         ATH79_SOC_AR9344,
 327 +       ATH79_SOC_QCA9533,
 328         ATH79_SOC_QCA9556,
 329         ATH79_SOC_QCA9558,
 330  };
 331 @@ -100,6 +101,16 @@ static inline int soc_is_ar934x(void)
 332         return soc_is_ar9341() || soc_is_ar9342() || soc_is_ar9344();
 333  }
 334
 335 +static inline int soc_is_qca9533(void)
 336 +{
 337 +       return ath79_soc == ATH79_SOC_QCA9533;
 338 +}
 339 +
 340 +static inline int soc_is_qca953x(void)
 341 +{
 342 +       return soc_is_qca9533();
 343 +}
 344 +
 345  static inline int soc_is_qca9556(void)
 346  {
 347         return ath79_soc == ATH79_SOC_QCA9556;
 348 --
 349 2.11.0
 350