target/linux/bcm4908/patches-5.10/037-v5.20-0002-arm64-dts-Add-DTS-files-for-bcmbca-SoC-BCM4912.patch

   1 From 1ba56aeb391401c4cb2126c39f90b3cdbfabdb3f Mon Sep 17 00:00:00 2001
   2 From: William Zhang <william.zhang@broadcom.com>
   3 Date: Wed, 1 Jun 2022 13:17:34 -0700
   4 Subject: [PATCH] arm64: dts: Add DTS files for bcmbca SoC BCM4912
   5
   6 Add DTS for ARMv8 based broadband SoC BCM4912. bcm4912.dtsi is the
   7 SoC description DTS header and bcm94912.dts is a simple DTS file for
   8 Broadcom BCM94912 Reference board that only enable the UART port.
   9
  10 Signed-off-by: William Zhang <william.zhang@broadcom.com>
  11 Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
  12 Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
  13 ---
  14  arch/arm64/boot/dts/broadcom/bcmbca/Makefile  |   3 +-
  15  .../boot/dts/broadcom/bcmbca/bcm4912.dtsi     | 128 ++++++++++++++++++
  16  .../boot/dts/broadcom/bcmbca/bcm94912.dts     |  30 ++++
  17  3 files changed, 160 insertions(+), 1 deletion(-)
  18  create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
  19  create mode 100644 arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
  20
  21 --- a/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
  22 +++ b/arch/arm64/boot/dts/broadcom/bcmbca/Makefile
  23 @@ -1,2 +1,3 @@
  24  # SPDX-License-Identifier: GPL-2.0
  25 -dtb-$(CONFIG_ARCH_BCMBCA) += bcm963158.dtb
  26 +dtb-$(CONFIG_ARCH_BCMBCA) += bcm94912.dtb \
  27 +                               bcm963158.dtb
  28 --- /dev/null
  29 +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
  30 @@ -0,0 +1,128 @@
  31 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
  32 +/*
  33 + * Copyright 2022 Broadcom Ltd.
  34 + */
  35 +
  36 +#include <dt-bindings/interrupt-controller/irq.h>
  37 +#include <dt-bindings/interrupt-controller/arm-gic.h>
  38 +
  39 +/ {
  40 +       compatible = "brcm,bcm4912", "brcm,bcmbca";
  41 +       #address-cells = <2>;
  42 +       #size-cells = <2>;
  43 +
  44 +       interrupt-parent = <&gic>;
  45 +
  46 +       cpus {
  47 +               #address-cells = <2>;
  48 +               #size-cells = <0>;
  49 +
  50 +               B53_0: cpu@0 {
  51 +                       compatible = "brcm,brahma-b53";
  52 +                       device_type = "cpu";
  53 +                       reg = <0x0 0x0>;
  54 +                       next-level-cache = <&L2_0>;
  55 +                       enable-method = "psci";
  56 +               };
  57 +
  58 +               B53_1: cpu@1 {
  59 +                       compatible = "brcm,brahma-b53";
  60 +                       device_type = "cpu";
  61 +                       reg = <0x0 0x1>;
  62 +                       next-level-cache = <&L2_0>;
  63 +                       enable-method = "psci";
  64 +               };
  65 +
  66 +               B53_2: cpu@2 {
  67 +                       compatible = "brcm,brahma-b53";
  68 +                       device_type = "cpu";
  69 +                       reg = <0x0 0x2>;
  70 +                       next-level-cache = <&L2_0>;
  71 +                       enable-method = "psci";
  72 +               };
  73 +
  74 +               B53_3: cpu@3 {
  75 +                       compatible = "brcm,brahma-b53";
  76 +                       device_type = "cpu";
  77 +                       reg = <0x0 0x3>;
  78 +                       next-level-cache = <&L2_0>;
  79 +                       enable-method = "psci";
  80 +               };
  81 +
  82 +               L2_0: l2-cache0 {
  83 +                       compatible = "cache";
  84 +               };
  85 +       };
  86 +
  87 +       timer {
  88 +               compatible = "arm,armv8-timer";
  89 +               interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  90 +                       <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  91 +                       <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  92 +                       <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  93 +       };
  94 +
  95 +       pmu: pmu {
  96 +               compatible = "arm,cortex-a53-pmu";
  97 +               interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
  98 +                       <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
  99 +                       <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
 100 +                       <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
 101 +               interrupt-affinity = <&B53_0>, <&B53_1>,
 102 +                       <&B53_2>, <&B53_3>;
 103 +       };
 104 +
 105 +       clocks: clocks {
 106 +               periph_clk: periph-clk {
 107 +                       compatible = "fixed-clock";
 108 +                       #clock-cells = <0>;
 109 +                       clock-frequency = <200000000>;
 110 +               };
 111 +               uart_clk: uart-clk {
 112 +                       compatible = "fixed-factor-clock";
 113 +                       #clock-cells = <0>;
 114 +                       clocks = <&periph_clk>;
 115 +                       clock-div = <4>;
 116 +                       clock-mult = <1>;
 117 +               };
 118 +       };
 119 +
 120 +       psci {
 121 +               compatible = "arm,psci-0.2";
 122 +               method = "smc";
 123 +       };
 124 +
 125 +       axi@81000000 {
 126 +               compatible = "simple-bus";
 127 +               #address-cells = <1>;
 128 +               #size-cells = <1>;
 129 +               ranges = <0x0 0x0 0x81000000 0x8000>;
 130 +
 131 +               gic: interrupt-controller@1000 {
 132 +                       compatible = "arm,gic-400";
 133 +                       #interrupt-cells = <3>;
 134 +                       interrupt-controller;
 135 +                       interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 136 +                       reg = <0x1000 0x1000>,
 137 +                               <0x2000 0x2000>,
 138 +                               <0x4000 0x2000>,
 139 +                               <0x6000 0x2000>;
 140 +               };
 141 +       };
 142 +
 143 +       bus@ff800000 {
 144 +               compatible = "simple-bus";
 145 +               #address-cells = <1>;
 146 +               #size-cells = <1>;
 147 +               ranges = <0x0 0x0 0xff800000 0x800000>;
 148 +
 149 +               uart0: serial@12000 {
 150 +                       compatible = "arm,pl011", "arm,primecell";
 151 +                       reg = <0x12000 0x1000>;
 152 +                       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 153 +                       clocks = <&uart_clk>, <&uart_clk>;
 154 +                       clock-names = "uartclk", "apb_pclk";
 155 +                       status = "disabled";
 156 +               };
 157 +       };
 158 +};
 159 --- /dev/null
 160 +++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm94912.dts
 161 @@ -0,0 +1,30 @@
 162 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
 163 +/*
 164 + * Copyright 2022 Broadcom Ltd.
 165 + */
 166 +
 167 +/dts-v1/;
 168 +
 169 +#include "bcm4912.dtsi"
 170 +
 171 +/ {
 172 +       model = "Broadcom BCM94912 Reference Board";
 173 +       compatible = "brcm,bcm94912", "brcm,bcm4912", "brcm,bcmbca";
 174 +
 175 +       aliases {
 176 +               serial0 = &uart0;
 177 +       };
 178 +
 179 +       chosen {
 180 +               stdout-path = "serial0:115200n8";
 181 +       };
 182 +
 183 +       memory@0 {
 184 +               device_type = "memory";
 185 +               reg = <0x0 0x0 0x0 0x08000000>;
 186 +       };
 187 +};
 188 +
 189 +&uart0 {
 190 +       status = "okay";
 191 +};