target/linux/bmips/patches-5.10/007-v5.12-mips-bmips-dts-add-BCM6368-reset-controller-support.patch

   1 From 7acf84e87857721d66a1ba800c2c50669089f43d Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?=C3=81lvaro=20Fern=C3=A1ndez=20Rojas?= <noltari@gmail.com>
   3 Date: Wed, 17 Jun 2020 12:50:39 +0200
   4 Subject: [PATCH 7/9] mips: bmips: dts: add BCM6368 reset controller support
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 BCM6368 SoCs have a reset controller for certain components.
  10
  11 Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
  12 Acked-by: Florian Fainelli <f.fainelli@gmail.com>
  13 Reviewed-by: Rob Herring <robh@kernel.org>
  14 Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
  15 ---
  16  arch/mips/boot/dts/brcm/bcm6368.dtsi      |  6 ++++++
  17  include/dt-bindings/reset/bcm6368-reset.h | 16 ++++++++++++++++
  18  2 files changed, 22 insertions(+)
  19  create mode 100644 include/dt-bindings/reset/bcm6368-reset.h
  20
  21 --- a/arch/mips/boot/dts/brcm/bcm6368.dtsi
  22 +++ b/arch/mips/boot/dts/brcm/bcm6368.dtsi
  23 @@ -70,6 +70,12 @@
  24                         mask = <0x1>;
  25                 };
  26
  27 +               periph_rst: reset-controller@10000010 {
  28 +                       compatible = "brcm,bcm6345-reset";
  29 +                       reg = <0x10000010 0x4>;
  30 +                       #reset-cells = <1>;
  31 +               };
  32 +
  33                 periph_intc: interrupt-controller@10000020 {
  34                         compatible = "brcm,bcm6345-l1-intc";
  35                         reg = <0x10000020 0x10>,
  36 --- /dev/null
  37 +++ b/include/dt-bindings/reset/bcm6368-reset.h
  38 @@ -0,0 +1,16 @@
  39 +/* SPDX-License-Identifier: GPL-2.0+ */
  40 +
  41 +#ifndef __DT_BINDINGS_RESET_BCM6368_H
  42 +#define __DT_BINDINGS_RESET_BCM6368_H
  43 +
  44 +#define BCM6368_RST_SPI                0
  45 +#define BCM6368_RST_MPI                3
  46 +#define BCM6368_RST_IPSEC      4
  47 +#define BCM6368_RST_EPHY       6
  48 +#define BCM6368_RST_SAR                7
  49 +#define BCM6368_RST_SWITCH     10
  50 +#define BCM6368_RST_USBD       11
  51 +#define BCM6368_RST_USBH       12
  52 +#define BCM6368_RST_PCM                13
  53 +
  54 +#endif /* __DT_BINDINGS_RESET_BCM6368_H */