target/linux/generic/backport-5.10/419-v5.14-mtd-spinand-gigadevice-Support-GD5F1GQ5UExxG.patch

   1 From bd568cc04c675b7fa97214d278a54794c2ecc2ad Mon Sep 17 00:00:00 2001
   2 From: Reto Schneider <reto.schneider@husqvarnagroup.com>
   3 Date: Thu, 11 Feb 2021 12:36:19 +0100
   4 Subject: [PATCH] mtd: spinand: gigadevice: Support GD5F1GQ5UExxG
   5
   6 The relevant changes to the already existing GD5F1GQ4UExxG support has
   7 been determined by consulting the GigaDevice product change notice
   8 AN-0392-10, version 1.0 from November 30, 2020.
   9
  10 As the overlaps are huge, variable names have been generalized
  11 accordingly.
  12
  13 Apart from the lowered ECC strength (4 instead of 8 bits per 512 bytes),
  14 the new device ID, and the extra quad IO dummy byte, no changes had to
  15 be taken into account.
  16
  17 New hardware features are not supported, namely:
  18  - Power on reset
  19  - Unique ID
  20  - Double transfer rate (DTR)
  21  - Parameter page
  22  - Random data quad IO
  23
  24 The inverted semantic of the "driver strength" register bits, defaulting
  25 to 100% instead of 50% for the Q5 devices, got ignored as the driver has
  26 never touched them anyway.
  27
  28 The no longer supported "read from cache during block erase"
  29 functionality is not reflected as the current SPI NAND core does not
  30 support it anyway.
  31
  32 Implementation has been tested on MediaTek MT7688 based GARDENA smart
  33 Gateways using both, GigaDevice GD5F1GQ5UEYIG and GD5F1GQ4UBYIG.
  34
  35 Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
  36 Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de>
  37 Reviewed-by: Stefan Roese <sr@denx.de>
  38 Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
  39 Link: https://lore.kernel.org/linux-mtd/20210211113619.3502-1-code@reto-schneider.ch
  40 (cherry picked from commit 469b992489852b500d39048aa0013639dfe9f2e6)
  41 ---
  42  drivers/mtd/nand/spi/gigadevice.c | 69 +++++++++++++++++++++++++++----
  43  1 file changed, 60 insertions(+), 9 deletions(-)
  44
  45 --- a/drivers/mtd/nand/spi/gigadevice.c
  46 +++ b/drivers/mtd/nand/spi/gigadevice.c
  47 @@ -13,7 +13,10 @@
  48  #define GD5FXGQ4XA_STATUS_ECC_1_7_BITFLIPS     (1 << 4)
  49  #define GD5FXGQ4XA_STATUS_ECC_8_BITFLIPS       (3 << 4)
  50
  51 -#define GD5FXGQ4UEXXG_REG_STATUS2              0xf0
  52 +#define GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS     (1 << 4)
  53 +#define GD5FXGQ5XE_STATUS_ECC_4_BITFLIPS       (3 << 4)
  54 +
  55 +#define GD5FXGQXXEXXG_REG_STATUS2              0xf0
  56
  57  #define GD5FXGQ4UXFXXG_STATUS_ECC_MASK         (7 << 4)
  58  #define GD5FXGQ4UXFXXG_STATUS_ECC_NO_BITFLIPS  (0 << 4)
  59 @@ -102,7 +105,7 @@ static int gd5fxgq4xa_ecc_get_status(str
  60         return -EINVAL;
  61  }
  62
  63 -static int gd5fxgq4_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,
  64 +static int gd5fxgqx_variant2_ooblayout_ecc(struct mtd_info *mtd, int section,
  65                                        struct mtd_oob_region *region)
  66  {
  67         if (section)
  68 @@ -114,7 +117,7 @@ static int gd5fxgq4_variant2_ooblayout_e
  69         return 0;
  70  }
  71
  72 -static int gd5fxgq4_variant2_ooblayout_free(struct mtd_info *mtd, int section,
  73 +static int gd5fxgqx_variant2_ooblayout_free(struct mtd_info *mtd, int section,
  74                                         struct mtd_oob_region *region)
  75  {
  76         if (section)
  77 @@ -127,9 +130,10 @@ static int gd5fxgq4_variant2_ooblayout_f
  78         return 0;
  79  }
  80
  81 -static const struct mtd_ooblayout_ops gd5fxgq4_variant2_ooblayout = {
  82 -       .ecc = gd5fxgq4_variant2_ooblayout_ecc,
  83 -       .free = gd5fxgq4_variant2_ooblayout_free,
  84 +/* Valid for Q4/Q5 and Q6 (untested) devices */
  85 +static const struct mtd_ooblayout_ops gd5fxgqx_variant2_ooblayout = {
  86 +       .ecc = gd5fxgqx_variant2_ooblayout_ecc,
  87 +       .free = gd5fxgqx_variant2_ooblayout_free,
  88  };
  89
  90  static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section,
  91 @@ -165,7 +169,7 @@ static int gd5fxgq4uexxg_ecc_get_status(
  92                                         u8 status)
  93  {
  94         u8 status2;
  95 -       struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQ4UEXXG_REG_STATUS2,
  96 +       struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2,
  97                                                       &status2);
  98         int ret;
  99
 100 @@ -203,6 +207,43 @@ static int gd5fxgq4uexxg_ecc_get_status(
 101         return -EINVAL;
 102  }
 103
 104 +static int gd5fxgq5xexxg_ecc_get_status(struct spinand_device *spinand,
 105 +                                       u8 status)
 106 +{
 107 +       u8 status2;
 108 +       struct spi_mem_op op = SPINAND_GET_FEATURE_OP(GD5FXGQXXEXXG_REG_STATUS2,
 109 +                                                     &status2);
 110 +       int ret;
 111 +
 112 +       switch (status & STATUS_ECC_MASK) {
 113 +       case STATUS_ECC_NO_BITFLIPS:
 114 +               return 0;
 115 +
 116 +       case GD5FXGQ5XE_STATUS_ECC_1_4_BITFLIPS:
 117 +               /*
 118 +                * Read status2 register to determine a more fine grained
 119 +                * bit error status
 120 +                */
 121 +               ret = spi_mem_exec_op(spinand->spimem, &op);
 122 +               if (ret)
 123 +                       return ret;
 124 +
 125 +               /*
 126 +                * 1 ... 4 bits are flipped (and corrected)
 127 +                */
 128 +               /* bits sorted this way (1...0): ECCSE1, ECCSE0 */
 129 +               return ((status2 & STATUS_ECC_MASK) >> 4) + 1;
 130 +
 131 +       case STATUS_ECC_UNCOR_ERROR:
 132 +               return -EBADMSG;
 133 +
 134 +       default:
 135 +               break;
 136 +       }
 137 +
 138 +       return -EINVAL;
 139 +}
 140 +
 141  static int gd5fxgq4ufxxg_ecc_get_status(struct spinand_device *spinand,
 142                                         u8 status)
 143  {
 144 @@ -282,7 +323,7 @@ static const struct spinand_info gigadev
 145                                               &write_cache_variants,
 146                                               &update_cache_variants),
 147                      SPINAND_HAS_QE_BIT,
 148 -                    SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
 149 +                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
 150                                      gd5fxgq4uexxg_ecc_get_status)),
 151         SPINAND_INFO("GD5F1GQ4UFxxG",
 152                      SPINAND_ID(SPINAND_READID_METHOD_OPCODE, 0xb1, 0x48),
 153 @@ -292,8 +333,18 @@ static const struct spinand_info gigadev
 154                                               &write_cache_variants,
 155                                               &update_cache_variants),
 156                      SPINAND_HAS_QE_BIT,
 157 -                    SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout,
 158 +                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
 159                                      gd5fxgq4ufxxg_ecc_get_status)),
 160 +       SPINAND_INFO("GD5F1GQ5UExxG",
 161 +                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x51),
 162 +                    NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
 163 +                    NAND_ECCREQ(4, 512),
 164 +                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
 165 +                                             &write_cache_variants,
 166 +                                             &update_cache_variants),
 167 +                    SPINAND_HAS_QE_BIT,
 168 +                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
 169 +                                    gd5fxgq5xexxg_ecc_get_status)),
 170  };
 171
 172  static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {