projects / openwrt / staging / ldir.git / blob
? search:


9378c3d422a5205b9a48b8a9cf8c655531779d5c
[openwrt/staging/ldir.git] / target / linux / generic / backport-5.10 / 610-v5.13-32-net-ethernet-mtk_eth_soc-add-support-for-initializin.patch
1 From: Felix Fietkau <nbd@nbd.name>
2 Date: Wed, 24 Mar 2021 02:30:53 +0100
3 Subject: [PATCH] net: ethernet: mtk_eth_soc: add support for
4 initializing the PPE
5
6 The PPE (packet processing engine) is used to offload NAT/routed or even
7 bridged flows. This patch brings up the PPE and uses it to get a packet
8 hash. It also contains some functionality that will be used to bring up
9 flow offloading.
10
11 Signed-off-by: Felix Fietkau <nbd@nbd.name>
12 Signed-off-by: Pablo Neira Ayuso <pablo@netfilter.org>
13 ---
14 create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe.c
15 create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe.h
16 create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c
17 create mode 100644 drivers/net/ethernet/mediatek/mtk_ppe_regs.h
18
19 --- a/drivers/net/ethernet/mediatek/Makefile
20 +++ b/drivers/net/ethernet/mediatek/Makefile
21 @@ -4,5 +4,5 @@
22 #
23
24 obj-$(CONFIG_NET_MEDIATEK_SOC) += mtk_eth.o
25 -mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o
26 +mtk_eth-y := mtk_eth_soc.o mtk_sgmii.o mtk_eth_path.o mtk_ppe.o mtk_ppe_debugfs.o
27 obj-$(CONFIG_NET_MEDIATEK_STAR_EMAC) += mtk_star_emac.o
28 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
29 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
30 @@ -2300,7 +2300,10 @@ static int mtk_open(struct net_device *d
31
32 /* we run 2 netdevs on the same dma ring so we only bring it up once */
33 if (!refcount_read(&eth->dma_refcnt)) {
34 - int err = mtk_start_dma(eth);
35 + u32 gdm_config = MTK_GDMA_TO_PDMA;
36 + int err;
37 +
38 + err = mtk_start_dma(eth);
39
40 if (err)
41 if (err) {
42 @@ -2308,7 +2311,10 @@ static int mtk_open(struct net_device *d
43 return err;
44 }
45
46 - mtk_gdm_config(eth, MTK_GDMA_TO_PDMA);
47 + if (eth->soc->offload_version && mtk_ppe_start(&eth->ppe) == 0)
48 + gdm_config = MTK_GDMA_TO_PPE;
49 +
50 + mtk_gdm_config(eth, gdm_config);
51
52 napi_enable(&eth->tx_napi);
53 napi_enable(&eth->rx_napi);
54 @@ -2375,6 +2381,9 @@ static int mtk_stop(struct net_device *d
55
56 mtk_dma_free(eth);
57
58 + if (eth->soc->offload_version)
59 + mtk_ppe_stop(&eth->ppe);
60 +
61 return 0;
62 }
63
64 @@ -3103,6 +3112,13 @@ static int mtk_probe(struct platform_dev
65 goto err_free_dev;
66 }
67
68 + if (eth->soc->offload_version) {
69 + err = mtk_ppe_init(&eth->ppe, eth->dev,
70 + eth->base + MTK_ETH_PPE_BASE, 2);
71 + if (err)
72 + goto err_free_dev;
73 + }
74 +
75 for (i = 0; i < MTK_MAX_DEVS; i++) {
76 if (!eth->netdev[i])
77 continue;
78 @@ -3177,6 +3193,7 @@ static const struct mtk_soc_data mt7621_
79 .hw_features = MTK_HW_FEATURES,
80 .required_clks = MT7621_CLKS_BITMAP,
81 .required_pctl = false,
82 + .offload_version = 2,
83 };
84
85 static const struct mtk_soc_data mt7622_data = {
86 @@ -3185,6 +3202,7 @@ static const struct mtk_soc_data mt7622_
87 .hw_features = MTK_HW_FEATURES,
88 .required_clks = MT7622_CLKS_BITMAP,
89 .required_pctl = false,
90 + .offload_version = 2,
91 };
92
93 static const struct mtk_soc_data mt7623_data = {
94 --- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
95 +++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
96 @@ -15,6 +15,7 @@
97 #include <linux/u64_stats_sync.h>
98 #include <linux/refcount.h>
99 #include <linux/phylink.h>
100 +#include "mtk_ppe.h"
101
102 #define MTK_QDMA_PAGE_SIZE 2048
103 #define MTK_MAX_RX_LENGTH 1536
104 @@ -86,6 +87,7 @@
105 #define MTK_GDMA_TCS_EN BIT(21)
106 #define MTK_GDMA_UCS_EN BIT(20)
107 #define MTK_GDMA_TO_PDMA 0x0
108 +#define MTK_GDMA_TO_PPE 0x4444
109 #define MTK_GDMA_DROP_ALL 0x7777
110
111 /* Unicast Filter MAC Address Register - Low */
112 @@ -315,6 +317,12 @@
113 #define RX_DMA_VID(_x) ((_x) & 0xfff)
114
115 /* QDMA descriptor rxd4 */
116 +#define MTK_RXD4_FOE_ENTRY GENMASK(13, 0)
117 +#define MTK_RXD4_PPE_CPU_REASON GENMASK(18, 14)
118 +#define MTK_RXD4_SRC_PORT GENMASK(21, 19)
119 +#define MTK_RXD4_ALG GENMASK(31, 22)
120 +
121 +/* QDMA descriptor rxd4 */
122 #define RX_DMA_L4_VALID BIT(24)
123 #define RX_DMA_L4_VALID_PDMA BIT(30) /* when PDMA is used */
124 #define RX_DMA_FPORT_SHIFT 19
125 @@ -820,6 +828,7 @@ struct mtk_soc_data {
126 u32 caps;
127 u32 required_clks;
128 bool required_pctl;
129 + u8 offload_version;
130 netdev_features_t hw_features;
131 };
132
133 @@ -919,6 +928,8 @@ struct mtk_eth {
134 u32 tx_int_status_reg;
135 u32 rx_dma_l4_valid;
136 int ip_align;
137 +
138 + struct mtk_ppe ppe;
139 };
140
141 /* struct mtk_mac - the structure that holds the info about the MACs of the
142 --- /dev/null
143 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.c
144 @@ -0,0 +1,511 @@
145 +// SPDX-License-Identifier: GPL-2.0-only
146 +/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */
147 +
148 +#include <linux/kernel.h>
149 +#include <linux/jiffies.h>
150 +#include <linux/delay.h>
151 +#include <linux/io.h>
152 +#include <linux/etherdevice.h>
153 +#include <linux/platform_device.h>
154 +#include "mtk_ppe.h"
155 +#include "mtk_ppe_regs.h"
156 +
157 +static void ppe_w32(struct mtk_ppe *ppe, u32 reg, u32 val)
158 +{
159 + writel(val, ppe->base + reg);
160 +}
161 +
162 +static u32 ppe_r32(struct mtk_ppe *ppe, u32 reg)
163 +{
164 + return readl(ppe->base + reg);
165 +}
166 +
167 +static u32 ppe_m32(struct mtk_ppe *ppe, u32 reg, u32 mask, u32 set)
168 +{
169 + u32 val;
170 +
171 + val = ppe_r32(ppe, reg);
172 + val &= ~mask;
173 + val |= set;
174 + ppe_w32(ppe, reg, val);
175 +
176 + return val;
177 +}
178 +
179 +static u32 ppe_set(struct mtk_ppe *ppe, u32 reg, u32 val)
180 +{
181 + return ppe_m32(ppe, reg, 0, val);
182 +}
183 +
184 +static u32 ppe_clear(struct mtk_ppe *ppe, u32 reg, u32 val)
185 +{
186 + return ppe_m32(ppe, reg, val, 0);
187 +}
188 +
189 +static int mtk_ppe_wait_busy(struct mtk_ppe *ppe)
190 +{
191 + unsigned long timeout = jiffies + HZ;
192 +
193 + while (time_is_before_jiffies(timeout)) {
194 + if (!(ppe_r32(ppe, MTK_PPE_GLO_CFG) & MTK_PPE_GLO_CFG_BUSY))
195 + return 0;
196 +
197 + usleep_range(10, 20);
198 + }
199 +
200 + dev_err(ppe->dev, "PPE table busy");
201 +
202 + return -ETIMEDOUT;
203 +}
204 +
205 +static void mtk_ppe_cache_clear(struct mtk_ppe *ppe)
206 +{
207 + ppe_set(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR);
208 + ppe_clear(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_CLEAR);
209 +}
210 +
211 +static void mtk_ppe_cache_enable(struct mtk_ppe *ppe, bool enable)
212 +{
213 + mtk_ppe_cache_clear(ppe);
214 +
215 + ppe_m32(ppe, MTK_PPE_CACHE_CTL, MTK_PPE_CACHE_CTL_EN,
216 + enable * MTK_PPE_CACHE_CTL_EN);
217 +}
218 +
219 +static u32 mtk_ppe_hash_entry(struct mtk_foe_entry *e)
220 +{
221 + u32 hv1, hv2, hv3;
222 + u32 hash;
223 +
224 + switch (FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, e->ib1)) {
225 + case MTK_PPE_PKT_TYPE_BRIDGE:
226 + hv1 = e->bridge.src_mac_lo;
227 + hv1 ^= ((e->bridge.src_mac_hi & 0xffff) << 16);
228 + hv2 = e->bridge.src_mac_hi >> 16;
229 + hv2 ^= e->bridge.dest_mac_lo;
230 + hv3 = e->bridge.dest_mac_hi;
231 + break;
232 + case MTK_PPE_PKT_TYPE_IPV4_ROUTE:
233 + case MTK_PPE_PKT_TYPE_IPV4_HNAPT:
234 + hv1 = e->ipv4.orig.ports;
235 + hv2 = e->ipv4.orig.dest_ip;
236 + hv3 = e->ipv4.orig.src_ip;
237 + break;
238 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T:
239 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T:
240 + hv1 = e->ipv6.src_ip[3] ^ e->ipv6.dest_ip[3];
241 + hv1 ^= e->ipv6.ports;
242 +
243 + hv2 = e->ipv6.src_ip[2] ^ e->ipv6.dest_ip[2];
244 + hv2 ^= e->ipv6.dest_ip[0];
245 +
246 + hv3 = e->ipv6.src_ip[1] ^ e->ipv6.dest_ip[1];
247 + hv3 ^= e->ipv6.src_ip[0];
248 + break;
249 + case MTK_PPE_PKT_TYPE_IPV4_DSLITE:
250 + case MTK_PPE_PKT_TYPE_IPV6_6RD:
251 + default:
252 + WARN_ON_ONCE(1);
253 + return MTK_PPE_HASH_MASK;
254 + }
255 +
256 + hash = (hv1 & hv2) | ((~hv1) & hv3);
257 + hash = (hash >> 24) | ((hash & 0xffffff) << 8);
258 + hash ^= hv1 ^ hv2 ^ hv3;
259 + hash ^= hash >> 16;
260 + hash <<= 1;
261 + hash &= MTK_PPE_ENTRIES - 1;
262 +
263 + return hash;
264 +}
265 +
266 +static inline struct mtk_foe_mac_info *
267 +mtk_foe_entry_l2(struct mtk_foe_entry *entry)
268 +{
269 + int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
270 +
271 + if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE)
272 + return &entry->ipv6.l2;
273 +
274 + return &entry->ipv4.l2;
275 +}
276 +
277 +static inline u32 *
278 +mtk_foe_entry_ib2(struct mtk_foe_entry *entry)
279 +{
280 + int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
281 +
282 + if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE)
283 + return &entry->ipv6.ib2;
284 +
285 + return &entry->ipv4.ib2;
286 +}
287 +
288 +int mtk_foe_entry_prepare(struct mtk_foe_entry *entry, int type, int l4proto,
289 + u8 pse_port, u8 *src_mac, u8 *dest_mac)
290 +{
291 + struct mtk_foe_mac_info *l2;
292 + u32 ports_pad, val;
293 +
294 + memset(entry, 0, sizeof(*entry));
295 +
296 + val = FIELD_PREP(MTK_FOE_IB1_STATE, MTK_FOE_STATE_BIND) |
297 + FIELD_PREP(MTK_FOE_IB1_PACKET_TYPE, type) |
298 + FIELD_PREP(MTK_FOE_IB1_UDP, l4proto == IPPROTO_UDP) |
299 + MTK_FOE_IB1_BIND_TTL |
300 + MTK_FOE_IB1_BIND_CACHE;
301 + entry->ib1 = val;
302 +
303 + val = FIELD_PREP(MTK_FOE_IB2_PORT_MG, 0x3f) |
304 + FIELD_PREP(MTK_FOE_IB2_PORT_AG, 0x1f) |
305 + FIELD_PREP(MTK_FOE_IB2_DEST_PORT, pse_port);
306 +
307 + if (is_multicast_ether_addr(dest_mac))
308 + val |= MTK_FOE_IB2_MULTICAST;
309 +
310 + ports_pad = 0xa5a5a500 | (l4proto & 0xff);
311 + if (type == MTK_PPE_PKT_TYPE_IPV4_ROUTE)
312 + entry->ipv4.orig.ports = ports_pad;
313 + if (type == MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T)
314 + entry->ipv6.ports = ports_pad;
315 +
316 + if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) {
317 + entry->ipv6.ib2 = val;
318 + l2 = &entry->ipv6.l2;
319 + } else {
320 + entry->ipv4.ib2 = val;
321 + l2 = &entry->ipv4.l2;
322 + }
323 +
324 + l2->dest_mac_hi = get_unaligned_be32(dest_mac);
325 + l2->dest_mac_lo = get_unaligned_be16(dest_mac + 4);
326 + l2->src_mac_hi = get_unaligned_be32(src_mac);
327 + l2->src_mac_lo = get_unaligned_be16(src_mac + 4);
328 +
329 + if (type >= MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T)
330 + l2->etype = ETH_P_IPV6;
331 + else
332 + l2->etype = ETH_P_IP;
333 +
334 + return 0;
335 +}
336 +
337 +int mtk_foe_entry_set_pse_port(struct mtk_foe_entry *entry, u8 port)
338 +{
339 + u32 *ib2 = mtk_foe_entry_ib2(entry);
340 + u32 val;
341 +
342 + val = *ib2;
343 + val &= ~MTK_FOE_IB2_DEST_PORT;
344 + val |= FIELD_PREP(MTK_FOE_IB2_DEST_PORT, port);
345 + *ib2 = val;
346 +
347 + return 0;
348 +}
349 +
350 +int mtk_foe_entry_set_ipv4_tuple(struct mtk_foe_entry *entry, bool egress,
351 + __be32 src_addr, __be16 src_port,
352 + __be32 dest_addr, __be16 dest_port)
353 +{
354 + int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
355 + struct mtk_ipv4_tuple *t;
356 +
357 + switch (type) {
358 + case MTK_PPE_PKT_TYPE_IPV4_HNAPT:
359 + if (egress) {
360 + t = &entry->ipv4.new;
361 + break;
362 + }
363 + fallthrough;
364 + case MTK_PPE_PKT_TYPE_IPV4_DSLITE:
365 + case MTK_PPE_PKT_TYPE_IPV4_ROUTE:
366 + t = &entry->ipv4.orig;
367 + break;
368 + case MTK_PPE_PKT_TYPE_IPV6_6RD:
369 + entry->ipv6_6rd.tunnel_src_ip = be32_to_cpu(src_addr);
370 + entry->ipv6_6rd.tunnel_dest_ip = be32_to_cpu(dest_addr);
371 + return 0;
372 + default:
373 + WARN_ON_ONCE(1);
374 + return -EINVAL;
375 + }
376 +
377 + t->src_ip = be32_to_cpu(src_addr);
378 + t->dest_ip = be32_to_cpu(dest_addr);
379 +
380 + if (type == MTK_PPE_PKT_TYPE_IPV4_ROUTE)
381 + return 0;
382 +
383 + t->src_port = be16_to_cpu(src_port);
384 + t->dest_port = be16_to_cpu(dest_port);
385 +
386 + return 0;
387 +}
388 +
389 +int mtk_foe_entry_set_ipv6_tuple(struct mtk_foe_entry *entry,
390 + __be32 *src_addr, __be16 src_port,
391 + __be32 *dest_addr, __be16 dest_port)
392 +{
393 + int type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
394 + u32 *src, *dest;
395 + int i;
396 +
397 + switch (type) {
398 + case MTK_PPE_PKT_TYPE_IPV4_DSLITE:
399 + src = entry->dslite.tunnel_src_ip;
400 + dest = entry->dslite.tunnel_dest_ip;
401 + break;
402 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T:
403 + case MTK_PPE_PKT_TYPE_IPV6_6RD:
404 + entry->ipv6.src_port = be16_to_cpu(src_port);
405 + entry->ipv6.dest_port = be16_to_cpu(dest_port);
406 + fallthrough;
407 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T:
408 + src = entry->ipv6.src_ip;
409 + dest = entry->ipv6.dest_ip;
410 + break;
411 + default:
412 + WARN_ON_ONCE(1);
413 + return -EINVAL;
414 + };
415 +
416 + for (i = 0; i < 4; i++)
417 + src[i] = be32_to_cpu(src_addr[i]);
418 + for (i = 0; i < 4; i++)
419 + dest[i] = be32_to_cpu(dest_addr[i]);
420 +
421 + return 0;
422 +}
423 +
424 +int mtk_foe_entry_set_dsa(struct mtk_foe_entry *entry, int port)
425 +{
426 + struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);
427 +
428 + l2->etype = BIT(port);
429 +
430 + if (!(entry->ib1 & MTK_FOE_IB1_BIND_VLAN_LAYER))
431 + entry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, 1);
432 + else
433 + l2->etype |= BIT(8);
434 +
435 + entry->ib1 &= ~MTK_FOE_IB1_BIND_VLAN_TAG;
436 +
437 + return 0;
438 +}
439 +
440 +int mtk_foe_entry_set_vlan(struct mtk_foe_entry *entry, int vid)
441 +{
442 + struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);
443 +
444 + switch (FIELD_GET(MTK_FOE_IB1_BIND_VLAN_LAYER, entry->ib1)) {
445 + case 0:
446 + entry->ib1 |= MTK_FOE_IB1_BIND_VLAN_TAG |
447 + FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, 1);
448 + l2->vlan1 = vid;
449 + return 0;
450 + case 1:
451 + if (!(entry->ib1 & MTK_FOE_IB1_BIND_VLAN_TAG)) {
452 + l2->vlan1 = vid;
453 + l2->etype |= BIT(8);
454 + } else {
455 + l2->vlan2 = vid;
456 + entry->ib1 += FIELD_PREP(MTK_FOE_IB1_BIND_VLAN_LAYER, 1);
457 + }
458 + return 0;
459 + default:
460 + return -ENOSPC;
461 + }
462 +}
463 +
464 +int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid)
465 +{
466 + struct mtk_foe_mac_info *l2 = mtk_foe_entry_l2(entry);
467 +
468 + if (!(entry->ib1 & MTK_FOE_IB1_BIND_VLAN_LAYER) ||
469 + (entry->ib1 & MTK_FOE_IB1_BIND_VLAN_TAG))
470 + l2->etype = ETH_P_PPP_SES;
471 +
472 + entry->ib1 |= MTK_FOE_IB1_BIND_PPPOE;
473 + l2->pppoe_id = sid;
474 +
475 + return 0;
476 +}
477 +
478 +static inline bool mtk_foe_entry_usable(struct mtk_foe_entry *entry)
479 +{
480 + return !(entry->ib1 & MTK_FOE_IB1_STATIC) &&
481 + FIELD_GET(MTK_FOE_IB1_STATE, entry->ib1) != MTK_FOE_STATE_BIND;
482 +}
483 +
484 +int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,
485 + u16 timestamp)
486 +{
487 + struct mtk_foe_entry *hwe;
488 + u32 hash;
489 +
490 + timestamp &= MTK_FOE_IB1_BIND_TIMESTAMP;
491 + entry->ib1 &= ~MTK_FOE_IB1_BIND_TIMESTAMP;
492 + entry->ib1 |= FIELD_PREP(MTK_FOE_IB1_BIND_TIMESTAMP, timestamp);
493 +
494 + hash = mtk_ppe_hash_entry(entry);
495 + hwe = &ppe->foe_table[hash];
496 + if (!mtk_foe_entry_usable(hwe)) {
497 + hwe++;
498 + hash++;
499 +
500 + if (!mtk_foe_entry_usable(hwe))
501 + return -ENOSPC;
502 + }
503 +
504 + memcpy(&hwe->data, &entry->data, sizeof(hwe->data));
505 + wmb();
506 + hwe->ib1 = entry->ib1;
507 +
508 + dma_wmb();
509 +
510 + mtk_ppe_cache_clear(ppe);
511 +
512 + return hash;
513 +}
514 +
515 +int mtk_ppe_init(struct mtk_ppe *ppe, struct device *dev, void __iomem *base,
516 + int version)
517 +{
518 + struct mtk_foe_entry *foe;
519 +
520 + /* need to allocate a separate device, since it PPE DMA access is
521 + * not coherent.
522 + */
523 + ppe->base = base;
524 + ppe->dev = dev;
525 + ppe->version = version;
526 +
527 + foe = dmam_alloc_coherent(ppe->dev, MTK_PPE_ENTRIES * sizeof(*foe),
528 + &ppe->foe_phys, GFP_KERNEL);
529 + if (!foe)
530 + return -ENOMEM;
531 +
532 + ppe->foe_table = foe;
533 +
534 + mtk_ppe_debugfs_init(ppe);
535 +
536 + return 0;
537 +}
538 +
539 +static void mtk_ppe_init_foe_table(struct mtk_ppe *ppe)
540 +{
541 + static const u8 skip[] = { 12, 25, 38, 51, 76, 89, 102 };
542 + int i, k;
543 +
544 + memset(ppe->foe_table, 0, MTK_PPE_ENTRIES * sizeof(ppe->foe_table));
545 +
546 + if (!IS_ENABLED(CONFIG_SOC_MT7621))
547 + return;
548 +
549 + /* skip all entries that cross the 1024 byte boundary */
550 + for (i = 0; i < MTK_PPE_ENTRIES; i += 128)
551 + for (k = 0; k < ARRAY_SIZE(skip); k++)
552 + ppe->foe_table[i + skip[k]].ib1 |= MTK_FOE_IB1_STATIC;
553 +}
554 +
555 +int mtk_ppe_start(struct mtk_ppe *ppe)
556 +{
557 + u32 val;
558 +
559 + mtk_ppe_init_foe_table(ppe);
560 + ppe_w32(ppe, MTK_PPE_TB_BASE, ppe->foe_phys);
561 +
562 + val = MTK_PPE_TB_CFG_ENTRY_80B |
563 + MTK_PPE_TB_CFG_AGE_NON_L4 |
564 + MTK_PPE_TB_CFG_AGE_UNBIND |
565 + MTK_PPE_TB_CFG_AGE_TCP |
566 + MTK_PPE_TB_CFG_AGE_UDP |
567 + MTK_PPE_TB_CFG_AGE_TCP_FIN |
568 + FIELD_PREP(MTK_PPE_TB_CFG_SEARCH_MISS,
569 + MTK_PPE_SEARCH_MISS_ACTION_FORWARD_BUILD) |
570 + FIELD_PREP(MTK_PPE_TB_CFG_KEEPALIVE,
571 + MTK_PPE_KEEPALIVE_DISABLE) |
572 + FIELD_PREP(MTK_PPE_TB_CFG_HASH_MODE, 1) |
573 + FIELD_PREP(MTK_PPE_TB_CFG_SCAN_MODE,
574 + MTK_PPE_SCAN_MODE_KEEPALIVE_AGE) |
575 + FIELD_PREP(MTK_PPE_TB_CFG_ENTRY_NUM,
576 + MTK_PPE_ENTRIES_SHIFT);
577 + ppe_w32(ppe, MTK_PPE_TB_CFG, val);
578 +
579 + ppe_w32(ppe, MTK_PPE_IP_PROTO_CHK,
580 + MTK_PPE_IP_PROTO_CHK_IPV4 | MTK_PPE_IP_PROTO_CHK_IPV6);
581 +
582 + mtk_ppe_cache_enable(ppe, true);
583 +
584 + val = MTK_PPE_FLOW_CFG_IP4_TCP_FRAG |
585 + MTK_PPE_FLOW_CFG_IP4_UDP_FRAG |
586 + MTK_PPE_FLOW_CFG_IP6_3T_ROUTE |
587 + MTK_PPE_FLOW_CFG_IP6_5T_ROUTE |
588 + MTK_PPE_FLOW_CFG_IP6_6RD |
589 + MTK_PPE_FLOW_CFG_IP4_NAT |
590 + MTK_PPE_FLOW_CFG_IP4_NAPT |
591 + MTK_PPE_FLOW_CFG_IP4_DSLITE |
592 + MTK_PPE_FLOW_CFG_L2_BRIDGE |
593 + MTK_PPE_FLOW_CFG_IP4_NAT_FRAG;
594 + ppe_w32(ppe, MTK_PPE_FLOW_CFG, val);
595 +
596 + val = FIELD_PREP(MTK_PPE_UNBIND_AGE_MIN_PACKETS, 1000) |
597 + FIELD_PREP(MTK_PPE_UNBIND_AGE_DELTA, 3);
598 + ppe_w32(ppe, MTK_PPE_UNBIND_AGE, val);
599 +
600 + val = FIELD_PREP(MTK_PPE_BIND_AGE0_DELTA_UDP, 12) |
601 + FIELD_PREP(MTK_PPE_BIND_AGE0_DELTA_NON_L4, 1);
602 + ppe_w32(ppe, MTK_PPE_BIND_AGE0, val);
603 +
604 + val = FIELD_PREP(MTK_PPE_BIND_AGE1_DELTA_TCP_FIN, 1) |
605 + FIELD_PREP(MTK_PPE_BIND_AGE1_DELTA_TCP, 7);
606 + ppe_w32(ppe, MTK_PPE_BIND_AGE1, val);
607 +
608 + val = MTK_PPE_BIND_LIMIT0_QUARTER | MTK_PPE_BIND_LIMIT0_HALF;
609 + ppe_w32(ppe, MTK_PPE_BIND_LIMIT0, val);
610 +
611 + val = MTK_PPE_BIND_LIMIT1_FULL |
612 + FIELD_PREP(MTK_PPE_BIND_LIMIT1_NON_L4, 1);
613 + ppe_w32(ppe, MTK_PPE_BIND_LIMIT1, val);
614 +
615 + val = FIELD_PREP(MTK_PPE_BIND_RATE_BIND, 30) |
616 + FIELD_PREP(MTK_PPE_BIND_RATE_PREBIND, 1);
617 + ppe_w32(ppe, MTK_PPE_BIND_RATE, val);
618 +
619 + /* enable PPE */
620 + val = MTK_PPE_GLO_CFG_EN |
621 + MTK_PPE_GLO_CFG_IP4_L4_CS_DROP |
622 + MTK_PPE_GLO_CFG_IP4_CS_DROP |
623 + MTK_PPE_GLO_CFG_FLOW_DROP_UPDATE;
624 + ppe_w32(ppe, MTK_PPE_GLO_CFG, val);
625 +
626 + ppe_w32(ppe, MTK_PPE_DEFAULT_CPU_PORT, 0);
627 +
628 + return 0;
629 +}
630 +
631 +int mtk_ppe_stop(struct mtk_ppe *ppe)
632 +{
633 + u32 val;
634 + int i;
635 +
636 + for (i = 0; i < MTK_PPE_ENTRIES; i++)
637 + ppe->foe_table[i].ib1 = FIELD_PREP(MTK_FOE_IB1_STATE,
638 + MTK_FOE_STATE_INVALID);
639 +
640 + mtk_ppe_cache_enable(ppe, false);
641 +
642 + /* disable offload engine */
643 + ppe_clear(ppe, MTK_PPE_GLO_CFG, MTK_PPE_GLO_CFG_EN);
644 + ppe_w32(ppe, MTK_PPE_FLOW_CFG, 0);
645 +
646 + /* disable aging */
647 + val = MTK_PPE_TB_CFG_AGE_NON_L4 |
648 + MTK_PPE_TB_CFG_AGE_UNBIND |
649 + MTK_PPE_TB_CFG_AGE_TCP |
650 + MTK_PPE_TB_CFG_AGE_UDP |
651 + MTK_PPE_TB_CFG_AGE_TCP_FIN;
652 + ppe_clear(ppe, MTK_PPE_TB_CFG, val);
653 +
654 + return mtk_ppe_wait_busy(ppe);
655 +}
656 --- /dev/null
657 +++ b/drivers/net/ethernet/mediatek/mtk_ppe.h
658 @@ -0,0 +1,287 @@
659 +// SPDX-License-Identifier: GPL-2.0-only
660 +/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */
661 +
662 +#ifndef __MTK_PPE_H
663 +#define __MTK_PPE_H
664 +
665 +#include <linux/kernel.h>
666 +#include <linux/bitfield.h>
667 +
668 +#define MTK_ETH_PPE_BASE 0xc00
669 +
670 +#define MTK_PPE_ENTRIES_SHIFT 3
671 +#define MTK_PPE_ENTRIES (1024 << MTK_PPE_ENTRIES_SHIFT)
672 +#define MTK_PPE_HASH_MASK (MTK_PPE_ENTRIES - 1)
673 +
674 +#define MTK_FOE_IB1_UNBIND_TIMESTAMP GENMASK(7, 0)
675 +#define MTK_FOE_IB1_UNBIND_PACKETS GENMASK(23, 8)
676 +#define MTK_FOE_IB1_UNBIND_PREBIND BIT(24)
677 +
678 +#define MTK_FOE_IB1_BIND_TIMESTAMP GENMASK(14, 0)
679 +#define MTK_FOE_IB1_BIND_KEEPALIVE BIT(15)
680 +#define MTK_FOE_IB1_BIND_VLAN_LAYER GENMASK(18, 16)
681 +#define MTK_FOE_IB1_BIND_PPPOE BIT(19)
682 +#define MTK_FOE_IB1_BIND_VLAN_TAG BIT(20)
683 +#define MTK_FOE_IB1_BIND_PKT_SAMPLE BIT(21)
684 +#define MTK_FOE_IB1_BIND_CACHE BIT(22)
685 +#define MTK_FOE_IB1_BIND_TUNNEL_DECAP BIT(23)
686 +#define MTK_FOE_IB1_BIND_TTL BIT(24)
687 +
688 +#define MTK_FOE_IB1_PACKET_TYPE GENMASK(27, 25)
689 +#define MTK_FOE_IB1_STATE GENMASK(29, 28)
690 +#define MTK_FOE_IB1_UDP BIT(30)
691 +#define MTK_FOE_IB1_STATIC BIT(31)
692 +
693 +enum {
694 + MTK_PPE_PKT_TYPE_IPV4_HNAPT = 0,
695 + MTK_PPE_PKT_TYPE_IPV4_ROUTE = 1,
696 + MTK_PPE_PKT_TYPE_BRIDGE = 2,
697 + MTK_PPE_PKT_TYPE_IPV4_DSLITE = 3,
698 + MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T = 4,
699 + MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T = 5,
700 + MTK_PPE_PKT_TYPE_IPV6_6RD = 7,
701 +};
702 +
703 +#define MTK_FOE_IB2_QID GENMASK(3, 0)
704 +#define MTK_FOE_IB2_PSE_QOS BIT(4)
705 +#define MTK_FOE_IB2_DEST_PORT GENMASK(7, 5)
706 +#define MTK_FOE_IB2_MULTICAST BIT(8)
707 +
708 +#define MTK_FOE_IB2_WHNAT_QID2 GENMASK(13, 12)
709 +#define MTK_FOE_IB2_WHNAT_DEVIDX BIT(16)
710 +#define MTK_FOE_IB2_WHNAT_NAT BIT(17)
711 +
712 +#define MTK_FOE_IB2_PORT_MG GENMASK(17, 12)
713 +
714 +#define MTK_FOE_IB2_PORT_AG GENMASK(23, 18)
715 +
716 +#define MTK_FOE_IB2_DSCP GENMASK(31, 24)
717 +
718 +#define MTK_FOE_VLAN2_WHNAT_BSS GEMMASK(5, 0)
719 +#define MTK_FOE_VLAN2_WHNAT_WCID GENMASK(13, 6)
720 +#define MTK_FOE_VLAN2_WHNAT_RING GENMASK(15, 14)
721 +
722 +enum {
723 + MTK_FOE_STATE_INVALID,
724 + MTK_FOE_STATE_UNBIND,
725 + MTK_FOE_STATE_BIND,
726 + MTK_FOE_STATE_FIN
727 +};
728 +
729 +struct mtk_foe_mac_info {
730 + u16 vlan1;
731 + u16 etype;
732 +
733 + u32 dest_mac_hi;
734 +
735 + u16 vlan2;
736 + u16 dest_mac_lo;
737 +
738 + u32 src_mac_hi;
739 +
740 + u16 pppoe_id;
741 + u16 src_mac_lo;
742 +};
743 +
744 +struct mtk_foe_bridge {
745 + u32 dest_mac_hi;
746 +
747 + u16 src_mac_lo;
748 + u16 dest_mac_lo;
749 +
750 + u32 src_mac_hi;
751 +
752 + u32 ib2;
753 +
754 + u32 _rsv[5];
755 +
756 + u32 udf_tsid;
757 + struct mtk_foe_mac_info l2;
758 +};
759 +
760 +struct mtk_ipv4_tuple {
761 + u32 src_ip;
762 + u32 dest_ip;
763 + union {
764 + struct {
765 + u16 dest_port;
766 + u16 src_port;
767 + };
768 + struct {
769 + u8 protocol;
770 + u8 _pad[3]; /* fill with 0xa5a5a5 */
771 + };
772 + u32 ports;
773 + };
774 +};
775 +
776 +struct mtk_foe_ipv4 {
777 + struct mtk_ipv4_tuple orig;
778 +
779 + u32 ib2;
780 +
781 + struct mtk_ipv4_tuple new;
782 +
783 + u16 timestamp;
784 + u16 _rsv0[3];
785 +
786 + u32 udf_tsid;
787 +
788 + struct mtk_foe_mac_info l2;
789 +};
790 +
791 +struct mtk_foe_ipv4_dslite {
792 + struct mtk_ipv4_tuple ip4;
793 +
794 + u32 tunnel_src_ip[4];
795 + u32 tunnel_dest_ip[4];
796 +
797 + u8 flow_label[3];
798 + u8 priority;
799 +
800 + u32 udf_tsid;
801 +
802 + u32 ib2;
803 +
804 + struct mtk_foe_mac_info l2;
805 +};
806 +
807 +struct mtk_foe_ipv6 {
808 + u32 src_ip[4];
809 + u32 dest_ip[4];
810 +
811 + union {
812 + struct {
813 + u8 protocol;
814 + u8 _pad[3]; /* fill with 0xa5a5a5 */
815 + }; /* 3-tuple */
816 + struct {
817 + u16 dest_port;
818 + u16 src_port;
819 + }; /* 5-tuple */
820 + u32 ports;
821 + };
822 +
823 + u32 _rsv[3];
824 +
825 + u32 udf;
826 +
827 + u32 ib2;
828 + struct mtk_foe_mac_info l2;
829 +};
830 +
831 +struct mtk_foe_ipv6_6rd {
832 + u32 src_ip[4];
833 + u32 dest_ip[4];
834 + u16 dest_port;
835 + u16 src_port;
836 +
837 + u32 tunnel_src_ip;
838 + u32 tunnel_dest_ip;
839 +
840 + u16 hdr_csum;
841 + u8 dscp;
842 + u8 ttl;
843 +
844 + u8 flag;
845 + u8 pad;
846 + u8 per_flow_6rd_id;
847 + u8 pad2;
848 +
849 + u32 ib2;
850 + struct mtk_foe_mac_info l2;
851 +};
852 +
853 +struct mtk_foe_entry {
854 + u32 ib1;
855 +
856 + union {
857 + struct mtk_foe_bridge bridge;
858 + struct mtk_foe_ipv4 ipv4;
859 + struct mtk_foe_ipv4_dslite dslite;
860 + struct mtk_foe_ipv6 ipv6;
861 + struct mtk_foe_ipv6_6rd ipv6_6rd;
862 + u32 data[19];
863 + };
864 +};
865 +
866 +enum {
867 + MTK_PPE_CPU_REASON_TTL_EXCEEDED = 0x02,
868 + MTK_PPE_CPU_REASON_OPTION_HEADER = 0x03,
869 + MTK_PPE_CPU_REASON_NO_FLOW = 0x07,
870 + MTK_PPE_CPU_REASON_IPV4_FRAG = 0x08,
871 + MTK_PPE_CPU_REASON_IPV4_DSLITE_FRAG = 0x09,
872 + MTK_PPE_CPU_REASON_IPV4_DSLITE_NO_TCP_UDP = 0x0a,
873 + MTK_PPE_CPU_REASON_IPV6_6RD_NO_TCP_UDP = 0x0b,
874 + MTK_PPE_CPU_REASON_TCP_FIN_SYN_RST = 0x0c,
875 + MTK_PPE_CPU_REASON_UN_HIT = 0x0d,
876 + MTK_PPE_CPU_REASON_HIT_UNBIND = 0x0e,
877 + MTK_PPE_CPU_REASON_HIT_UNBIND_RATE_REACHED = 0x0f,
878 + MTK_PPE_CPU_REASON_HIT_BIND_TCP_FIN = 0x10,
879 + MTK_PPE_CPU_REASON_HIT_TTL_1 = 0x11,
880 + MTK_PPE_CPU_REASON_HIT_BIND_VLAN_VIOLATION = 0x12,
881 + MTK_PPE_CPU_REASON_KEEPALIVE_UC_OLD_HDR = 0x13,
882 + MTK_PPE_CPU_REASON_KEEPALIVE_MC_NEW_HDR = 0x14,
883 + MTK_PPE_CPU_REASON_KEEPALIVE_DUP_OLD_HDR = 0x15,
884 + MTK_PPE_CPU_REASON_HIT_BIND_FORCE_CPU = 0x16,
885 + MTK_PPE_CPU_REASON_TUNNEL_OPTION_HEADER = 0x17,
886 + MTK_PPE_CPU_REASON_MULTICAST_TO_CPU = 0x18,
887 + MTK_PPE_CPU_REASON_MULTICAST_TO_GMAC1_CPU = 0x19,
888 + MTK_PPE_CPU_REASON_HIT_PRE_BIND = 0x1a,
889 + MTK_PPE_CPU_REASON_PACKET_SAMPLING = 0x1b,
890 + MTK_PPE_CPU_REASON_EXCEED_MTU = 0x1c,
891 + MTK_PPE_CPU_REASON_PPE_BYPASS = 0x1e,
892 + MTK_PPE_CPU_REASON_INVALID = 0x1f,
893 +};
894 +
895 +struct mtk_ppe {
896 + struct device *dev;
897 + void __iomem *base;
898 + int version;
899 +
900 + struct mtk_foe_entry *foe_table;
901 + dma_addr_t foe_phys;
902 +
903 + void *acct_table;
904 +};
905 +
906 +int mtk_ppe_init(struct mtk_ppe *ppe, struct device *dev, void __iomem *base,
907 + int version);
908 +int mtk_ppe_start(struct mtk_ppe *ppe);
909 +int mtk_ppe_stop(struct mtk_ppe *ppe);
910 +
911 +static inline void
912 +mtk_foe_entry_clear(struct mtk_ppe *ppe, u16 hash)
913 +{
914 + ppe->foe_table[hash].ib1 = 0;
915 + dma_wmb();
916 +}
917 +
918 +static inline int
919 +mtk_foe_entry_timestamp(struct mtk_ppe *ppe, u16 hash)
920 +{
921 + u32 ib1 = READ_ONCE(ppe->foe_table[hash].ib1);
922 +
923 + if (FIELD_GET(MTK_FOE_IB1_STATE, ib1) != MTK_FOE_STATE_BIND)
924 + return -1;
925 +
926 + return FIELD_GET(MTK_FOE_IB1_BIND_TIMESTAMP, ib1);
927 +}
928 +
929 +int mtk_foe_entry_prepare(struct mtk_foe_entry *entry, int type, int l4proto,
930 + u8 pse_port, u8 *src_mac, u8 *dest_mac);
931 +int mtk_foe_entry_set_pse_port(struct mtk_foe_entry *entry, u8 port);
932 +int mtk_foe_entry_set_ipv4_tuple(struct mtk_foe_entry *entry, bool orig,
933 + __be32 src_addr, __be16 src_port,
934 + __be32 dest_addr, __be16 dest_port);
935 +int mtk_foe_entry_set_ipv6_tuple(struct mtk_foe_entry *entry,
936 + __be32 *src_addr, __be16 src_port,
937 + __be32 *dest_addr, __be16 dest_port);
938 +int mtk_foe_entry_set_dsa(struct mtk_foe_entry *entry, int port);
939 +int mtk_foe_entry_set_vlan(struct mtk_foe_entry *entry, int vid);
940 +int mtk_foe_entry_set_pppoe(struct mtk_foe_entry *entry, int sid);
941 +int mtk_foe_entry_commit(struct mtk_ppe *ppe, struct mtk_foe_entry *entry,
942 + u16 timestamp);
943 +int mtk_ppe_debugfs_init(struct mtk_ppe *ppe);
944 +
945 +#endif
946 --- /dev/null
947 +++ b/drivers/net/ethernet/mediatek/mtk_ppe_debugfs.c
948 @@ -0,0 +1,217 @@
949 +// SPDX-License-Identifier: GPL-2.0-only
950 +/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */
951 +
952 +#include <linux/kernel.h>
953 +#include <linux/debugfs.h>
954 +#include "mtk_eth_soc.h"
955 +
956 +struct mtk_flow_addr_info
957 +{
958 + void *src, *dest;
959 + u16 *src_port, *dest_port;
960 + bool ipv6;
961 +};
962 +
963 +static const char *mtk_foe_entry_state_str(int state)
964 +{
965 + static const char * const state_str[] = {
966 + [MTK_FOE_STATE_INVALID] = "INV",
967 + [MTK_FOE_STATE_UNBIND] = "UNB",
968 + [MTK_FOE_STATE_BIND] = "BND",
969 + [MTK_FOE_STATE_FIN] = "FIN",
970 + };
971 +
972 + if (state >= ARRAY_SIZE(state_str) || !state_str[state])
973 + return "UNK";
974 +
975 + return state_str[state];
976 +}
977 +
978 +static const char *mtk_foe_pkt_type_str(int type)
979 +{
980 + static const char * const type_str[] = {
981 + [MTK_PPE_PKT_TYPE_IPV4_HNAPT] = "IPv4 5T",
982 + [MTK_PPE_PKT_TYPE_IPV4_ROUTE] = "IPv4 3T",
983 + [MTK_PPE_PKT_TYPE_BRIDGE] = "L2",
984 + [MTK_PPE_PKT_TYPE_IPV4_DSLITE] = "DS-LITE",
985 + [MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T] = "IPv6 3T",
986 + [MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T] = "IPv6 5T",
987 + [MTK_PPE_PKT_TYPE_IPV6_6RD] = "6RD",
988 + };
989 +
990 + if (type >= ARRAY_SIZE(type_str) || !type_str[type])
991 + return "UNKNOWN";
992 +
993 + return type_str[type];
994 +}
995 +
996 +static void
997 +mtk_print_addr(struct seq_file *m, u32 *addr, bool ipv6)
998 +{
999 + u32 n_addr[4];
1000 + int i;
1001 +
1002 + if (!ipv6) {
1003 + seq_printf(m, "%pI4h", addr);
1004 + return;
1005 + }
1006 +
1007 + for (i = 0; i < ARRAY_SIZE(n_addr); i++)
1008 + n_addr[i] = htonl(addr[i]);
1009 + seq_printf(m, "%pI6", n_addr);
1010 +}
1011 +
1012 +static void
1013 +mtk_print_addr_info(struct seq_file *m, struct mtk_flow_addr_info *ai)
1014 +{
1015 + mtk_print_addr(m, ai->src, ai->ipv6);
1016 + if (ai->src_port)
1017 + seq_printf(m, ":%d", *ai->src_port);
1018 + seq_printf(m, "->");
1019 + mtk_print_addr(m, ai->dest, ai->ipv6);
1020 + if (ai->dest_port)
1021 + seq_printf(m, ":%d", *ai->dest_port);
1022 +}
1023 +
1024 +static int
1025 +mtk_ppe_debugfs_foe_show(struct seq_file *m, void *private, bool bind)
1026 +{
1027 + struct mtk_ppe *ppe = m->private;
1028 + int i, count;
1029 +
1030 + for (i = 0, count = 0; i < MTK_PPE_ENTRIES; i++) {
1031 + struct mtk_foe_entry *entry = &ppe->foe_table[i];
1032 + struct mtk_foe_mac_info *l2;
1033 + struct mtk_flow_addr_info ai = {};
1034 + unsigned char h_source[ETH_ALEN];
1035 + unsigned char h_dest[ETH_ALEN];
1036 + int type, state;
1037 + u32 ib2;
1038 +
1039 +
1040 + state = FIELD_GET(MTK_FOE_IB1_STATE, entry->ib1);
1041 + if (!state)
1042 + continue;
1043 +
1044 + if (bind && state != MTK_FOE_STATE_BIND)
1045 + continue;
1046 +
1047 + type = FIELD_GET(MTK_FOE_IB1_PACKET_TYPE, entry->ib1);
1048 + seq_printf(m, "%05x %s %7s", i,
1049 + mtk_foe_entry_state_str(state),
1050 + mtk_foe_pkt_type_str(type));
1051 +
1052 + switch (type) {
1053 + case MTK_PPE_PKT_TYPE_IPV4_HNAPT:
1054 + case MTK_PPE_PKT_TYPE_IPV4_DSLITE:
1055 + ai.src_port = &entry->ipv4.orig.src_port;
1056 + ai.dest_port = &entry->ipv4.orig.dest_port;
1057 + fallthrough;
1058 + case MTK_PPE_PKT_TYPE_IPV4_ROUTE:
1059 + ai.src = &entry->ipv4.orig.src_ip;
1060 + ai.dest = &entry->ipv4.orig.dest_ip;
1061 + break;
1062 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_5T:
1063 + ai.src_port = &entry->ipv6.src_port;
1064 + ai.dest_port = &entry->ipv6.dest_port;
1065 + fallthrough;
1066 + case MTK_PPE_PKT_TYPE_IPV6_ROUTE_3T:
1067 + case MTK_PPE_PKT_TYPE_IPV6_6RD:
1068 + ai.src = &entry->ipv6.src_ip;
1069 + ai.dest = &entry->ipv6.dest_ip;
1070 + ai.ipv6 = true;
1071 + break;
1072 + }
1073 +
1074 + seq_printf(m, " orig=");
1075 + mtk_print_addr_info(m, &ai);
1076 +
1077 + switch (type) {
1078 + case MTK_PPE_PKT_TYPE_IPV4_HNAPT:
1079 + case MTK_PPE_PKT_TYPE_IPV4_DSLITE:
1080 + ai.src_port = &entry->ipv4.new.src_port;
1081 + ai.dest_port = &entry->ipv4.new.dest_port;
1082 + fallthrough;
1083 + case MTK_PPE_PKT_TYPE_IPV4_ROUTE:
1084 + ai.src = &entry->ipv4.new.src_ip;
1085 + ai.dest = &entry->ipv4.new.dest_ip;
1086 + seq_printf(m, " new=");
1087 + mtk_print_addr_info(m, &ai);
1088 + break;
1089 + }
1090 +
1091 + if (type >= MTK_PPE_PKT_TYPE_IPV4_DSLITE) {
1092 + l2 = &entry->ipv6.l2;
1093 + ib2 = entry->ipv6.ib2;
1094 + } else {
1095 + l2 = &entry->ipv4.l2;
1096 + ib2 = entry->ipv4.ib2;
1097 + }
1098 +
1099 + *((__be32 *)h_source) = htonl(l2->src_mac_hi);
1100 + *((__be16 *)&h_source[4]) = htons(l2->src_mac_lo);
1101 + *((__be32 *)h_dest) = htonl(l2->dest_mac_hi);
1102 + *((__be16 *)&h_dest[4]) = htons(l2->dest_mac_lo);
1103 +
1104 + seq_printf(m, " eth=%pM->%pM etype=%04x"
1105 + " vlan=%d,%d ib1=%08x ib2=%08x\n",
1106 + h_source, h_dest, ntohs(l2->etype),
1107 + l2->vlan1, l2->vlan2, entry->ib1, ib2);
1108 + }
1109 +
1110 + return 0;
1111 +}
1112 +
1113 +static int
1114 +mtk_ppe_debugfs_foe_show_all(struct seq_file *m, void *private)
1115 +{
1116 + return mtk_ppe_debugfs_foe_show(m, private, false);
1117 +}
1118 +
1119 +static int
1120 +mtk_ppe_debugfs_foe_show_bind(struct seq_file *m, void *private)
1121 +{
1122 + return mtk_ppe_debugfs_foe_show(m, private, true);
1123 +}
1124 +
1125 +static int
1126 +mtk_ppe_debugfs_foe_open_all(struct inode *inode, struct file *file)
1127 +{
1128 + return single_open(file, mtk_ppe_debugfs_foe_show_all,
1129 + inode->i_private);
1130 +}
1131 +
1132 +static int
1133 +mtk_ppe_debugfs_foe_open_bind(struct inode *inode, struct file *file)
1134 +{
1135 + return single_open(file, mtk_ppe_debugfs_foe_show_bind,
1136 + inode->i_private);
1137 +}
1138 +
1139 +int mtk_ppe_debugfs_init(struct mtk_ppe *ppe)
1140 +{
1141 + static const struct file_operations fops_all = {
1142 + .open = mtk_ppe_debugfs_foe_open_all,
1143 + .read = seq_read,
1144 + .llseek = seq_lseek,
1145 + .release = single_release,
1146 + };
1147 +
1148 + static const struct file_operations fops_bind = {
1149 + .open = mtk_ppe_debugfs_foe_open_bind,
1150 + .read = seq_read,
1151 + .llseek = seq_lseek,
1152 + .release = single_release,
1153 + };
1154 +
1155 + struct dentry *root;
1156 +
1157 + root = debugfs_create_dir("mtk_ppe", NULL);
1158 + if (!root)
1159 + return -ENOMEM;
1160 +
1161 + debugfs_create_file("entries", S_IRUGO, root, ppe, &fops_all);
1162 + debugfs_create_file("bind", S_IRUGO, root, ppe, &fops_bind);
1163 +
1164 + return 0;
1165 +}
1166 --- /dev/null
1167 +++ b/drivers/net/ethernet/mediatek/mtk_ppe_regs.h
1168 @@ -0,0 +1,144 @@
1169 +// SPDX-License-Identifier: GPL-2.0-only
1170 +/* Copyright (C) 2020 Felix Fietkau <nbd@nbd.name> */
1171 +
1172 +#ifndef __MTK_PPE_REGS_H
1173 +#define __MTK_PPE_REGS_H
1174 +
1175 +#define MTK_PPE_GLO_CFG 0x200
1176 +#define MTK_PPE_GLO_CFG_EN BIT(0)
1177 +#define MTK_PPE_GLO_CFG_TSID_EN BIT(1)
1178 +#define MTK_PPE_GLO_CFG_IP4_L4_CS_DROP BIT(2)
1179 +#define MTK_PPE_GLO_CFG_IP4_CS_DROP BIT(3)
1180 +#define MTK_PPE_GLO_CFG_TTL0_DROP BIT(4)
1181 +#define MTK_PPE_GLO_CFG_PPE_BSWAP BIT(5)
1182 +#define MTK_PPE_GLO_CFG_PSE_HASH_OFS BIT(6)
1183 +#define MTK_PPE_GLO_CFG_MCAST_TB_EN BIT(7)
1184 +#define MTK_PPE_GLO_CFG_FLOW_DROP_KA BIT(8)
1185 +#define MTK_PPE_GLO_CFG_FLOW_DROP_UPDATE BIT(9)
1186 +#define MTK_PPE_GLO_CFG_UDP_LITE_EN BIT(10)
1187 +#define MTK_PPE_GLO_CFG_UDP_LEN_DROP BIT(11)
1188 +#define MTK_PPE_GLO_CFG_MCAST_ENTRIES GNEMASK(13, 12)
1189 +#define MTK_PPE_GLO_CFG_BUSY BIT(31)
1190 +
1191 +#define MTK_PPE_FLOW_CFG 0x204
1192 +#define MTK_PPE_FLOW_CFG_IP4_TCP_FRAG BIT(6)
1193 +#define MTK_PPE_FLOW_CFG_IP4_UDP_FRAG BIT(7)
1194 +#define MTK_PPE_FLOW_CFG_IP6_3T_ROUTE BIT(8)
1195 +#define MTK_PPE_FLOW_CFG_IP6_5T_ROUTE BIT(9)
1196 +#define MTK_PPE_FLOW_CFG_IP6_6RD BIT(10)
1197 +#define MTK_PPE_FLOW_CFG_IP4_NAT BIT(12)
1198 +#define MTK_PPE_FLOW_CFG_IP4_NAPT BIT(13)
1199 +#define MTK_PPE_FLOW_CFG_IP4_DSLITE BIT(14)
1200 +#define MTK_PPE_FLOW_CFG_L2_BRIDGE BIT(15)
1201 +#define MTK_PPE_FLOW_CFG_IP_PROTO_BLACKLIST BIT(16)
1202 +#define MTK_PPE_FLOW_CFG_IP4_NAT_FRAG BIT(17)
1203 +#define MTK_PPE_FLOW_CFG_IP4_HASH_FLOW_LABEL BIT(18)
1204 +#define MTK_PPE_FLOW_CFG_IP4_HASH_GRE_KEY BIT(19)
1205 +#define MTK_PPE_FLOW_CFG_IP6_HASH_GRE_KEY BIT(20)
1206 +
1207 +#define MTK_PPE_IP_PROTO_CHK 0x208
1208 +#define MTK_PPE_IP_PROTO_CHK_IPV4 GENMASK(15, 0)
1209 +#define MTK_PPE_IP_PROTO_CHK_IPV6 GENMASK(31, 16)
1210 +
1211 +#define MTK_PPE_TB_CFG 0x21c
1212 +#define MTK_PPE_TB_CFG_ENTRY_NUM GENMASK(2, 0)
1213 +#define MTK_PPE_TB_CFG_ENTRY_80B BIT(3)
1214 +#define MTK_PPE_TB_CFG_SEARCH_MISS GENMASK(5, 4)
1215 +#define MTK_PPE_TB_CFG_AGE_PREBIND BIT(6)
1216 +#define MTK_PPE_TB_CFG_AGE_NON_L4 BIT(7)
1217 +#define MTK_PPE_TB_CFG_AGE_UNBIND BIT(8)
1218 +#define MTK_PPE_TB_CFG_AGE_TCP BIT(9)
1219 +#define MTK_PPE_TB_CFG_AGE_UDP BIT(10)
1220 +#define MTK_PPE_TB_CFG_AGE_TCP_FIN BIT(11)
1221 +#define MTK_PPE_TB_CFG_KEEPALIVE GENMASK(13, 12)
1222 +#define MTK_PPE_TB_CFG_HASH_MODE GENMASK(15, 14)
1223 +#define MTK_PPE_TB_CFG_SCAN_MODE GENMASK(17, 16)
1224 +#define MTK_PPE_TB_CFG_HASH_DEBUG GENMASK(19, 18)
1225 +
1226 +enum {
1227 + MTK_PPE_SCAN_MODE_DISABLED,
1228 + MTK_PPE_SCAN_MODE_CHECK_AGE,
1229 + MTK_PPE_SCAN_MODE_KEEPALIVE_AGE,
1230 +};
1231 +
1232 +enum {
1233 + MTK_PPE_KEEPALIVE_DISABLE,
1234 + MTK_PPE_KEEPALIVE_UNICAST_CPU,
1235 + MTK_PPE_KEEPALIVE_DUP_CPU = 3,
1236 +};
1237 +
1238 +enum {
1239 + MTK_PPE_SEARCH_MISS_ACTION_DROP,
1240 + MTK_PPE_SEARCH_MISS_ACTION_FORWARD = 2,
1241 + MTK_PPE_SEARCH_MISS_ACTION_FORWARD_BUILD = 3,
1242 +};
1243 +
1244 +#define MTK_PPE_TB_BASE 0x220
1245 +
1246 +#define MTK_PPE_TB_USED 0x224
1247 +#define MTK_PPE_TB_USED_NUM GENMASK(13, 0)
1248 +
1249 +#define MTK_PPE_BIND_RATE 0x228
1250 +#define MTK_PPE_BIND_RATE_BIND GENMASK(15, 0)
1251 +#define MTK_PPE_BIND_RATE_PREBIND GENMASK(31, 16)
1252 +
1253 +#define MTK_PPE_BIND_LIMIT0 0x22c
1254 +#define MTK_PPE_BIND_LIMIT0_QUARTER GENMASK(13, 0)
1255 +#define MTK_PPE_BIND_LIMIT0_HALF GENMASK(29, 16)
1256 +
1257 +#define MTK_PPE_BIND_LIMIT1 0x230
1258 +#define MTK_PPE_BIND_LIMIT1_FULL GENMASK(13, 0)
1259 +#define MTK_PPE_BIND_LIMIT1_NON_L4 GENMASK(23, 16)
1260 +
1261 +#define MTK_PPE_KEEPALIVE 0x234
1262 +#define MTK_PPE_KEEPALIVE_TIME GENMASK(15, 0)
1263 +#define MTK_PPE_KEEPALIVE_TIME_TCP GENMASK(23, 16)
1264 +#define MTK_PPE_KEEPALIVE_TIME_UDP GENMASK(31, 24)
1265 +
1266 +#define MTK_PPE_UNBIND_AGE 0x238
1267 +#define MTK_PPE_UNBIND_AGE_MIN_PACKETS GENMASK(31, 16)
1268 +#define MTK_PPE_UNBIND_AGE_DELTA GENMASK(7, 0)
1269 +
1270 +#define MTK_PPE_BIND_AGE0 0x23c
1271 +#define MTK_PPE_BIND_AGE0_DELTA_NON_L4 GENMASK(30, 16)
1272 +#define MTK_PPE_BIND_AGE0_DELTA_UDP GENMASK(14, 0)
1273 +
1274 +#define MTK_PPE_BIND_AGE1 0x240
1275 +#define MTK_PPE_BIND_AGE1_DELTA_TCP_FIN GENMASK(30, 16)
1276 +#define MTK_PPE_BIND_AGE1_DELTA_TCP GENMASK(14, 0)
1277 +
1278 +#define MTK_PPE_HASH_SEED 0x244
1279 +
1280 +#define MTK_PPE_DEFAULT_CPU_PORT 0x248
1281 +#define MTK_PPE_DEFAULT_CPU_PORT_MASK(_n) (GENMASK(2, 0) << ((_n) * 4))
1282 +
1283 +#define MTK_PPE_MTU_DROP 0x308
1284 +
1285 +#define MTK_PPE_VLAN_MTU0 0x30c
1286 +#define MTK_PPE_VLAN_MTU0_NONE GENMASK(13, 0)
1287 +#define MTK_PPE_VLAN_MTU0_1TAG GENMASK(29, 16)
1288 +
1289 +#define MTK_PPE_VLAN_MTU1 0x310
1290 +#define MTK_PPE_VLAN_MTU1_2TAG GENMASK(13, 0)
1291 +#define MTK_PPE_VLAN_MTU1_3TAG GENMASK(29, 16)
1292 +
1293 +#define MTK_PPE_VPM_TPID 0x318
1294 +
1295 +#define MTK_PPE_CACHE_CTL 0x320
1296 +#define MTK_PPE_CACHE_CTL_EN BIT(0)
1297 +#define MTK_PPE_CACHE_CTL_LOCK_CLR BIT(4)
1298 +#define MTK_PPE_CACHE_CTL_REQ BIT(8)
1299 +#define MTK_PPE_CACHE_CTL_CLEAR BIT(9)
1300 +#define MTK_PPE_CACHE_CTL_CMD GENMASK(13, 12)
1301 +
1302 +#define MTK_PPE_MIB_CFG 0x334
1303 +#define MTK_PPE_MIB_CFG_EN BIT(0)
1304 +#define MTK_PPE_MIB_CFG_RD_CLR BIT(1)
1305 +
1306 +#define MTK_PPE_MIB_TB_BASE 0x338
1307 +
1308 +#define MTK_PPE_MIB_CACHE_CTL 0x350
1309 +#define MTK_PPE_MIB_CACHE_CTL_EN BIT(0)
1310 +#define MTK_PPE_MIB_CACHE_CTL_FLUSH BIT(2)
1311 +
1312 +#endif
Kevin D-Bs staging tree