target/linux/generic/backport-5.10/730-net-dsa-mt7530-setup-core-clock-even-in-TRGMII-mode.patch

   1 From c3b8e07909dbe67b0d580416c1a5257643a73be7 Mon Sep 17 00:00:00 2001
   2 From: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
   3 Date: Fri, 12 Mar 2021 00:07:03 -0800
   4 Subject: [PATCH] net: dsa: mt7530: setup core clock even in TRGMII mode
   5
   6 A recent change to MIPS ralink reset logic made it so mt7530 actually
   7 resets the switch on platforms such as mt7621 (where bit 2 is the reset
   8 line for the switch). That exposed an issue where the switch would not
   9 function properly in TRGMII mode after a reset.
  10
  11 Reconfigure core clock in TRGMII mode to fix the issue.
  12
  13 Tested on Ubiquiti ER-X (MT7621) with TRGMII mode enabled.
  14
  15 Fixes: 3f9ef7785a9c ("MIPS: ralink: manage low reset lines")
  16 Signed-off-by: Ilya Lipnitskiy <ilya.lipnitskiy@gmail.com>
  17 Signed-off-by: David S. Miller <davem@davemloft.net>
  18 ---
  19  drivers/net/dsa/mt7530.c | 52 +++++++++++++++++++---------------------
  20  1 file changed, 25 insertions(+), 27 deletions(-)
  21
  22 --- a/drivers/net/dsa/mt7530.c
  23 +++ b/drivers/net/dsa/mt7530.c
  24 @@ -436,34 +436,32 @@ mt7530_pad_clk_setup(struct dsa_switch *
  25                              TD_DM_DRVP(8) | TD_DM_DRVN(8));
  26
  27         /* Setup core clock for MT7530 */
  28 -       if (!trgint) {
  29 -               /* Disable MT7530 core clock */
  30 -               core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
  31 -
  32 -               /* Disable PLL, since phy_device has not yet been created
  33 -                * provided for phy_[read,write]_mmd_indirect is called, we
  34 -                * provide our own core_write_mmd_indirect to complete this
  35 -                * function.
  36 -                */
  37 -               core_write_mmd_indirect(priv,
  38 -                                       CORE_GSWPLL_GRP1,
  39 -                                       MDIO_MMD_VEND2,
  40 -                                       0);
  41 -
  42 -               /* Set core clock into 500Mhz */
  43 -               core_write(priv, CORE_GSWPLL_GRP2,
  44 -                          RG_GSWPLL_POSDIV_500M(1) |
  45 -                          RG_GSWPLL_FBKDIV_500M(25));
  46 -
  47 -               /* Enable PLL */
  48 -               core_write(priv, CORE_GSWPLL_GRP1,
  49 -                          RG_GSWPLL_EN_PRE |
  50 -                          RG_GSWPLL_POSDIV_200M(2) |
  51 -                          RG_GSWPLL_FBKDIV_200M(32));
  52 -
  53 -               /* Enable MT7530 core clock */
  54 -               core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
  55 -       }
  56 +       /* Disable MT7530 core clock */
  57 +       core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
  58 +
  59 +       /* Disable PLL, since phy_device has not yet been created
  60 +        * provided for phy_[read,write]_mmd_indirect is called, we
  61 +        * provide our own core_write_mmd_indirect to complete this
  62 +        * function.
  63 +        */
  64 +       core_write_mmd_indirect(priv,
  65 +                               CORE_GSWPLL_GRP1,
  66 +                               MDIO_MMD_VEND2,
  67 +                               0);
  68 +
  69 +       /* Set core clock into 500Mhz */
  70 +       core_write(priv, CORE_GSWPLL_GRP2,
  71 +                  RG_GSWPLL_POSDIV_500M(1) |
  72 +                  RG_GSWPLL_FBKDIV_500M(25));
  73 +
  74 +       /* Enable PLL */
  75 +       core_write(priv, CORE_GSWPLL_GRP1,
  76 +                  RG_GSWPLL_EN_PRE |
  77 +                  RG_GSWPLL_POSDIV_200M(2) |
  78 +                  RG_GSWPLL_FBKDIV_200M(32));
  79 +
  80 +       /* Enable MT7530 core clock */
  81 +       core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);
  82
  83         /* Setup the MT7530 TRGMII Tx Clock */
  84         core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN);