projects / openwrt / staging / ldir.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
ath25: switch default kernel to 5.15
[openwrt/staging/ldir.git] / target / linux / generic / backport-5.10 / 793-v5.13-r8152-support-new-chips.patch
1 From e7439e7fd384f55f55837f7e4866e74d8dca3827 Mon Sep 17 00:00:00 2001
2 From: Hayes Wang <hayeswang@realtek.com>
3 Date: Fri, 16 Apr 2021 16:04:35 +0800
4 Subject: [PATCH] r8152: support new chips
5
6 commit 195aae321c829dd1945900d75561e6aa79cce208 upstream.
7
8 Support RTL8153C, RTL8153D, RTL8156A, and RTL8156B. The RTL8156A
9 and RTL8156B are the 2.5G ethernet.
10
11 Signed-off-by: Hayes Wang <hayeswang@realtek.com>
12 Signed-off-by: David S. Miller <davem@davemloft.net>
13 ---
14 drivers/net/usb/r8152.c | 2634 +++++++++++++++++++++++++++++++++++----
15 1 file changed, 2359 insertions(+), 275 deletions(-)
16
17 --- a/drivers/net/usb/r8152.c
18 +++ b/drivers/net/usb/r8152.c
19 @@ -43,10 +43,14 @@
20
21 #define PLA_IDR 0xc000
22 #define PLA_RCR 0xc010
23 +#define PLA_RCR1 0xc012
24 #define PLA_RMS 0xc016
25 #define PLA_RXFIFO_CTRL0 0xc0a0
26 +#define PLA_RXFIFO_FULL 0xc0a2
27 #define PLA_RXFIFO_CTRL1 0xc0a4
28 +#define PLA_RX_FIFO_FULL 0xc0a6
29 #define PLA_RXFIFO_CTRL2 0xc0a8
30 +#define PLA_RX_FIFO_EMPTY 0xc0aa
31 #define PLA_DMY_REG0 0xc0b0
32 #define PLA_FMC 0xc0b4
33 #define PLA_CFG_WOL 0xc0b6
34 @@ -63,6 +67,8 @@
35 #define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */
36 #define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */
37 #define PLA_EXTRA_STATUS 0xd398
38 +#define PLA_GPHY_CTRL 0xd3ae
39 +#define PLA_POL_GPIO_CTRL 0xdc6a
40 #define PLA_EFUSE_DATA 0xdd00
41 #define PLA_EFUSE_CMD 0xdd02
42 #define PLA_LEDSEL 0xdd90
43 @@ -72,6 +78,8 @@
44 #define PLA_LWAKE_CTRL_REG 0xe007
45 #define PLA_GPHY_INTR_IMR 0xe022
46 #define PLA_EEE_CR 0xe040
47 +#define PLA_EEE_TXTWSYS 0xe04c
48 +#define PLA_EEE_TXTWSYS_2P5G 0xe058
49 #define PLA_EEEP_CR 0xe080
50 #define PLA_MAC_PWR_CTRL 0xe0c0
51 #define PLA_MAC_PWR_CTRL2 0xe0ca
52 @@ -82,6 +90,7 @@
53 #define PLA_TCR1 0xe612
54 #define PLA_MTPS 0xe615
55 #define PLA_TXFIFO_CTRL 0xe618
56 +#define PLA_TXFIFO_FULL 0xe61a
57 #define PLA_RSTTALLY 0xe800
58 #define PLA_CR 0xe813
59 #define PLA_CRWECR 0xe81c
60 @@ -98,6 +107,7 @@
61 #define PLA_SFF_STS_7 0xe8de
62 #define PLA_PHYSTATUS 0xe908
63 #define PLA_CONFIG6 0xe90a /* CONFIG6 */
64 +#define PLA_USB_CFG 0xe952
65 #define PLA_BP_BA 0xfc26
66 #define PLA_BP_0 0xfc28
67 #define PLA_BP_1 0xfc2a
68 @@ -112,6 +122,7 @@
69 #define USB_USB2PHY 0xb41e
70 #define USB_SSPHYLINK1 0xb426
71 #define USB_SSPHYLINK2 0xb428
72 +#define USB_L1_CTRL 0xb45e
73 #define USB_U2P3_CTRL 0xb460
74 #define USB_CSR_DUMMY1 0xb464
75 #define USB_CSR_DUMMY2 0xb466
76 @@ -122,7 +133,12 @@
77 #define USB_FW_FIX_EN0 0xcfca
78 #define USB_FW_FIX_EN1 0xcfcc
79 #define USB_LPM_CONFIG 0xcfd8
80 +#define USB_ECM_OPTION 0xcfee
81 #define USB_CSTMR 0xcfef /* RTL8153A */
82 +#define USB_MISC_2 0xcfff
83 +#define USB_ECM_OP 0xd26b
84 +#define USB_GPHY_CTRL 0xd284
85 +#define USB_SPEED_OPTION 0xd32a
86 #define USB_FW_CTRL 0xd334 /* RTL8153B */
87 #define USB_FC_TIMER 0xd340
88 #define USB_USB_CTRL 0xd406
89 @@ -136,16 +152,20 @@
90 #define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */
91 #define USB_TX_DMA 0xd434
92 #define USB_UPT_RXDMA_OWN 0xd437
93 +#define USB_UPHY3_MDCMDIO 0xd480
94 #define USB_TOLERANCE 0xd490
95 #define USB_LPM_CTRL 0xd41a
96 #define USB_BMU_RESET 0xd4b0
97 +#define USB_BMU_CONFIG 0xd4b4
98 #define USB_U1U2_TIMER 0xd4da
99 #define USB_FW_TASK 0xd4e8 /* RTL8153B */
100 +#define USB_RX_AGGR_NUM 0xd4ee
101 #define USB_UPS_CTRL 0xd800
102 #define USB_POWER_CUT 0xd80a
103 #define USB_MISC_0 0xd81a
104 #define USB_MISC_1 0xd81f
105 #define USB_AFE_CTRL2 0xd824
106 +#define USB_UPHY_XTAL 0xd826
107 #define USB_UPS_CFG 0xd842
108 #define USB_UPS_FLAGS 0xd848
109 #define USB_WDT1_CTRL 0xe404
110 @@ -188,6 +208,9 @@
111 #define OCP_EEE_ABLE 0xa5c4
112 #define OCP_EEE_ADV 0xa5d0
113 #define OCP_EEE_LPABLE 0xa5d2
114 +#define OCP_10GBT_CTRL 0xa5d4
115 +#define OCP_10GBT_STAT 0xa5d6
116 +#define OCP_EEE_ADV2 0xa6d4
117 #define OCP_PHY_STATE 0xa708 /* nway state for 8153 */
118 #define OCP_PHY_PATCH_STAT 0xb800
119 #define OCP_PHY_PATCH_CMD 0xb820
120 @@ -199,6 +222,7 @@
121 /* SRAM Register */
122 #define SRAM_GREEN_CFG 0x8011
123 #define SRAM_LPF_CFG 0x8012
124 +#define SRAM_GPHY_FW_VER 0x801e
125 #define SRAM_10M_AMP1 0x8080
126 #define SRAM_10M_AMP2 0x8082
127 #define SRAM_IMPEDANCE 0x8084
128 @@ -210,11 +234,19 @@
129 #define RCR_AM 0x00000004
130 #define RCR_AB 0x00000008
131 #define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB)
132 +#define SLOT_EN BIT(11)
133 +
134 +/* PLA_RCR1 */
135 +#define OUTER_VLAN BIT(7)
136 +#define INNER_VLAN BIT(6)
137
138 /* PLA_RXFIFO_CTRL0 */
139 #define RXFIFO_THR1_NORMAL 0x00080002
140 #define RXFIFO_THR1_OOB 0x01800003
141
142 +/* PLA_RXFIFO_FULL */
143 +#define RXFIFO_FULL_MASK 0xfff
144 +
145 /* PLA_RXFIFO_CTRL1 */
146 #define RXFIFO_THR2_FULL 0x00000060
147 #define RXFIFO_THR2_HIGH 0x00000038
148 @@ -285,6 +317,7 @@
149 #define MCU_BORW_EN 0x4000
150
151 /* PLA_CPCR */
152 +#define FLOW_CTRL_EN BIT(0)
153 #define CPCR_RX_VLAN 0x0040
154
155 /* PLA_CFG_WOL */
156 @@ -310,6 +343,10 @@
157 /* PLA_CONFIG6 */
158 #define LANWAKE_CLR_EN BIT(0)
159
160 +/* PLA_USB_CFG */
161 +#define EN_XG_LIP BIT(1)
162 +#define EN_G_LIP BIT(2)
163 +
164 /* PLA_CONFIG5 */
165 #define BWF_EN 0x0040
166 #define MWF_EN 0x0020
167 @@ -333,6 +370,7 @@
168 /* PLA_MAC_PWR_CTRL2 */
169 #define EEE_SPDWN_RATIO 0x8007
170 #define MAC_CLK_SPDWN_EN BIT(15)
171 +#define EEE_SPDWN_RATIO_MASK 0xff
172
173 /* PLA_MAC_PWR_CTRL3 */
174 #define PLA_MCU_SPDWN_EN BIT(14)
175 @@ -345,6 +383,7 @@
176 #define PWRSAVE_SPDWN_EN 0x1000
177 #define RXDV_SPDWN_EN 0x0800
178 #define TX10MIDLE_EN 0x0100
179 +#define IDLE_SPDWN_EN BIT(6)
180 #define TP100_SPDWN_EN 0x0020
181 #define TP500_SPDWN_EN 0x0010
182 #define TP1000_SPDWN_EN 0x0008
183 @@ -385,6 +424,13 @@
184 #define LINK_CHANGE_FLAG BIT(8)
185 #define POLL_LINK_CHG BIT(0)
186
187 +/* PLA_GPHY_CTRL */
188 +#define GPHY_FLASH BIT(1)
189 +
190 +/* PLA_POL_GPIO_CTRL */
191 +#define DACK_DET_EN BIT(15)
192 +#define POL_GPHY_PATCH BIT(4)
193 +
194 /* USB_USB2PHY */
195 #define USB2PHY_SUSPEND 0x0001
196 #define USB2PHY_L1 0x0002
197 @@ -433,6 +479,9 @@
198 #define BMU_RESET_EP_IN 0x01
199 #define BMU_RESET_EP_OUT 0x02
200
201 +/* USB_BMU_CONFIG */
202 +#define ACT_ODMA BIT(1)
203 +
204 /* USB_UPT_RXDMA_OWN */
205 #define OWN_UPDATE BIT(0)
206 #define OWN_CLEAR BIT(1)
207 @@ -440,27 +489,52 @@
208 /* USB_FW_TASK */
209 #define FC_PATCH_TASK BIT(1)
210
211 +/* USB_RX_AGGR_NUM */
212 +#define RX_AGGR_NUM_MASK 0x1ff
213 +
214 /* USB_UPS_CTRL */
215 #define POWER_CUT 0x0100
216
217 /* USB_PM_CTRL_STATUS */
218 #define RESUME_INDICATE 0x0001
219
220 +/* USB_ECM_OPTION */
221 +#define BYPASS_MAC_RESET BIT(5)
222 +
223 /* USB_CSTMR */
224 #define FORCE_SUPER BIT(0)
225
226 +/* USB_MISC_2 */
227 +#define UPS_FORCE_PWR_DOWN BIT(0)
228 +
229 +/* USB_ECM_OP */
230 +#define EN_ALL_SPEED BIT(0)
231 +
232 +/* USB_GPHY_CTRL */
233 +#define GPHY_PATCH_DONE BIT(2)
234 +#define BYPASS_FLASH BIT(5)
235 +#define BACKUP_RESTRORE BIT(6)
236 +
237 +/* USB_SPEED_OPTION */
238 +#define RG_PWRDN_EN BIT(8)
239 +#define ALL_SPEED_OFF BIT(9)
240 +
241 /* USB_FW_CTRL */
242 #define FLOW_CTRL_PATCH_OPT BIT(1)
243 +#define AUTO_SPEEDUP BIT(3)
244 +#define FLOW_CTRL_PATCH_2 BIT(8)
245
246 /* USB_FC_TIMER */
247 #define CTRL_TIMER_EN BIT(15)
248
249 /* USB_USB_CTRL */
250 +#define CDC_ECM_EN BIT(3)
251 #define RX_AGG_DISABLE 0x0010
252 #define RX_ZERO_EN 0x0080
253
254 /* USB_U2P3_CTRL */
255 #define U2P3_ENABLE 0x0001
256 +#define RX_DETECT8 BIT(3)
257
258 /* USB_POWER_CUT */
259 #define PWR_EN 0x0001
260 @@ -496,8 +570,12 @@
261 #define SEN_VAL_NORMAL 0xa000
262 #define SEL_RXIDLE 0x0100
263
264 +/* USB_UPHY_XTAL */
265 +#define OOBS_POLLING BIT(8)
266 +
267 /* USB_UPS_CFG */
268 #define SAW_CNT_1MS_MASK 0x0fff
269 +#define MID_REVERSE BIT(5) /* RTL8156A */
270
271 /* USB_UPS_FLAGS */
272 #define UPS_FLAGS_R_TUNE BIT(0)
273 @@ -505,6 +583,7 @@
274 #define UPS_FLAGS_250M_CKDIV BIT(2)
275 #define UPS_FLAGS_EN_ALDPS BIT(3)
276 #define UPS_FLAGS_CTAP_SHORT_DIS BIT(4)
277 +#define UPS_FLAGS_SPEED_MASK (0xf << 16)
278 #define ups_flags_speed(x) ((x) << 16)
279 #define UPS_FLAGS_EN_EEE BIT(20)
280 #define UPS_FLAGS_EN_500M_EEE BIT(21)
281 @@ -525,6 +604,8 @@ enum spd_duplex {
282 FORCE_10M_FULL,
283 FORCE_100M_HALF,
284 FORCE_100M_FULL,
285 + FORCE_1000M_FULL,
286 + NWAY_2500M_FULL,
287 };
288
289 /* OCP_ALDPS_CONFIG */
290 @@ -589,6 +670,9 @@ enum spd_duplex {
291 #define EN_10M_CLKDIV BIT(11)
292 #define EN_10M_BGOFF 0x0080
293
294 +/* OCP_10GBT_CTRL */
295 +#define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */
296 +
297 /* OCP_PHY_STATE */
298 #define TXDIS_STATE 0x01
299 #define ABD_STATE 0x02
300 @@ -608,7 +692,8 @@ enum spd_duplex {
301 #define EN_EMI_L 0x0040
302
303 /* OCP_SYSCLK_CFG */
304 -#define clk_div_expo(x) (min(x, 5) << 8)
305 +#define sysclk_div_expo(x) (min(x, 5) << 8)
306 +#define clk_div_expo(x) (min(x, 5) << 4)
307
308 /* SRAM_GREEN_CFG */
309 #define GREEN_ETH_EN BIT(15)
310 @@ -639,6 +724,11 @@ enum spd_duplex {
311 #define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */
312
313 enum rtl_register_content {
314 + _2500bps = BIT(10),
315 + _1250bps = BIT(9),
316 + _500bps = BIT(8),
317 + _tx_flow = BIT(6),
318 + _rx_flow = BIT(5),
319 _1000bps = 0x10,
320 _100bps = 0x08,
321 _10bps = 0x04,
322 @@ -646,6 +736,9 @@ enum rtl_register_content {
323 FULL_DUP = 0x01,
324 };
325
326 +#define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS))
327 +#define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow))
328 +
329 #define RTL8152_MAX_TX 4
330 #define RTL8152_MAX_RX 10
331 #define INTBUFSIZE 2
332 @@ -660,7 +753,6 @@ enum rtl_register_content {
333 #define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN)
334 #define RTL8153_RMS RTL8153_MAX_PACKET
335 #define RTL8152_TX_TIMEOUT (5 * HZ)
336 -#define RTL8152_NAPI_WEIGHT 64
337 #define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN)
338 #define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN)
339 #define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN)
340 @@ -797,6 +889,7 @@ struct r8152 {
341 } rtl_ops;
342
343 struct ups_info {
344 + u32 r_tune:1;
345 u32 _10m_ckdiv:1;
346 u32 _250m_ckdiv:1;
347 u32 aldps:1;
348 @@ -838,7 +931,9 @@ struct r8152 {
349 u32 rx_buf_sz;
350 u32 rx_copybreak;
351 u32 rx_pending;
352 + u32 fc_pause_on, fc_pause_off;
353
354 + u32 support_2500full:1;
355 u16 ocp_base;
356 u16 speed;
357 u16 eee_adv;
358 @@ -998,6 +1093,15 @@ enum rtl_version {
359 RTL_VER_07,
360 RTL_VER_08,
361 RTL_VER_09,
362 +
363 + RTL_TEST_01,
364 + RTL_VER_10,
365 + RTL_VER_11,
366 + RTL_VER_12,
367 + RTL_VER_13,
368 + RTL_VER_14,
369 + RTL_VER_15,
370 +
371 RTL_VER_MAX
372 };
373
374 @@ -1013,6 +1117,7 @@ enum tx_csum_stat {
375 #define RTL_ADVERTISED_100_FULL BIT(3)
376 #define RTL_ADVERTISED_1000_HALF BIT(4)
377 #define RTL_ADVERTISED_1000_FULL BIT(5)
378 +#define RTL_ADVERTISED_2500_FULL BIT(6)
379
380 /* Maximum number of multicast addresses to filter (vs. Rx-all-multicast).
381 * The RTL chips use a 64 element hash table based on the Ethernet CRC.
382 @@ -2608,7 +2713,7 @@ static netdev_tx_t rtl8152_start_xmit(st
383
384 static void r8152b_reset_packet_filter(struct r8152 *tp)
385 {
386 - u32 ocp_data;
387 + u32 ocp_data;
388
389 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC);
390 ocp_data &= ~FMC_FCR_MCU_EN;
391 @@ -2619,14 +2724,47 @@ static void r8152b_reset_packet_filter(s
392
393 static void rtl8152_nic_reset(struct r8152 *tp)
394 {
395 - int i;
396 + u32 ocp_data;
397 + int i;
398
399 - ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
400 + switch (tp->version) {
401 + case RTL_TEST_01:
402 + case RTL_VER_10:
403 + case RTL_VER_11:
404 + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
405 + ocp_data &= ~CR_TE;
406 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
407 +
408 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
409 + ocp_data &= ~BMU_RESET_EP_IN;
410 + ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
411 +
412 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
413 + ocp_data |= CDC_ECM_EN;
414 + ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
415 +
416 + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR);
417 + ocp_data &= ~CR_RE;
418 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data);
419 +
420 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET);
421 + ocp_data |= BMU_RESET_EP_IN;
422 + ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data);
423 +
424 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
425 + ocp_data &= ~CDC_ECM_EN;
426 + ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
427 + break;
428
429 - for (i = 0; i < 1000; i++) {
430 - if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
431 - break;
432 - usleep_range(100, 400);
433 + default:
434 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST);
435 +
436 + for (i = 0; i < 1000; i++) {
437 + if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST))
438 + break;
439 + usleep_range(100, 400);
440 + }
441 + break;
442 }
443 }
444
445 @@ -2635,9 +2773,9 @@ static void set_tx_qlen(struct r8152 *tp
446 tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc));
447 }
448
449 -static inline u8 rtl8152_get_speed(struct r8152 *tp)
450 +static inline u16 rtl8152_get_speed(struct r8152 *tp)
451 {
452 - return ocp_read_byte(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
453 + return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS);
454 }
455
456 static void rtl_eee_plus_en(struct r8152 *tp, bool enable)
457 @@ -2797,6 +2935,7 @@ static int rtl_enable(struct r8152 *tp)
458 switch (tp->version) {
459 case RTL_VER_08:
460 case RTL_VER_09:
461 + case RTL_VER_14:
462 r8153b_rx_agg_chg_indicate(tp);
463 break;
464 default:
465 @@ -2834,6 +2973,7 @@ static void r8153_set_rx_early_timeout(s
466
467 case RTL_VER_08:
468 case RTL_VER_09:
469 + case RTL_VER_14:
470 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout
471 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns.
472 */
473 @@ -2843,6 +2983,18 @@ static void r8153_set_rx_early_timeout(s
474 ocp_data);
475 break;
476
477 + case RTL_VER_10:
478 + case RTL_VER_11:
479 + case RTL_VER_12:
480 + case RTL_VER_13:
481 + case RTL_VER_15:
482 + ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT,
483 + 640 / 8);
484 + ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR,
485 + ocp_data);
486 + r8153b_rx_agg_chg_indicate(tp);
487 + break;
488 +
489 default:
490 break;
491 }
492 @@ -2862,8 +3014,19 @@ static void r8153_set_rx_early_size(stru
493 break;
494 case RTL_VER_08:
495 case RTL_VER_09:
496 + case RTL_VER_14:
497 + ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
498 + ocp_data / 8);
499 + break;
500 + case RTL_TEST_01:
501 + case RTL_VER_10:
502 + case RTL_VER_11:
503 + case RTL_VER_12:
504 + case RTL_VER_13:
505 + case RTL_VER_15:
506 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE,
507 ocp_data / 8);
508 + r8153b_rx_agg_chg_indicate(tp);
509 break;
510 default:
511 WARN_ON_ONCE(1);
512 @@ -2873,6 +3036,8 @@ static void r8153_set_rx_early_size(stru
513
514 static int rtl8153_enable(struct r8152 *tp)
515 {
516 + u32 ocp_data;
517 +
518 if (test_bit(RTL8152_UNPLUG, &tp->flags))
519 return -ENODEV;
520
521 @@ -2883,15 +3048,18 @@ static int rtl8153_enable(struct r8152 *
522
523 rtl_set_ifg(tp, rtl8152_get_speed(tp));
524
525 - if (tp->version == RTL_VER_09) {
526 - u32 ocp_data;
527 -
528 + switch (tp->version) {
529 + case RTL_VER_09:
530 + case RTL_VER_14:
531 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
532 ocp_data &= ~FC_PATCH_TASK;
533 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
534 usleep_range(1000, 2000);
535 ocp_data |= FC_PATCH_TASK;
536 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
537 + break;
538 + default:
539 + break;
540 }
541
542 return rtl_enable(tp);
543 @@ -2956,12 +3124,40 @@ static void rtl_rx_vlan_en(struct r8152
544 {
545 u32 ocp_data;
546
547 - ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
548 - if (enable)
549 - ocp_data |= CPCR_RX_VLAN;
550 - else
551 - ocp_data &= ~CPCR_RX_VLAN;
552 - ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
553 + switch (tp->version) {
554 + case RTL_VER_01:
555 + case RTL_VER_02:
556 + case RTL_VER_03:
557 + case RTL_VER_04:
558 + case RTL_VER_05:
559 + case RTL_VER_06:
560 + case RTL_VER_07:
561 + case RTL_VER_08:
562 + case RTL_VER_09:
563 + case RTL_VER_14:
564 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
565 + if (enable)
566 + ocp_data |= CPCR_RX_VLAN;
567 + else
568 + ocp_data &= ~CPCR_RX_VLAN;
569 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
570 + break;
571 +
572 + case RTL_TEST_01:
573 + case RTL_VER_10:
574 + case RTL_VER_11:
575 + case RTL_VER_12:
576 + case RTL_VER_13:
577 + case RTL_VER_15:
578 + default:
579 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1);
580 + if (enable)
581 + ocp_data |= OUTER_VLAN | INNER_VLAN;
582 + else
583 + ocp_data &= ~(OUTER_VLAN | INNER_VLAN);
584 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data);
585 + break;
586 + }
587 }
588
589 static int rtl8152_set_features(struct net_device *dev,
590 @@ -3054,6 +3250,40 @@ static void __rtl_set_wol(struct r8152 *
591 device_set_wakeup_enable(&tp->udev->dev, false);
592 }
593
594 +static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable)
595 +{
596 + u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
597 +
598 + /* MAC clock speed down */
599 + if (enable)
600 + ocp_data |= MAC_CLK_SPDWN_EN;
601 + else
602 + ocp_data &= ~MAC_CLK_SPDWN_EN;
603 +
604 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
605 +}
606 +
607 +static void r8156_mac_clk_spd(struct r8152 *tp, bool enable)
608 +{
609 + u32 ocp_data;
610 +
611 + /* MAC clock speed down */
612 + if (enable) {
613 + /* aldps_spdwn_ratio, tp10_spdwn_ratio */
614 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL,
615 + 0x0403);
616 +
617 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
618 + ocp_data &= ~EEE_SPDWN_RATIO_MASK;
619 + ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */
620 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
621 + } else {
622 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
623 + ocp_data &= ~MAC_CLK_SPDWN_EN;
624 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
625 + }
626 +}
627 +
628 static void r8153_u1u2en(struct r8152 *tp, bool enable)
629 {
630 u8 u1u2[8];
631 @@ -3113,6 +3343,9 @@ static void r8153b_ups_flags(struct r815
632 if (tp->ups_info.eee_cmod_lv)
633 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN;
634
635 + if (tp->ups_info.r_tune)
636 + ups_flags |= UPS_FLAGS_R_TUNE;
637 +
638 if (tp->ups_info._10m_ckdiv)
639 ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
640
641 @@ -3163,6 +3396,88 @@ static void r8153b_ups_flags(struct r815
642 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
643 }
644
645 +static void r8156_ups_flags(struct r8152 *tp)
646 +{
647 + u32 ups_flags = 0;
648 +
649 + if (tp->ups_info.green)
650 + ups_flags |= UPS_FLAGS_EN_GREEN;
651 +
652 + if (tp->ups_info.aldps)
653 + ups_flags |= UPS_FLAGS_EN_ALDPS;
654 +
655 + if (tp->ups_info.eee)
656 + ups_flags |= UPS_FLAGS_EN_EEE;
657 +
658 + if (tp->ups_info.flow_control)
659 + ups_flags |= UPS_FLAGS_EN_FLOW_CTR;
660 +
661 + if (tp->ups_info.eee_ckdiv)
662 + ups_flags |= UPS_FLAGS_EN_EEE_CKDIV;
663 +
664 + if (tp->ups_info._10m_ckdiv)
665 + ups_flags |= UPS_FLAGS_EN_10M_CKDIV;
666 +
667 + if (tp->ups_info.eee_plloff_100)
668 + ups_flags |= UPS_FLAGS_EEE_PLLOFF_100;
669 +
670 + if (tp->ups_info.eee_plloff_giga)
671 + ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA;
672 +
673 + if (tp->ups_info._250m_ckdiv)
674 + ups_flags |= UPS_FLAGS_250M_CKDIV;
675 +
676 + switch (tp->ups_info.speed_duplex) {
677 + case FORCE_10M_HALF:
678 + ups_flags |= ups_flags_speed(0);
679 + break;
680 + case FORCE_10M_FULL:
681 + ups_flags |= ups_flags_speed(1);
682 + break;
683 + case FORCE_100M_HALF:
684 + ups_flags |= ups_flags_speed(2);
685 + break;
686 + case FORCE_100M_FULL:
687 + ups_flags |= ups_flags_speed(3);
688 + break;
689 + case NWAY_10M_HALF:
690 + ups_flags |= ups_flags_speed(4);
691 + break;
692 + case NWAY_10M_FULL:
693 + ups_flags |= ups_flags_speed(5);
694 + break;
695 + case NWAY_100M_HALF:
696 + ups_flags |= ups_flags_speed(6);
697 + break;
698 + case NWAY_100M_FULL:
699 + ups_flags |= ups_flags_speed(7);
700 + break;
701 + case NWAY_1000M_FULL:
702 + ups_flags |= ups_flags_speed(8);
703 + break;
704 + case NWAY_2500M_FULL:
705 + ups_flags |= ups_flags_speed(9);
706 + break;
707 + default:
708 + break;
709 + }
710 +
711 + switch (tp->ups_info.lite_mode) {
712 + case 1:
713 + ups_flags |= 0 << 5;
714 + break;
715 + case 2:
716 + ups_flags |= 2 << 5;
717 + break;
718 + case 0:
719 + default:
720 + ups_flags |= 1 << 5;
721 + break;
722 + }
723 +
724 + ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags);
725 +}
726 +
727 static void rtl_green_en(struct r8152 *tp, bool enable)
728 {
729 u16 data;
730 @@ -3226,16 +3541,16 @@ static void r8153b_ups_en(struct r8152 *
731 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
732 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
733
734 - ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
735 - ocp_data |= BIT(0);
736 - ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
737 + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
738 + ocp_data |= UPS_FORCE_PWR_DOWN;
739 + ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
740 } else {
741 ocp_data &= ~(UPS_EN | USP_PREWAKE);
742 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
743
744 - ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, 0xcfff);
745 - ocp_data &= ~BIT(0);
746 - ocp_write_byte(tp, MCU_TYPE_USB, 0xcfff, ocp_data);
747 + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
748 + ocp_data &= ~UPS_FORCE_PWR_DOWN;
749 + ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
750
751 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
752 int i;
753 @@ -3255,6 +3570,95 @@ static void r8153b_ups_en(struct r8152 *
754 }
755 }
756
757 +static void r8153c_ups_en(struct r8152 *tp, bool enable)
758 +{
759 + u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
760 +
761 + if (enable) {
762 + r8153b_ups_flags(tp);
763 +
764 + ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
765 + ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
766 +
767 + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
768 + ocp_data |= UPS_FORCE_PWR_DOWN;
769 + ocp_data &= ~BIT(7);
770 + ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
771 + } else {
772 + ocp_data &= ~(UPS_EN | USP_PREWAKE);
773 + ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
774 +
775 + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
776 + ocp_data &= ~UPS_FORCE_PWR_DOWN;
777 + ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
778 +
779 + if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
780 + int i;
781 +
782 + for (i = 0; i < 500; i++) {
783 + if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
784 + AUTOLOAD_DONE)
785 + break;
786 + msleep(20);
787 + }
788 +
789 + tp->rtl_ops.hw_phy_cfg(tp);
790 +
791 + rtl8152_set_speed(tp, tp->autoneg, tp->speed,
792 + tp->duplex, tp->advertising);
793 + }
794 +
795 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
796 +
797 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
798 + ocp_data |= BIT(8);
799 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
800 +
801 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
802 + }
803 +}
804 +
805 +static void r8156_ups_en(struct r8152 *tp, bool enable)
806 +{
807 + u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT);
808 +
809 + if (enable) {
810 + r8156_ups_flags(tp);
811 +
812 + ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN;
813 + ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
814 +
815 + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
816 + ocp_data |= UPS_FORCE_PWR_DOWN;
817 + ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
818 +
819 + switch (tp->version) {
820 + case RTL_VER_13:
821 + case RTL_VER_15:
822 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL);
823 + ocp_data &= ~OOBS_POLLING;
824 + ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data);
825 + break;
826 + default:
827 + break;
828 + }
829 + } else {
830 + ocp_data &= ~(UPS_EN | USP_PREWAKE);
831 + ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data);
832 +
833 + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
834 + ocp_data &= ~UPS_FORCE_PWR_DOWN;
835 + ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
836 +
837 + if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) {
838 + tp->rtl_ops.hw_phy_cfg(tp);
839 +
840 + rtl8152_set_speed(tp, tp->autoneg, tp->speed,
841 + tp->duplex, tp->advertising);
842 + }
843 + }
844 +}
845 +
846 static void r8153_power_cut_en(struct r8152 *tp, bool enable)
847 {
848 u32 ocp_data;
849 @@ -3384,6 +3788,38 @@ static void rtl8153b_runtime_enable(stru
850 }
851 }
852
853 +static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable)
854 +{
855 + if (enable) {
856 + r8153_queue_wake(tp, true);
857 + r8153b_u1u2en(tp, false);
858 + r8153_u2p3en(tp, false);
859 + rtl_runtime_suspend_enable(tp, true);
860 + r8153c_ups_en(tp, true);
861 + } else {
862 + r8153c_ups_en(tp, false);
863 + r8153_queue_wake(tp, false);
864 + rtl_runtime_suspend_enable(tp, false);
865 + r8153b_u1u2en(tp, true);
866 + }
867 +}
868 +
869 +static void rtl8156_runtime_enable(struct r8152 *tp, bool enable)
870 +{
871 + if (enable) {
872 + r8153_queue_wake(tp, true);
873 + r8153b_u1u2en(tp, false);
874 + r8153_u2p3en(tp, false);
875 + rtl_runtime_suspend_enable(tp, true);
876 + } else {
877 + r8153_queue_wake(tp, false);
878 + rtl_runtime_suspend_enable(tp, false);
879 + r8153_u2p3en(tp, true);
880 + if (tp->udev->speed >= USB_SPEED_SUPER)
881 + r8153b_u1u2en(tp, true);
882 + }
883 +}
884 +
885 static void r8153_teredo_off(struct r8152 *tp)
886 {
887 u32 ocp_data;
888 @@ -3404,14 +3840,19 @@ static void r8153_teredo_off(struct r815
889
890 case RTL_VER_08:
891 case RTL_VER_09:
892 + case RTL_TEST_01:
893 + case RTL_VER_10:
894 + case RTL_VER_11:
895 + case RTL_VER_12:
896 + case RTL_VER_13:
897 + case RTL_VER_14:
898 + case RTL_VER_15:
899 + default:
900 /* The bit 0 ~ 7 are relative with teredo settings. They are
901 * W1C (write 1 to clear), so set all 1 to disable it.
902 */
903 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff);
904 break;
905 -
906 - default:
907 - break;
908 }
909
910 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE);
911 @@ -3446,6 +3887,12 @@ static void rtl_clear_bp(struct r8152 *t
912 break;
913 case RTL_VER_08:
914 case RTL_VER_09:
915 + case RTL_VER_10:
916 + case RTL_VER_11:
917 + case RTL_VER_12:
918 + case RTL_VER_13:
919 + case RTL_VER_14:
920 + case RTL_VER_15:
921 default:
922 if (type == MCU_TYPE_USB) {
923 ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0);
924 @@ -3655,6 +4102,11 @@ static bool rtl8152_is_fw_mac_ok(struct
925 case RTL_VER_06:
926 case RTL_VER_08:
927 case RTL_VER_09:
928 + case RTL_VER_11:
929 + case RTL_VER_12:
930 + case RTL_VER_13:
931 + case RTL_VER_14:
932 + case RTL_VER_15:
933 fw_reg = 0xf800;
934 bp_ba_addr = PLA_BP_BA;
935 bp_en_addr = PLA_BP_EN;
936 @@ -3678,6 +4130,11 @@ static bool rtl8152_is_fw_mac_ok(struct
937 break;
938 case RTL_VER_08:
939 case RTL_VER_09:
940 + case RTL_VER_11:
941 + case RTL_VER_12:
942 + case RTL_VER_13:
943 + case RTL_VER_14:
944 + case RTL_VER_15:
945 fw_reg = 0xe600;
946 bp_ba_addr = USB_BP_BA;
947 bp_en_addr = USB_BP2_EN;
948 @@ -4217,6 +4674,22 @@ static void r8153_eee_en(struct r8152 *t
949 tp->ups_info.eee = enable;
950 }
951
952 +static void r8156_eee_en(struct r8152 *tp, bool enable)
953 +{
954 + u16 config;
955 +
956 + r8153_eee_en(tp, enable);
957 +
958 + config = ocp_reg_read(tp, OCP_EEE_ADV2);
959 +
960 + if (enable)
961 + config |= MDIO_EEE_2_5GT;
962 + else
963 + config &= ~MDIO_EEE_2_5GT;
964 +
965 + ocp_reg_write(tp, OCP_EEE_ADV2, config);
966 +}
967 +
968 static void rtl_eee_enable(struct r8152 *tp, bool enable)
969 {
970 switch (tp->version) {
971 @@ -4238,6 +4711,7 @@ static void rtl_eee_enable(struct r8152
972 case RTL_VER_06:
973 case RTL_VER_08:
974 case RTL_VER_09:
975 + case RTL_VER_14:
976 if (enable) {
977 r8153_eee_en(tp, true);
978 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
979 @@ -4246,6 +4720,19 @@ static void rtl_eee_enable(struct r8152
980 ocp_reg_write(tp, OCP_EEE_ADV, 0);
981 }
982 break;
983 + case RTL_VER_10:
984 + case RTL_VER_11:
985 + case RTL_VER_12:
986 + case RTL_VER_13:
987 + case RTL_VER_15:
988 + if (enable) {
989 + r8156_eee_en(tp, true);
990 + ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv);
991 + } else {
992 + r8156_eee_en(tp, false);
993 + ocp_reg_write(tp, OCP_EEE_ADV, 0);
994 + }
995 + break;
996 default:
997 break;
998 }
999 @@ -4292,6 +4779,20 @@ static void wait_oob_link_list_ready(str
1000 }
1001 }
1002
1003 +static void r8156b_wait_loading_flash(struct r8152 *tp)
1004 +{
1005 + if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) &&
1006 + !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) {
1007 + int i;
1008 +
1009 + for (i = 0; i < 100; i++) {
1010 + if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE)
1011 + break;
1012 + usleep_range(1000, 2000);
1013 + }
1014 + }
1015 +}
1016 +
1017 static void r8152b_exit_oob(struct r8152 *tp)
1018 {
1019 u32 ocp_data;
1020 @@ -4342,7 +4843,7 @@ static void r8152b_exit_oob(struct r8152
1021 }
1022
1023 /* TX share fifo free credit full threshold */
1024 - ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL);
1025 + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2);
1026
1027 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD);
1028 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH);
1029 @@ -4519,6 +5020,21 @@ static int r8153b_post_firmware_1(struct
1030 return 0;
1031 }
1032
1033 +static int r8153c_post_firmware_1(struct r8152 *tp)
1034 +{
1035 + u32 ocp_data;
1036 +
1037 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
1038 + ocp_data |= FLOW_CTRL_PATCH_2;
1039 + ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
1040 +
1041 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
1042 + ocp_data |= FC_PATCH_TASK;
1043 + ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
1044 +
1045 + return 0;
1046 +}
1047 +
1048 static void r8153_aldps_en(struct r8152 *tp, bool enable)
1049 {
1050 u16 data;
1051 @@ -4721,6 +5237,13 @@ static void r8153b_hw_phy_cfg(struct r81
1052 set_bit(PHY_RESET, &tp->flags);
1053 }
1054
1055 +static void r8153c_hw_phy_cfg(struct r8152 *tp)
1056 +{
1057 + r8153b_hw_phy_cfg(tp);
1058 +
1059 + tp->ups_info.r_tune = true;
1060 +}
1061 +
1062 static void rtl8153_change_mtu(struct r8152 *tp)
1063 {
1064 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
1065 @@ -4808,6 +5331,7 @@ static void r8153_enter_oob(struct r8152
1066
1067 case RTL_VER_08:
1068 case RTL_VER_09:
1069 + case RTL_VER_14:
1070 /* Clear teredo wake event. bit[15:8] is the teredo wakeup
1071 * type. Set it to zero. bits[7:0] are the W1C bits about
1072 * the events. Set them to all 1 to clear them.
1073 @@ -4844,6 +5368,96 @@ static void rtl8153_disable(struct r8152
1074 r8153_aldps_en(tp, true);
1075 }
1076
1077 +static int rtl8156_enable(struct r8152 *tp)
1078 +{
1079 + u32 ocp_data;
1080 + u16 speed;
1081 +
1082 + if (test_bit(RTL8152_UNPLUG, &tp->flags))
1083 + return -ENODEV;
1084 +
1085 + set_tx_qlen(tp);
1086 + rtl_set_eee_plus(tp);
1087 + r8153_set_rx_early_timeout(tp);
1088 + r8153_set_rx_early_size(tp);
1089 +
1090 + speed = rtl8152_get_speed(tp);
1091 + rtl_set_ifg(tp, speed);
1092 +
1093 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
1094 + if (speed & _2500bps)
1095 + ocp_data &= ~IDLE_SPDWN_EN;
1096 + else
1097 + ocp_data |= IDLE_SPDWN_EN;
1098 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
1099 +
1100 + if (speed & _1000bps)
1101 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11);
1102 + else if (speed & _500bps)
1103 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d);
1104 +
1105 + if (tp->udev->speed == USB_SPEED_HIGH) {
1106 + /* USB 0xb45e[3:0] l1_nyet_hird */
1107 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
1108 + ocp_data &= ~0xf;
1109 + if (is_flow_control(speed))
1110 + ocp_data |= 0xf;
1111 + else
1112 + ocp_data |= 0x1;
1113 + ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
1114 + }
1115 +
1116 + return rtl_enable(tp);
1117 +}
1118 +
1119 +static int rtl8156b_enable(struct r8152 *tp)
1120 +{
1121 + u32 ocp_data;
1122 + u16 speed;
1123 +
1124 + if (test_bit(RTL8152_UNPLUG, &tp->flags))
1125 + return -ENODEV;
1126 +
1127 + set_tx_qlen(tp);
1128 + rtl_set_eee_plus(tp);
1129 +
1130 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM);
1131 + ocp_data &= ~RX_AGGR_NUM_MASK;
1132 + ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data);
1133 +
1134 + r8153_set_rx_early_timeout(tp);
1135 + r8153_set_rx_early_size(tp);
1136 +
1137 + speed = rtl8152_get_speed(tp);
1138 + rtl_set_ifg(tp, speed);
1139 +
1140 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
1141 + if (speed & _2500bps)
1142 + ocp_data &= ~IDLE_SPDWN_EN;
1143 + else
1144 + ocp_data |= IDLE_SPDWN_EN;
1145 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
1146 +
1147 + if (tp->udev->speed == USB_SPEED_HIGH) {
1148 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL);
1149 + ocp_data &= ~0xf;
1150 + if (is_flow_control(speed))
1151 + ocp_data |= 0xf;
1152 + else
1153 + ocp_data |= 0x1;
1154 + ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data);
1155 + }
1156 +
1157 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
1158 + ocp_data &= ~FC_PATCH_TASK;
1159 + ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
1160 + usleep_range(1000, 2000);
1161 + ocp_data |= FC_PATCH_TASK;
1162 + ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
1163 +
1164 + return rtl_enable(tp);
1165 +}
1166 +
1167 static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex,
1168 u32 advertising)
1169 {
1170 @@ -4892,58 +5506,73 @@ static int rtl8152_set_speed(struct r815
1171
1172 tp->mii.force_media = 1;
1173 } else {
1174 - u16 anar, tmp1;
1175 + u16 orig, new1;
1176 u32 support;
1177
1178 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
1179 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
1180
1181 - if (tp->mii.supports_gmii)
1182 + if (tp->mii.supports_gmii) {
1183 support |= RTL_ADVERTISED_1000_FULL;
1184
1185 + if (tp->support_2500full)
1186 + support |= RTL_ADVERTISED_2500_FULL;
1187 + }
1188 +
1189 if (!(advertising & support))
1190 return -EINVAL;
1191
1192 - anar = r8152_mdio_read(tp, MII_ADVERTISE);
1193 - tmp1 = anar & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1194 + orig = r8152_mdio_read(tp, MII_ADVERTISE);
1195 + new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL |
1196 ADVERTISE_100HALF | ADVERTISE_100FULL);
1197 if (advertising & RTL_ADVERTISED_10_HALF) {
1198 - tmp1 |= ADVERTISE_10HALF;
1199 + new1 |= ADVERTISE_10HALF;
1200 tp->ups_info.speed_duplex = NWAY_10M_HALF;
1201 }
1202 if (advertising & RTL_ADVERTISED_10_FULL) {
1203 - tmp1 |= ADVERTISE_10FULL;
1204 + new1 |= ADVERTISE_10FULL;
1205 tp->ups_info.speed_duplex = NWAY_10M_FULL;
1206 }
1207
1208 if (advertising & RTL_ADVERTISED_100_HALF) {
1209 - tmp1 |= ADVERTISE_100HALF;
1210 + new1 |= ADVERTISE_100HALF;
1211 tp->ups_info.speed_duplex = NWAY_100M_HALF;
1212 }
1213 if (advertising & RTL_ADVERTISED_100_FULL) {
1214 - tmp1 |= ADVERTISE_100FULL;
1215 + new1 |= ADVERTISE_100FULL;
1216 tp->ups_info.speed_duplex = NWAY_100M_FULL;
1217 }
1218
1219 - if (anar != tmp1) {
1220 - r8152_mdio_write(tp, MII_ADVERTISE, tmp1);
1221 - tp->mii.advertising = tmp1;
1222 + if (orig != new1) {
1223 + r8152_mdio_write(tp, MII_ADVERTISE, new1);
1224 + tp->mii.advertising = new1;
1225 }
1226
1227 if (tp->mii.supports_gmii) {
1228 - u16 gbcr;
1229 -
1230 - gbcr = r8152_mdio_read(tp, MII_CTRL1000);
1231 - tmp1 = gbcr & ~(ADVERTISE_1000FULL |
1232 + orig = r8152_mdio_read(tp, MII_CTRL1000);
1233 + new1 = orig & ~(ADVERTISE_1000FULL |
1234 ADVERTISE_1000HALF);
1235
1236 if (advertising & RTL_ADVERTISED_1000_FULL) {
1237 - tmp1 |= ADVERTISE_1000FULL;
1238 + new1 |= ADVERTISE_1000FULL;
1239 tp->ups_info.speed_duplex = NWAY_1000M_FULL;
1240 }
1241
1242 - if (gbcr != tmp1)
1243 - r8152_mdio_write(tp, MII_CTRL1000, tmp1);
1244 + if (orig != new1)
1245 + r8152_mdio_write(tp, MII_CTRL1000, new1);
1246 + }
1247 +
1248 + if (tp->support_2500full) {
1249 + orig = ocp_reg_read(tp, OCP_10GBT_CTRL);
1250 + new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G;
1251 +
1252 + if (advertising & RTL_ADVERTISED_2500_FULL) {
1253 + new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G;
1254 + tp->ups_info.speed_duplex = NWAY_2500M_FULL;
1255 + }
1256 +
1257 + if (orig != new1)
1258 + ocp_reg_write(tp, OCP_10GBT_CTRL, new1);
1259 }
1260
1261 bmcr = BMCR_ANENABLE | BMCR_ANRESTART;
1262 @@ -5099,6 +5728,253 @@ static void rtl8153b_down(struct r8152 *
1263 r8153_aldps_en(tp, true);
1264 }
1265
1266 +static void rtl8153c_change_mtu(struct r8152 *tp)
1267 +{
1268 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu));
1269 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64);
1270 +
1271 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
1272 +
1273 + /* Adjust the tx fifo free credit full threshold, otherwise
1274 + * the fifo would be too small to send a jumbo frame packet.
1275 + */
1276 + if (tp->netdev->mtu < 8000)
1277 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8);
1278 + else
1279 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8);
1280 +}
1281 +
1282 +static void rtl8153c_up(struct r8152 *tp)
1283 +{
1284 + u32 ocp_data;
1285 +
1286 + if (test_bit(RTL8152_UNPLUG, &tp->flags))
1287 + return;
1288 +
1289 + r8153b_u1u2en(tp, false);
1290 + r8153_u2p3en(tp, false);
1291 + r8153_aldps_en(tp, false);
1292 +
1293 + rxdy_gated_en(tp, true);
1294 + r8153_teredo_off(tp);
1295 +
1296 + ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1297 + ocp_data &= ~RCR_ACPT_ALL;
1298 + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1299 +
1300 + rtl8152_nic_reset(tp);
1301 + rtl_reset_bmu(tp);
1302 +
1303 + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1304 + ocp_data &= ~NOW_IS_OOB;
1305 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1306 +
1307 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1308 + ocp_data &= ~MCU_BORW_EN;
1309 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1310 +
1311 + wait_oob_link_list_ready(tp);
1312 +
1313 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1314 + ocp_data |= RE_INIT_LL;
1315 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1316 +
1317 + wait_oob_link_list_ready(tp);
1318 +
1319 + rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
1320 +
1321 + rtl8153c_change_mtu(tp);
1322 +
1323 + rtl8152_nic_reset(tp);
1324 +
1325 + /* rx share fifo credit full threshold */
1326 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02);
1327 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08);
1328 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL);
1329 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL);
1330 +
1331 + ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B);
1332 +
1333 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1334 +
1335 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34);
1336 + ocp_data |= BIT(8);
1337 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data);
1338 +
1339 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML);
1340 +
1341 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
1342 + ocp_data &= ~PLA_MCU_SPDWN_EN;
1343 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
1344 +
1345 + r8153_aldps_en(tp, true);
1346 + r8153b_u1u2en(tp, true);
1347 +}
1348 +
1349 +static inline u32 fc_pause_on_auto(struct r8152 *tp)
1350 +{
1351 + return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024);
1352 +}
1353 +
1354 +static inline u32 fc_pause_off_auto(struct r8152 *tp)
1355 +{
1356 + return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024);
1357 +}
1358 +
1359 +static void r8156_fc_parameter(struct r8152 *tp)
1360 +{
1361 + u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp);
1362 + u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp);
1363 +
1364 + switch (tp->version) {
1365 + case RTL_VER_10:
1366 + case RTL_VER_11:
1367 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 8);
1368 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 8);
1369 + break;
1370 + case RTL_VER_12:
1371 + case RTL_VER_13:
1372 + case RTL_VER_15:
1373 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16);
1374 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16);
1375 + break;
1376 + default:
1377 + break;
1378 + }
1379 +}
1380 +
1381 +static void rtl8156_change_mtu(struct r8152 *tp)
1382 +{
1383 + u32 rx_max_size = mtu_to_size(tp->netdev->mtu);
1384 +
1385 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size);
1386 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO);
1387 + r8156_fc_parameter(tp);
1388 +
1389 + /* TX share fifo free credit full threshold */
1390 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64);
1391 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL,
1392 + ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16);
1393 +}
1394 +
1395 +static void rtl8156_up(struct r8152 *tp)
1396 +{
1397 + u32 ocp_data;
1398 +
1399 + if (test_bit(RTL8152_UNPLUG, &tp->flags))
1400 + return;
1401 +
1402 + r8153b_u1u2en(tp, false);
1403 + r8153_u2p3en(tp, false);
1404 + r8153_aldps_en(tp, false);
1405 +
1406 + rxdy_gated_en(tp, true);
1407 + r8153_teredo_off(tp);
1408 +
1409 + ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1410 + ocp_data &= ~RCR_ACPT_ALL;
1411 + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1412 +
1413 + rtl8152_nic_reset(tp);
1414 + rtl_reset_bmu(tp);
1415 +
1416 + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1417 + ocp_data &= ~NOW_IS_OOB;
1418 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1419 +
1420 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7);
1421 + ocp_data &= ~MCU_BORW_EN;
1422 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data);
1423 +
1424 + rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX);
1425 +
1426 + rtl8156_change_mtu(tp);
1427 +
1428 + switch (tp->version) {
1429 + case RTL_TEST_01:
1430 + case RTL_VER_10:
1431 + case RTL_VER_11:
1432 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
1433 + ocp_data |= ACT_ODMA;
1434 + ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
1435 + break;
1436 + default:
1437 + break;
1438 + }
1439 +
1440 + /* share FIFO settings */
1441 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL);
1442 + ocp_data &= ~RXFIFO_FULL_MASK;
1443 + ocp_data |= 0x08;
1444 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data);
1445 +
1446 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
1447 + ocp_data &= ~PLA_MCU_SPDWN_EN;
1448 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
1449 +
1450 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION);
1451 + ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF);
1452 + ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data);
1453 +
1454 + ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400);
1455 +
1456 + if (tp->saved_wolopts != __rtl_get_wol(tp)) {
1457 + netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n");
1458 + __rtl_set_wol(tp, tp->saved_wolopts);
1459 + }
1460 +
1461 + r8153_aldps_en(tp, true);
1462 + r8153_u2p3en(tp, true);
1463 +
1464 + if (tp->udev->speed >= USB_SPEED_SUPER)
1465 + r8153b_u1u2en(tp, true);
1466 +}
1467 +
1468 +static void rtl8156_down(struct r8152 *tp)
1469 +{
1470 + u32 ocp_data;
1471 +
1472 + if (test_bit(RTL8152_UNPLUG, &tp->flags)) {
1473 + rtl_drop_queued_tx(tp);
1474 + return;
1475 + }
1476 +
1477 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
1478 + ocp_data |= PLA_MCU_SPDWN_EN;
1479 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
1480 +
1481 + r8153b_u1u2en(tp, false);
1482 + r8153_u2p3en(tp, false);
1483 + r8153b_power_cut_en(tp, false);
1484 + r8153_aldps_en(tp, false);
1485 +
1486 + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1487 + ocp_data &= ~NOW_IS_OOB;
1488 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1489 +
1490 + rtl_disable(tp);
1491 + rtl_reset_bmu(tp);
1492 +
1493 + /* Clear teredo wake event. bit[15:8] is the teredo wakeup
1494 + * type. Set it to zero. bits[7:0] are the W1C bits about
1495 + * the events. Set them to all 1 to clear them.
1496 + */
1497 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff);
1498 +
1499 + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL);
1500 + ocp_data |= NOW_IS_OOB;
1501 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data);
1502 +
1503 + rtl_rx_vlan_en(tp, true);
1504 + rxdy_gated_en(tp, false);
1505 +
1506 + ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR);
1507 + ocp_data |= RCR_APM | RCR_AM | RCR_AB;
1508 + ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
1509 +
1510 + r8153_aldps_en(tp, true);
1511 +}
1512 +
1513 static bool rtl8152_in_nway(struct r8152 *tp)
1514 {
1515 u16 nway_state;
1516 @@ -5129,7 +6005,7 @@ static void set_carrier(struct r8152 *tp
1517 {
1518 struct net_device *netdev = tp->netdev;
1519 struct napi_struct *napi = &tp->napi;
1520 - u8 speed;
1521 + u16 speed;
1522
1523 speed = rtl8152_get_speed(tp);
1524
1525 @@ -5142,7 +6018,7 @@ static void set_carrier(struct r8152 *tp
1526 rtl_start_rx(tp);
1527 clear_bit(RTL8152_SET_RX_MODE, &tp->flags);
1528 _rtl8152_set_rx_mode(netdev);
1529 - napi_enable(&tp->napi);
1530 + napi_enable(napi);
1531 netif_wake_queue(netdev);
1532 netif_info(tp, link, netdev, "carrier on\n");
1533 } else if (netif_queue_stopped(netdev) &&
1534 @@ -5504,14 +6380,9 @@ static void r8153_init(struct r8152 *tp)
1535
1536 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001);
1537
1538 - /* MAC clock speed down */
1539 - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 0);
1540 - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, 0);
1541 - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, 0);
1542 - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, 0);
1543 -
1544 r8153_power_cut_en(tp, false);
1545 rtl_runtime_suspend_enable(tp, false);
1546 + r8153_mac_clk_speed_down(tp, false);
1547 r8153_u1u2en(tp, true);
1548 usb_enable_lpm(tp->udev);
1549
1550 @@ -5602,9 +6473,7 @@ static void r8153b_init(struct r8152 *tp
1551 usb_enable_lpm(tp->udev);
1552
1553 /* MAC clock speed down */
1554 - ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2);
1555 - ocp_data |= MAC_CLK_SPDWN_EN;
1556 - ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data);
1557 + r8153_mac_clk_speed_down(tp, true);
1558
1559 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
1560 ocp_data &= ~PLA_MCU_SPDWN_EN;
1561 @@ -5631,6 +6500,1069 @@ static void r8153b_init(struct r8152 *tp
1562 tp->coalesce = 15000; /* 15 us */
1563 }
1564
1565 +static void r8153c_init(struct r8152 *tp)
1566 +{
1567 + u32 ocp_data;
1568 + u16 data;
1569 + int i;
1570 +
1571 + if (test_bit(RTL8152_UNPLUG, &tp->flags))
1572 + return;
1573 +
1574 + r8153b_u1u2en(tp, false);
1575 +
1576 + /* Disable spi_en */
1577 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG);
1578 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5);
1579 + ocp_data &= ~BIT(3);
1580 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data);
1581 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0);
1582 + ocp_data |= BIT(1);
1583 + ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data);
1584 +
1585 + for (i = 0; i < 500; i++) {
1586 + if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
1587 + AUTOLOAD_DONE)
1588 + break;
1589 +
1590 + msleep(20);
1591 + if (test_bit(RTL8152_UNPLUG, &tp->flags))
1592 + return;
1593 + }
1594 +
1595 + data = r8153_phy_status(tp, 0);
1596 +
1597 + data = r8152_mdio_read(tp, MII_BMCR);
1598 + if (data & BMCR_PDOWN) {
1599 + data &= ~BMCR_PDOWN;
1600 + r8152_mdio_write(tp, MII_BMCR, data);
1601 + }
1602 +
1603 + data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
1604 +
1605 + r8153_u2p3en(tp, false);
1606 +
1607 + /* MSC timer = 0xfff * 8ms = 32760 ms */
1608 + ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
1609 +
1610 + r8153b_power_cut_en(tp, false);
1611 + r8153c_ups_en(tp, false);
1612 + r8153_queue_wake(tp, false);
1613 + rtl_runtime_suspend_enable(tp, false);
1614 +
1615 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
1616 + if (rtl8152_get_speed(tp) & LINK_STATUS)
1617 + ocp_data |= CUR_LINK_OK;
1618 + else
1619 + ocp_data &= ~CUR_LINK_OK;
1620 +
1621 + ocp_data |= POLL_LINK_CHG;
1622 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
1623 +
1624 + r8153b_u1u2en(tp, true);
1625 +
1626 + usb_enable_lpm(tp->udev);
1627 +
1628 + /* MAC clock speed down */
1629 + r8153_mac_clk_speed_down(tp, true);
1630 +
1631 + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2);
1632 + ocp_data &= ~BIT(7);
1633 + ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data);
1634 +
1635 + set_bit(GREEN_ETHERNET, &tp->flags);
1636 +
1637 + /* rx aggregation */
1638 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
1639 + ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
1640 + ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
1641 +
1642 + rtl_tally_reset(tp);
1643 +
1644 + tp->coalesce = 15000; /* 15 us */
1645 +}
1646 +
1647 +static void r8156_hw_phy_cfg(struct r8152 *tp)
1648 +{
1649 + u32 ocp_data;
1650 + u16 data;
1651 +
1652 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
1653 + if (ocp_data & PCUT_STATUS) {
1654 + ocp_data &= ~PCUT_STATUS;
1655 + ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
1656 + }
1657 +
1658 + data = r8153_phy_status(tp, 0);
1659 + switch (data) {
1660 + case PHY_STAT_EXT_INIT:
1661 + rtl8152_apply_firmware(tp, true);
1662 +
1663 + data = ocp_reg_read(tp, 0xa468);
1664 + data &= ~(BIT(3) | BIT(1));
1665 + ocp_reg_write(tp, 0xa468, data);
1666 + break;
1667 + case PHY_STAT_LAN_ON:
1668 + case PHY_STAT_PWRDN:
1669 + default:
1670 + rtl8152_apply_firmware(tp, false);
1671 + break;
1672 + }
1673 +
1674 + /* disable ALDPS before updating the PHY parameters */
1675 + r8153_aldps_en(tp, false);
1676 +
1677 + /* disable EEE before updating the PHY parameters */
1678 + rtl_eee_enable(tp, false);
1679 +
1680 + data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
1681 + WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
1682 +
1683 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
1684 + ocp_data |= PFM_PWM_SWITCH;
1685 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
1686 +
1687 + switch (tp->version) {
1688 + case RTL_VER_10:
1689 + data = ocp_reg_read(tp, 0xad40);
1690 + data &= ~0x3ff;
1691 + data |= BIT(7) | BIT(2);
1692 + ocp_reg_write(tp, 0xad40, data);
1693 +
1694 + data = ocp_reg_read(tp, 0xad4e);
1695 + data |= BIT(4);
1696 + ocp_reg_write(tp, 0xad4e, data);
1697 + data = ocp_reg_read(tp, 0xad16);
1698 + data &= ~0x3ff;
1699 + data |= 0x6;
1700 + ocp_reg_write(tp, 0xad16, data);
1701 + data = ocp_reg_read(tp, 0xad32);
1702 + data &= ~0x3f;
1703 + data |= 6;
1704 + ocp_reg_write(tp, 0xad32, data);
1705 + data = ocp_reg_read(tp, 0xac08);
1706 + data &= ~(BIT(12) | BIT(8));
1707 + ocp_reg_write(tp, 0xac08, data);
1708 + data = ocp_reg_read(tp, 0xac8a);
1709 + data |= BIT(12) | BIT(13) | BIT(14);
1710 + data &= ~BIT(15);
1711 + ocp_reg_write(tp, 0xac8a, data);
1712 + data = ocp_reg_read(tp, 0xad18);
1713 + data |= BIT(10);
1714 + ocp_reg_write(tp, 0xad18, data);
1715 + data = ocp_reg_read(tp, 0xad1a);
1716 + data |= 0x3ff;
1717 + ocp_reg_write(tp, 0xad1a, data);
1718 + data = ocp_reg_read(tp, 0xad1c);
1719 + data |= 0x3ff;
1720 + ocp_reg_write(tp, 0xad1c, data);
1721 +
1722 + data = sram_read(tp, 0x80ea);
1723 + data &= ~0xff00;
1724 + data |= 0xc400;
1725 + sram_write(tp, 0x80ea, data);
1726 + data = sram_read(tp, 0x80eb);
1727 + data &= ~0x0700;
1728 + data |= 0x0300;
1729 + sram_write(tp, 0x80eb, data);
1730 + data = sram_read(tp, 0x80f8);
1731 + data &= ~0xff00;
1732 + data |= 0x1c00;
1733 + sram_write(tp, 0x80f8, data);
1734 + data = sram_read(tp, 0x80f1);
1735 + data &= ~0xff00;
1736 + data |= 0x3000;
1737 + sram_write(tp, 0x80f1, data);
1738 +
1739 + data = sram_read(tp, 0x80fe);
1740 + data &= ~0xff00;
1741 + data |= 0xa500;
1742 + sram_write(tp, 0x80fe, data);
1743 + data = sram_read(tp, 0x8102);
1744 + data &= ~0xff00;
1745 + data |= 0x5000;
1746 + sram_write(tp, 0x8102, data);
1747 + data = sram_read(tp, 0x8015);
1748 + data &= ~0xff00;
1749 + data |= 0x3300;
1750 + sram_write(tp, 0x8015, data);
1751 + data = sram_read(tp, 0x8100);
1752 + data &= ~0xff00;
1753 + data |= 0x7000;
1754 + sram_write(tp, 0x8100, data);
1755 + data = sram_read(tp, 0x8014);
1756 + data &= ~0xff00;
1757 + data |= 0xf000;
1758 + sram_write(tp, 0x8014, data);
1759 + data = sram_read(tp, 0x8016);
1760 + data &= ~0xff00;
1761 + data |= 0x6500;
1762 + sram_write(tp, 0x8016, data);
1763 + data = sram_read(tp, 0x80dc);
1764 + data &= ~0xff00;
1765 + data |= 0xed00;
1766 + sram_write(tp, 0x80dc, data);
1767 + data = sram_read(tp, 0x80df);
1768 + data |= BIT(8);
1769 + sram_write(tp, 0x80df, data);
1770 + data = sram_read(tp, 0x80e1);
1771 + data &= ~BIT(8);
1772 + sram_write(tp, 0x80e1, data);
1773 +
1774 + data = ocp_reg_read(tp, 0xbf06);
1775 + data &= ~0x003f;
1776 + data |= 0x0038;
1777 + ocp_reg_write(tp, 0xbf06, data);
1778 +
1779 + sram_write(tp, 0x819f, 0xddb6);
1780 +
1781 + ocp_reg_write(tp, 0xbc34, 0x5555);
1782 + data = ocp_reg_read(tp, 0xbf0a);
1783 + data &= ~0x0e00;
1784 + data |= 0x0a00;
1785 + ocp_reg_write(tp, 0xbf0a, data);
1786 +
1787 + data = ocp_reg_read(tp, 0xbd2c);
1788 + data &= ~BIT(13);
1789 + ocp_reg_write(tp, 0xbd2c, data);
1790 + break;
1791 + case RTL_VER_11:
1792 + data = ocp_reg_read(tp, 0xad16);
1793 + data |= 0x3ff;
1794 + ocp_reg_write(tp, 0xad16, data);
1795 + data = ocp_reg_read(tp, 0xad32);
1796 + data &= ~0x3f;
1797 + data |= 6;
1798 + ocp_reg_write(tp, 0xad32, data);
1799 + data = ocp_reg_read(tp, 0xac08);
1800 + data &= ~(BIT(12) | BIT(8));
1801 + ocp_reg_write(tp, 0xac08, data);
1802 + data = ocp_reg_read(tp, 0xacc0);
1803 + data &= ~0x3;
1804 + data |= BIT(1);
1805 + ocp_reg_write(tp, 0xacc0, data);
1806 + data = ocp_reg_read(tp, 0xad40);
1807 + data &= ~0xe7;
1808 + data |= BIT(6) | BIT(2);
1809 + ocp_reg_write(tp, 0xad40, data);
1810 + data = ocp_reg_read(tp, 0xac14);
1811 + data &= ~BIT(7);
1812 + ocp_reg_write(tp, 0xac14, data);
1813 + data = ocp_reg_read(tp, 0xac80);
1814 + data &= ~(BIT(8) | BIT(9));
1815 + ocp_reg_write(tp, 0xac80, data);
1816 + data = ocp_reg_read(tp, 0xac5e);
1817 + data &= ~0x7;
1818 + data |= BIT(1);
1819 + ocp_reg_write(tp, 0xac5e, data);
1820 + ocp_reg_write(tp, 0xad4c, 0x00a8);
1821 + ocp_reg_write(tp, 0xac5c, 0x01ff);
1822 + data = ocp_reg_read(tp, 0xac8a);
1823 + data &= ~0xf0;
1824 + data |= BIT(4) | BIT(5);
1825 + ocp_reg_write(tp, 0xac8a, data);
1826 + ocp_reg_write(tp, 0xb87c, 0x8157);
1827 + data = ocp_reg_read(tp, 0xb87e);
1828 + data &= ~0xff00;
1829 + data |= 0x0500;
1830 + ocp_reg_write(tp, 0xb87e, data);
1831 + ocp_reg_write(tp, 0xb87c, 0x8159);
1832 + data = ocp_reg_read(tp, 0xb87e);
1833 + data &= ~0xff00;
1834 + data |= 0x0700;
1835 + ocp_reg_write(tp, 0xb87e, data);
1836 +
1837 + /* AAGC */
1838 + ocp_reg_write(tp, 0xb87c, 0x80a2);
1839 + ocp_reg_write(tp, 0xb87e, 0x0153);
1840 + ocp_reg_write(tp, 0xb87c, 0x809c);
1841 + ocp_reg_write(tp, 0xb87e, 0x0153);
1842 +
1843 + /* EEE parameter */
1844 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056);
1845 +
1846 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG);
1847 + ocp_data |= EN_XG_LIP | EN_G_LIP;
1848 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
1849 +
1850 + sram_write(tp, 0x8257, 0x020f); /* XG PLL */
1851 + sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */
1852 +
1853 + if (rtl_phy_patch_request(tp, true, true))
1854 + return;
1855 +
1856 + /* Advance EEE */
1857 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
1858 + ocp_data |= EEE_SPDWN_EN;
1859 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
1860 +
1861 + data = ocp_reg_read(tp, OCP_DOWN_SPEED);
1862 + data &= ~(EN_EEE_100 | EN_EEE_1000);
1863 + data |= EN_10M_CLKDIV;
1864 + ocp_reg_write(tp, OCP_DOWN_SPEED, data);
1865 + tp->ups_info._10m_ckdiv = true;
1866 + tp->ups_info.eee_plloff_100 = false;
1867 + tp->ups_info.eee_plloff_giga = false;
1868 +
1869 + data = ocp_reg_read(tp, OCP_POWER_CFG);
1870 + data &= ~EEE_CLKDIV_EN;
1871 + ocp_reg_write(tp, OCP_POWER_CFG, data);
1872 + tp->ups_info.eee_ckdiv = false;
1873 +
1874 + ocp_reg_write(tp, OCP_SYSCLK_CFG, 0);
1875 + ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5));
1876 + tp->ups_info._250m_ckdiv = false;
1877 +
1878 + rtl_phy_patch_request(tp, false, true);
1879 +
1880 + /* enable ADC Ibias Cal */
1881 + data = ocp_reg_read(tp, 0xd068);
1882 + data |= BIT(13);
1883 + ocp_reg_write(tp, 0xd068, data);
1884 +
1885 + /* enable Thermal Sensor */
1886 + data = sram_read(tp, 0x81a2);
1887 + data &= ~BIT(8);
1888 + sram_write(tp, 0x81a2, data);
1889 + data = ocp_reg_read(tp, 0xb54c);
1890 + data &= ~0xff00;
1891 + data |= 0xdb00;
1892 + ocp_reg_write(tp, 0xb54c, data);
1893 +
1894 + /* Nway 2.5G Lite */
1895 + data = ocp_reg_read(tp, 0xa454);
1896 + data &= ~BIT(0);
1897 + ocp_reg_write(tp, 0xa454, data);
1898 +
1899 + /* CS DSP solution */
1900 + data = ocp_reg_read(tp, OCP_10GBT_CTRL);
1901 + data |= RTL_ADV2_5G_F_R;
1902 + ocp_reg_write(tp, OCP_10GBT_CTRL, data);
1903 + data = ocp_reg_read(tp, 0xad4e);
1904 + data &= ~BIT(4);
1905 + ocp_reg_write(tp, 0xad4e, data);
1906 + data = ocp_reg_read(tp, 0xa86a);
1907 + data &= ~BIT(0);
1908 + ocp_reg_write(tp, 0xa86a, data);
1909 +
1910 + /* MDI SWAP */
1911 + if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) &&
1912 + (ocp_reg_read(tp, 0xd068) & BIT(1))) {
1913 + u16 swap_a, swap_b;
1914 +
1915 + data = ocp_reg_read(tp, 0xd068);
1916 + data &= ~0x1f;
1917 + data |= 0x1; /* p0 */
1918 + ocp_reg_write(tp, 0xd068, data);
1919 + swap_a = ocp_reg_read(tp, 0xd06a);
1920 + data &= ~0x18;
1921 + data |= 0x18; /* p3 */
1922 + ocp_reg_write(tp, 0xd068, data);
1923 + swap_b = ocp_reg_read(tp, 0xd06a);
1924 + data &= ~0x18; /* p0 */
1925 + ocp_reg_write(tp, 0xd068, data);
1926 + ocp_reg_write(tp, 0xd06a,
1927 + (swap_a & ~0x7ff) | (swap_b & 0x7ff));
1928 + data |= 0x18; /* p3 */
1929 + ocp_reg_write(tp, 0xd068, data);
1930 + ocp_reg_write(tp, 0xd06a,
1931 + (swap_b & ~0x7ff) | (swap_a & 0x7ff));
1932 + data &= ~0x18;
1933 + data |= 0x08; /* p1 */
1934 + ocp_reg_write(tp, 0xd068, data);
1935 + swap_a = ocp_reg_read(tp, 0xd06a);
1936 + data &= ~0x18;
1937 + data |= 0x10; /* p2 */
1938 + ocp_reg_write(tp, 0xd068, data);
1939 + swap_b = ocp_reg_read(tp, 0xd06a);
1940 + data &= ~0x18;
1941 + data |= 0x08; /* p1 */
1942 + ocp_reg_write(tp, 0xd068, data);
1943 + ocp_reg_write(tp, 0xd06a,
1944 + (swap_a & ~0x7ff) | (swap_b & 0x7ff));
1945 + data &= ~0x18;
1946 + data |= 0x10; /* p2 */
1947 + ocp_reg_write(tp, 0xd068, data);
1948 + ocp_reg_write(tp, 0xd06a,
1949 + (swap_b & ~0x7ff) | (swap_a & 0x7ff));
1950 + swap_a = ocp_reg_read(tp, 0xbd5a);
1951 + swap_b = ocp_reg_read(tp, 0xbd5c);
1952 + ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) |
1953 + ((swap_b & 0x1f) << 8) |
1954 + ((swap_b >> 8) & 0x1f));
1955 + ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) |
1956 + ((swap_a & 0x1f) << 8) |
1957 + ((swap_a >> 8) & 0x1f));
1958 + swap_a = ocp_reg_read(tp, 0xbc18);
1959 + swap_b = ocp_reg_read(tp, 0xbc1a);
1960 + ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) |
1961 + ((swap_b & 0x1f) << 8) |
1962 + ((swap_b >> 8) & 0x1f));
1963 + ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) |
1964 + ((swap_a & 0x1f) << 8) |
1965 + ((swap_a >> 8) & 0x1f));
1966 + }
1967 + break;
1968 + default:
1969 + break;
1970 + }
1971 +
1972 + rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
1973 +
1974 + data = ocp_reg_read(tp, 0xa428);
1975 + data &= ~BIT(9);
1976 + ocp_reg_write(tp, 0xa428, data);
1977 + data = ocp_reg_read(tp, 0xa5ea);
1978 + data &= ~BIT(0);
1979 + ocp_reg_write(tp, 0xa5ea, data);
1980 + tp->ups_info.lite_mode = 0;
1981 +
1982 + if (tp->eee_en)
1983 + rtl_eee_enable(tp, true);
1984 +
1985 + r8153_aldps_en(tp, true);
1986 + r8152b_enable_fc(tp);
1987 + r8153_u2p3en(tp, true);
1988 +
1989 + set_bit(PHY_RESET, &tp->flags);
1990 +}
1991 +
1992 +static void r8156b_hw_phy_cfg(struct r8152 *tp)
1993 +{
1994 + u32 ocp_data;
1995 + u16 data;
1996 +
1997 + switch (tp->version) {
1998 + case RTL_VER_12:
1999 + ocp_reg_write(tp, 0xbf86, 0x9000);
2000 + data = ocp_reg_read(tp, 0xc402);
2001 + data |= BIT(10);
2002 + ocp_reg_write(tp, 0xc402, data);
2003 + data &= ~BIT(10);
2004 + ocp_reg_write(tp, 0xc402, data);
2005 + ocp_reg_write(tp, 0xbd86, 0x1010);
2006 + ocp_reg_write(tp, 0xbd88, 0x1010);
2007 + data = ocp_reg_read(tp, 0xbd4e);
2008 + data &= ~(BIT(10) | BIT(11));
2009 + data |= BIT(11);
2010 + ocp_reg_write(tp, 0xbd4e, data);
2011 + data = ocp_reg_read(tp, 0xbf46);
2012 + data &= ~0xf00;
2013 + data |= 0x700;
2014 + ocp_reg_write(tp, 0xbf46, data);
2015 + break;
2016 + case RTL_VER_13:
2017 + case RTL_VER_15:
2018 + r8156b_wait_loading_flash(tp);
2019 + break;
2020 + default:
2021 + break;
2022 + }
2023 +
2024 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0);
2025 + if (ocp_data & PCUT_STATUS) {
2026 + ocp_data &= ~PCUT_STATUS;
2027 + ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data);
2028 + }
2029 +
2030 + data = r8153_phy_status(tp, 0);
2031 + switch (data) {
2032 + case PHY_STAT_EXT_INIT:
2033 + rtl8152_apply_firmware(tp, true);
2034 +
2035 + data = ocp_reg_read(tp, 0xa466);
2036 + data &= ~BIT(0);
2037 + ocp_reg_write(tp, 0xa466, data);
2038 +
2039 + data = ocp_reg_read(tp, 0xa468);
2040 + data &= ~(BIT(3) | BIT(1));
2041 + ocp_reg_write(tp, 0xa468, data);
2042 + break;
2043 + case PHY_STAT_LAN_ON:
2044 + case PHY_STAT_PWRDN:
2045 + default:
2046 + rtl8152_apply_firmware(tp, false);
2047 + break;
2048 + }
2049 +
2050 + data = r8152_mdio_read(tp, MII_BMCR);
2051 + if (data & BMCR_PDOWN) {
2052 + data &= ~BMCR_PDOWN;
2053 + r8152_mdio_write(tp, MII_BMCR, data);
2054 + }
2055 +
2056 + /* disable ALDPS before updating the PHY parameters */
2057 + r8153_aldps_en(tp, false);
2058 +
2059 + /* disable EEE before updating the PHY parameters */
2060 + rtl_eee_enable(tp, false);
2061 +
2062 + data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
2063 + WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
2064 +
2065 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR);
2066 + ocp_data |= PFM_PWM_SWITCH;
2067 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data);
2068 +
2069 + switch (tp->version) {
2070 + case RTL_VER_12:
2071 + data = ocp_reg_read(tp, 0xbc08);
2072 + data |= BIT(3) | BIT(2);
2073 + ocp_reg_write(tp, 0xbc08, data);
2074 +
2075 + data = sram_read(tp, 0x8fff);
2076 + data &= ~0xff00;
2077 + data |= 0x0400;
2078 + sram_write(tp, 0x8fff, data);
2079 +
2080 + data = ocp_reg_read(tp, 0xacda);
2081 + data |= 0xff00;
2082 + ocp_reg_write(tp, 0xacda, data);
2083 + data = ocp_reg_read(tp, 0xacde);
2084 + data |= 0xf000;
2085 + ocp_reg_write(tp, 0xacde, data);
2086 + ocp_reg_write(tp, 0xac8c, 0x0ffc);
2087 + ocp_reg_write(tp, 0xac46, 0xb7b4);
2088 + ocp_reg_write(tp, 0xac50, 0x0fbc);
2089 + ocp_reg_write(tp, 0xac3c, 0x9240);
2090 + ocp_reg_write(tp, 0xac4e, 0x0db4);
2091 + ocp_reg_write(tp, 0xacc6, 0x0707);
2092 + ocp_reg_write(tp, 0xacc8, 0xa0d3);
2093 + ocp_reg_write(tp, 0xad08, 0x0007);
2094 +
2095 + ocp_reg_write(tp, 0xb87c, 0x8560);
2096 + ocp_reg_write(tp, 0xb87e, 0x19cc);
2097 + ocp_reg_write(tp, 0xb87c, 0x8562);
2098 + ocp_reg_write(tp, 0xb87e, 0x19cc);
2099 + ocp_reg_write(tp, 0xb87c, 0x8564);
2100 + ocp_reg_write(tp, 0xb87e, 0x19cc);
2101 + ocp_reg_write(tp, 0xb87c, 0x8566);
2102 + ocp_reg_write(tp, 0xb87e, 0x147d);
2103 + ocp_reg_write(tp, 0xb87c, 0x8568);
2104 + ocp_reg_write(tp, 0xb87e, 0x147d);
2105 + ocp_reg_write(tp, 0xb87c, 0x856a);
2106 + ocp_reg_write(tp, 0xb87e, 0x147d);
2107 + ocp_reg_write(tp, 0xb87c, 0x8ffe);
2108 + ocp_reg_write(tp, 0xb87e, 0x0907);
2109 + ocp_reg_write(tp, 0xb87c, 0x80d6);
2110 + ocp_reg_write(tp, 0xb87e, 0x2801);
2111 + ocp_reg_write(tp, 0xb87c, 0x80f2);
2112 + ocp_reg_write(tp, 0xb87e, 0x2801);
2113 + ocp_reg_write(tp, 0xb87c, 0x80f4);
2114 + ocp_reg_write(tp, 0xb87e, 0x6077);
2115 + ocp_reg_write(tp, 0xb506, 0x01e7);
2116 +
2117 + ocp_reg_write(tp, 0xb87c, 0x8013);
2118 + ocp_reg_write(tp, 0xb87e, 0x0700);
2119 + ocp_reg_write(tp, 0xb87c, 0x8fb9);
2120 + ocp_reg_write(tp, 0xb87e, 0x2801);
2121 + ocp_reg_write(tp, 0xb87c, 0x8fba);
2122 + ocp_reg_write(tp, 0xb87e, 0x0100);
2123 + ocp_reg_write(tp, 0xb87c, 0x8fbc);
2124 + ocp_reg_write(tp, 0xb87e, 0x1900);
2125 + ocp_reg_write(tp, 0xb87c, 0x8fbe);
2126 + ocp_reg_write(tp, 0xb87e, 0xe100);
2127 + ocp_reg_write(tp, 0xb87c, 0x8fc0);
2128 + ocp_reg_write(tp, 0xb87e, 0x0800);
2129 + ocp_reg_write(tp, 0xb87c, 0x8fc2);
2130 + ocp_reg_write(tp, 0xb87e, 0xe500);
2131 + ocp_reg_write(tp, 0xb87c, 0x8fc4);
2132 + ocp_reg_write(tp, 0xb87e, 0x0f00);
2133 + ocp_reg_write(tp, 0xb87c, 0x8fc6);
2134 + ocp_reg_write(tp, 0xb87e, 0xf100);
2135 + ocp_reg_write(tp, 0xb87c, 0x8fc8);
2136 + ocp_reg_write(tp, 0xb87e, 0x0400);
2137 + ocp_reg_write(tp, 0xb87c, 0x8fca);
2138 + ocp_reg_write(tp, 0xb87e, 0xf300);
2139 + ocp_reg_write(tp, 0xb87c, 0x8fcc);
2140 + ocp_reg_write(tp, 0xb87e, 0xfd00);
2141 + ocp_reg_write(tp, 0xb87c, 0x8fce);
2142 + ocp_reg_write(tp, 0xb87e, 0xff00);
2143 + ocp_reg_write(tp, 0xb87c, 0x8fd0);
2144 + ocp_reg_write(tp, 0xb87e, 0xfb00);
2145 + ocp_reg_write(tp, 0xb87c, 0x8fd2);
2146 + ocp_reg_write(tp, 0xb87e, 0x0100);
2147 + ocp_reg_write(tp, 0xb87c, 0x8fd4);
2148 + ocp_reg_write(tp, 0xb87e, 0xf400);
2149 + ocp_reg_write(tp, 0xb87c, 0x8fd6);
2150 + ocp_reg_write(tp, 0xb87e, 0xff00);
2151 + ocp_reg_write(tp, 0xb87c, 0x8fd8);
2152 + ocp_reg_write(tp, 0xb87e, 0xf600);
2153 +
2154 + ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG);
2155 + ocp_data |= EN_XG_LIP | EN_G_LIP;
2156 + ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data);
2157 + ocp_reg_write(tp, 0xb87c, 0x813d);
2158 + ocp_reg_write(tp, 0xb87e, 0x390e);
2159 + ocp_reg_write(tp, 0xb87c, 0x814f);
2160 + ocp_reg_write(tp, 0xb87e, 0x790e);
2161 + ocp_reg_write(tp, 0xb87c, 0x80b0);
2162 + ocp_reg_write(tp, 0xb87e, 0x0f31);
2163 + data = ocp_reg_read(tp, 0xbf4c);
2164 + data |= BIT(1);
2165 + ocp_reg_write(tp, 0xbf4c, data);
2166 + data = ocp_reg_read(tp, 0xbcca);
2167 + data |= BIT(9) | BIT(8);
2168 + ocp_reg_write(tp, 0xbcca, data);
2169 + ocp_reg_write(tp, 0xb87c, 0x8141);
2170 + ocp_reg_write(tp, 0xb87e, 0x320e);
2171 + ocp_reg_write(tp, 0xb87c, 0x8153);
2172 + ocp_reg_write(tp, 0xb87e, 0x720e);
2173 + ocp_reg_write(tp, 0xb87c, 0x8529);
2174 + ocp_reg_write(tp, 0xb87e, 0x050e);
2175 + data = ocp_reg_read(tp, OCP_EEE_CFG);
2176 + data &= ~CTAP_SHORT_EN;
2177 + ocp_reg_write(tp, OCP_EEE_CFG, data);
2178 +
2179 + sram_write(tp, 0x816c, 0xc4a0);
2180 + sram_write(tp, 0x8170, 0xc4a0);
2181 + sram_write(tp, 0x8174, 0x04a0);
2182 + sram_write(tp, 0x8178, 0x04a0);
2183 + sram_write(tp, 0x817c, 0x0719);
2184 + sram_write(tp, 0x8ff4, 0x0400);
2185 + sram_write(tp, 0x8ff1, 0x0404);
2186 +
2187 + ocp_reg_write(tp, 0xbf4a, 0x001b);
2188 + ocp_reg_write(tp, 0xb87c, 0x8033);
2189 + ocp_reg_write(tp, 0xb87e, 0x7c13);
2190 + ocp_reg_write(tp, 0xb87c, 0x8037);
2191 + ocp_reg_write(tp, 0xb87e, 0x7c13);
2192 + ocp_reg_write(tp, 0xb87c, 0x803b);
2193 + ocp_reg_write(tp, 0xb87e, 0xfc32);
2194 + ocp_reg_write(tp, 0xb87c, 0x803f);
2195 + ocp_reg_write(tp, 0xb87e, 0x7c13);
2196 + ocp_reg_write(tp, 0xb87c, 0x8043);
2197 + ocp_reg_write(tp, 0xb87e, 0x7c13);
2198 + ocp_reg_write(tp, 0xb87c, 0x8047);
2199 + ocp_reg_write(tp, 0xb87e, 0x7c13);
2200 +
2201 + ocp_reg_write(tp, 0xb87c, 0x8145);
2202 + ocp_reg_write(tp, 0xb87e, 0x370e);
2203 + ocp_reg_write(tp, 0xb87c, 0x8157);
2204 + ocp_reg_write(tp, 0xb87e, 0x770e);
2205 + ocp_reg_write(tp, 0xb87c, 0x8169);
2206 + ocp_reg_write(tp, 0xb87e, 0x0d0a);
2207 + ocp_reg_write(tp, 0xb87c, 0x817b);
2208 + ocp_reg_write(tp, 0xb87e, 0x1d0a);
2209 +
2210 + data = sram_read(tp, 0x8217);
2211 + data &= ~0xff00;
2212 + data |= 0x5000;
2213 + sram_write(tp, 0x8217, data);
2214 + data = sram_read(tp, 0x821a);
2215 + data &= ~0xff00;
2216 + data |= 0x5000;
2217 + sram_write(tp, 0x821a, data);
2218 + sram_write(tp, 0x80da, 0x0403);
2219 + data = sram_read(tp, 0x80dc);
2220 + data &= ~0xff00;
2221 + data |= 0x1000;
2222 + sram_write(tp, 0x80dc, data);
2223 + sram_write(tp, 0x80b3, 0x0384);
2224 + sram_write(tp, 0x80b7, 0x2007);
2225 + data = sram_read(tp, 0x80ba);
2226 + data &= ~0xff00;
2227 + data |= 0x6c00;
2228 + sram_write(tp, 0x80ba, data);
2229 + sram_write(tp, 0x80b5, 0xf009);
2230 + data = sram_read(tp, 0x80bd);
2231 + data &= ~0xff00;
2232 + data |= 0x9f00;
2233 + sram_write(tp, 0x80bd, data);
2234 + sram_write(tp, 0x80c7, 0xf083);
2235 + sram_write(tp, 0x80dd, 0x03f0);
2236 + data = sram_read(tp, 0x80df);
2237 + data &= ~0xff00;
2238 + data |= 0x1000;
2239 + sram_write(tp, 0x80df, data);
2240 + sram_write(tp, 0x80cb, 0x2007);
2241 + data = sram_read(tp, 0x80ce);
2242 + data &= ~0xff00;
2243 + data |= 0x6c00;
2244 + sram_write(tp, 0x80ce, data);
2245 + sram_write(tp, 0x80c9, 0x8009);
2246 + data = sram_read(tp, 0x80d1);
2247 + data &= ~0xff00;
2248 + data |= 0x8000;
2249 + sram_write(tp, 0x80d1, data);
2250 + sram_write(tp, 0x80a3, 0x200a);
2251 + sram_write(tp, 0x80a5, 0xf0ad);
2252 + sram_write(tp, 0x809f, 0x6073);
2253 + sram_write(tp, 0x80a1, 0x000b);
2254 + data = sram_read(tp, 0x80a9);
2255 + data &= ~0xff00;
2256 + data |= 0xc000;
2257 + sram_write(tp, 0x80a9, data);
2258 +
2259 + if (rtl_phy_patch_request(tp, true, true))
2260 + return;
2261 +
2262 + data = ocp_reg_read(tp, 0xb896);
2263 + data &= ~BIT(0);
2264 + ocp_reg_write(tp, 0xb896, data);
2265 + data = ocp_reg_read(tp, 0xb892);
2266 + data &= ~0xff00;
2267 + ocp_reg_write(tp, 0xb892, data);
2268 + ocp_reg_write(tp, 0xb88e, 0xc23e);
2269 + ocp_reg_write(tp, 0xb890, 0x0000);
2270 + ocp_reg_write(tp, 0xb88e, 0xc240);
2271 + ocp_reg_write(tp, 0xb890, 0x0103);
2272 + ocp_reg_write(tp, 0xb88e, 0xc242);
2273 + ocp_reg_write(tp, 0xb890, 0x0507);
2274 + ocp_reg_write(tp, 0xb88e, 0xc244);
2275 + ocp_reg_write(tp, 0xb890, 0x090b);
2276 + ocp_reg_write(tp, 0xb88e, 0xc246);
2277 + ocp_reg_write(tp, 0xb890, 0x0c0e);
2278 + ocp_reg_write(tp, 0xb88e, 0xc248);
2279 + ocp_reg_write(tp, 0xb890, 0x1012);
2280 + ocp_reg_write(tp, 0xb88e, 0xc24a);
2281 + ocp_reg_write(tp, 0xb890, 0x1416);
2282 + data = ocp_reg_read(tp, 0xb896);
2283 + data |= BIT(0);
2284 + ocp_reg_write(tp, 0xb896, data);
2285 +
2286 + rtl_phy_patch_request(tp, false, true);
2287 +
2288 + data = ocp_reg_read(tp, 0xa86a);
2289 + data |= BIT(0);
2290 + ocp_reg_write(tp, 0xa86a, data);
2291 + data = ocp_reg_read(tp, 0xa6f0);
2292 + data |= BIT(0);
2293 + ocp_reg_write(tp, 0xa6f0, data);
2294 +
2295 + ocp_reg_write(tp, 0xbfa0, 0xd70d);
2296 + ocp_reg_write(tp, 0xbfa2, 0x4100);
2297 + ocp_reg_write(tp, 0xbfa4, 0xe868);
2298 + ocp_reg_write(tp, 0xbfa6, 0xdc59);
2299 + ocp_reg_write(tp, 0xb54c, 0x3c18);
2300 + data = ocp_reg_read(tp, 0xbfa4);
2301 + data &= ~BIT(5);
2302 + ocp_reg_write(tp, 0xbfa4, data);
2303 + data = sram_read(tp, 0x817d);
2304 + data |= BIT(12);
2305 + sram_write(tp, 0x817d, data);
2306 + break;
2307 + case RTL_VER_13:
2308 + /* 2.5G INRX */
2309 + data = ocp_reg_read(tp, 0xac46);
2310 + data &= ~0x00f0;
2311 + data |= 0x0090;
2312 + ocp_reg_write(tp, 0xac46, data);
2313 + data = ocp_reg_read(tp, 0xad30);
2314 + data &= ~0x0003;
2315 + data |= 0x0001;
2316 + ocp_reg_write(tp, 0xad30, data);
2317 + fallthrough;
2318 + case RTL_VER_15:
2319 + /* EEE parameter */
2320 + ocp_reg_write(tp, 0xb87c, 0x80f5);
2321 + ocp_reg_write(tp, 0xb87e, 0x760e);
2322 + ocp_reg_write(tp, 0xb87c, 0x8107);
2323 + ocp_reg_write(tp, 0xb87e, 0x360e);
2324 + ocp_reg_write(tp, 0xb87c, 0x8551);
2325 + data = ocp_reg_read(tp, 0xb87e);
2326 + data &= ~0xff00;
2327 + data |= 0x0800;
2328 + ocp_reg_write(tp, 0xb87e, data);
2329 +
2330 + /* ADC_PGA parameter */
2331 + data = ocp_reg_read(tp, 0xbf00);
2332 + data &= ~0xe000;
2333 + data |= 0xa000;
2334 + ocp_reg_write(tp, 0xbf00, data);
2335 + data = ocp_reg_read(tp, 0xbf46);
2336 + data &= ~0x0f00;
2337 + data |= 0x0300;
2338 + ocp_reg_write(tp, 0xbf46, data);
2339 +
2340 + /* Green Table-PGA, 1G full viterbi */
2341 + sram_write(tp, 0x8044, 0x2417);
2342 + sram_write(tp, 0x804a, 0x2417);
2343 + sram_write(tp, 0x8050, 0x2417);
2344 + sram_write(tp, 0x8056, 0x2417);
2345 + sram_write(tp, 0x805c, 0x2417);
2346 + sram_write(tp, 0x8062, 0x2417);
2347 + sram_write(tp, 0x8068, 0x2417);
2348 + sram_write(tp, 0x806e, 0x2417);
2349 + sram_write(tp, 0x8074, 0x2417);
2350 + sram_write(tp, 0x807a, 0x2417);
2351 +
2352 + /* XG PLL */
2353 + data = ocp_reg_read(tp, 0xbf84);
2354 + data &= ~0xe000;
2355 + data |= 0xa000;
2356 + ocp_reg_write(tp, 0xbf84, data);
2357 + break;
2358 + default:
2359 + break;
2360 + }
2361 +
2362 + if (rtl_phy_patch_request(tp, true, true))
2363 + return;
2364 +
2365 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4);
2366 + ocp_data |= EEE_SPDWN_EN;
2367 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data);
2368 +
2369 + data = ocp_reg_read(tp, OCP_DOWN_SPEED);
2370 + data &= ~(EN_EEE_100 | EN_EEE_1000);
2371 + data |= EN_10M_CLKDIV;
2372 + ocp_reg_write(tp, OCP_DOWN_SPEED, data);
2373 + tp->ups_info._10m_ckdiv = true;
2374 + tp->ups_info.eee_plloff_100 = false;
2375 + tp->ups_info.eee_plloff_giga = false;
2376 +
2377 + data = ocp_reg_read(tp, OCP_POWER_CFG);
2378 + data &= ~EEE_CLKDIV_EN;
2379 + ocp_reg_write(tp, OCP_POWER_CFG, data);
2380 + tp->ups_info.eee_ckdiv = false;
2381 +
2382 + rtl_phy_patch_request(tp, false, true);
2383 +
2384 + rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags));
2385 +
2386 + data = ocp_reg_read(tp, 0xa428);
2387 + data &= ~BIT(9);
2388 + ocp_reg_write(tp, 0xa428, data);
2389 + data = ocp_reg_read(tp, 0xa5ea);
2390 + data &= ~BIT(0);
2391 + ocp_reg_write(tp, 0xa5ea, data);
2392 + tp->ups_info.lite_mode = 0;
2393 +
2394 + if (tp->eee_en)
2395 + rtl_eee_enable(tp, true);
2396 +
2397 + r8153_aldps_en(tp, true);
2398 + r8152b_enable_fc(tp);
2399 + r8153_u2p3en(tp, true);
2400 +
2401 + set_bit(PHY_RESET, &tp->flags);
2402 +}
2403 +
2404 +static void r8156_init(struct r8152 *tp)
2405 +{
2406 + u32 ocp_data;
2407 + u16 data;
2408 + int i;
2409 +
2410 + if (test_bit(RTL8152_UNPLUG, &tp->flags))
2411 + return;
2412 +
2413 + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
2414 + ocp_data &= ~EN_ALL_SPEED;
2415 + ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
2416 +
2417 + ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
2418 +
2419 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
2420 + ocp_data |= BYPASS_MAC_RESET;
2421 + ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
2422 +
2423 + r8153b_u1u2en(tp, false);
2424 +
2425 + for (i = 0; i < 500; i++) {
2426 + if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
2427 + AUTOLOAD_DONE)
2428 + break;
2429 +
2430 + msleep(20);
2431 + if (test_bit(RTL8152_UNPLUG, &tp->flags))
2432 + return;
2433 + }
2434 +
2435 + data = r8153_phy_status(tp, 0);
2436 + if (data == PHY_STAT_EXT_INIT) {
2437 + data = ocp_reg_read(tp, 0xa468);
2438 + data &= ~(BIT(3) | BIT(1));
2439 + ocp_reg_write(tp, 0xa468, data);
2440 + }
2441 +
2442 + data = r8152_mdio_read(tp, MII_BMCR);
2443 + if (data & BMCR_PDOWN) {
2444 + data &= ~BMCR_PDOWN;
2445 + r8152_mdio_write(tp, MII_BMCR, data);
2446 + }
2447 +
2448 + data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
2449 + WARN_ON_ONCE(data != PHY_STAT_LAN_ON);
2450 +
2451 + r8153_u2p3en(tp, false);
2452 +
2453 + /* MSC timer = 0xfff * 8ms = 32760 ms */
2454 + ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
2455 +
2456 + /* U1/U2/L1 idle timer. 500 us */
2457 + ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
2458 +
2459 + r8153b_power_cut_en(tp, false);
2460 + r8156_ups_en(tp, false);
2461 + r8153_queue_wake(tp, false);
2462 + rtl_runtime_suspend_enable(tp, false);
2463 +
2464 + if (tp->udev->speed >= USB_SPEED_SUPER)
2465 + r8153b_u1u2en(tp, true);
2466 +
2467 + usb_enable_lpm(tp->udev);
2468 +
2469 + r8156_mac_clk_spd(tp, true);
2470 +
2471 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
2472 + ocp_data &= ~PLA_MCU_SPDWN_EN;
2473 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
2474 +
2475 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
2476 + if (rtl8152_get_speed(tp) & LINK_STATUS)
2477 + ocp_data |= CUR_LINK_OK;
2478 + else
2479 + ocp_data &= ~CUR_LINK_OK;
2480 + ocp_data |= POLL_LINK_CHG;
2481 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
2482 +
2483 + set_bit(GREEN_ETHERNET, &tp->flags);
2484 +
2485 + /* rx aggregation */
2486 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2487 + ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
2488 + ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2489 +
2490 + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG);
2491 + ocp_data |= ACT_ODMA;
2492 + ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data);
2493 +
2494 + rtl_tally_reset(tp);
2495 +
2496 + tp->coalesce = 15000; /* 15 us */
2497 +}
2498 +
2499 +static void r8156b_init(struct r8152 *tp)
2500 +{
2501 + u32 ocp_data;
2502 + u16 data;
2503 + int i;
2504 +
2505 + if (test_bit(RTL8152_UNPLUG, &tp->flags))
2506 + return;
2507 +
2508 + ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP);
2509 + ocp_data &= ~EN_ALL_SPEED;
2510 + ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data);
2511 +
2512 + ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0);
2513 +
2514 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION);
2515 + ocp_data |= BYPASS_MAC_RESET;
2516 + ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data);
2517 +
2518 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL);
2519 + ocp_data |= RX_DETECT8;
2520 + ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data);
2521 +
2522 + r8153b_u1u2en(tp, false);
2523 +
2524 + switch (tp->version) {
2525 + case RTL_VER_13:
2526 + case RTL_VER_15:
2527 + r8156b_wait_loading_flash(tp);
2528 + break;
2529 + default:
2530 + break;
2531 + }
2532 +
2533 + for (i = 0; i < 500; i++) {
2534 + if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) &
2535 + AUTOLOAD_DONE)
2536 + break;
2537 +
2538 + msleep(20);
2539 + if (test_bit(RTL8152_UNPLUG, &tp->flags))
2540 + return;
2541 + }
2542 +
2543 + data = r8153_phy_status(tp, 0);
2544 + if (data == PHY_STAT_EXT_INIT) {
2545 + data = ocp_reg_read(tp, 0xa468);
2546 + data &= ~(BIT(3) | BIT(1));
2547 + ocp_reg_write(tp, 0xa468, data);
2548 +
2549 + data = ocp_reg_read(tp, 0xa466);
2550 + data &= ~BIT(0);
2551 + ocp_reg_write(tp, 0xa466, data);
2552 + }
2553 +
2554 + data = r8152_mdio_read(tp, MII_BMCR);
2555 + if (data & BMCR_PDOWN) {
2556 + data &= ~BMCR_PDOWN;
2557 + r8152_mdio_write(tp, MII_BMCR, data);
2558 + }
2559 +
2560 + data = r8153_phy_status(tp, PHY_STAT_LAN_ON);
2561 +
2562 + r8153_u2p3en(tp, false);
2563 +
2564 + /* MSC timer = 0xfff * 8ms = 32760 ms */
2565 + ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff);
2566 +
2567 + /* U1/U2/L1 idle timer. 500 us */
2568 + ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500);
2569 +
2570 + r8153b_power_cut_en(tp, false);
2571 + r8156_ups_en(tp, false);
2572 + r8153_queue_wake(tp, false);
2573 + rtl_runtime_suspend_enable(tp, false);
2574 +
2575 + if (tp->udev->speed >= USB_SPEED_SUPER)
2576 + r8153b_u1u2en(tp, true);
2577 +
2578 + usb_enable_lpm(tp->udev);
2579 +
2580 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR);
2581 + ocp_data &= ~SLOT_EN;
2582 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data);
2583 +
2584 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR);
2585 + ocp_data |= FLOW_CTRL_EN;
2586 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data);
2587 +
2588 + /* enable fc timer and set timer to 600 ms. */
2589 + ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER,
2590 + CTRL_TIMER_EN | (600 / 8));
2591 +
2592 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL);
2593 + if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN))
2594 + ocp_data |= FLOW_CTRL_PATCH_2;
2595 + ocp_data &= ~AUTO_SPEEDUP;
2596 + ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data);
2597 +
2598 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK);
2599 + ocp_data |= FC_PATCH_TASK;
2600 + ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data);
2601 +
2602 + r8156_mac_clk_spd(tp, true);
2603 +
2604 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3);
2605 + ocp_data &= ~PLA_MCU_SPDWN_EN;
2606 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data);
2607 +
2608 + ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS);
2609 + if (rtl8152_get_speed(tp) & LINK_STATUS)
2610 + ocp_data |= CUR_LINK_OK;
2611 + else
2612 + ocp_data &= ~CUR_LINK_OK;
2613 + ocp_data |= POLL_LINK_CHG;
2614 + ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data);
2615 +
2616 + set_bit(GREEN_ETHERNET, &tp->flags);
2617 +
2618 + /* rx aggregation */
2619 + ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL);
2620 + ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN);
2621 + ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data);
2622 +
2623 + rtl_tally_reset(tp);
2624 +
2625 + tp->coalesce = 15000; /* 15 us */
2626 +}
2627 +
2628 static int rtl8152_pre_reset(struct usb_interface *intf)
2629 {
2630 struct r8152 *tp = usb_get_intfdata(intf);
2631 @@ -5994,6 +7926,22 @@ int rtl8152_get_link_ksettings(struct ne
2632
2633 mii_ethtool_get_link_ksettings(&tp->mii, cmd);
2634
2635 + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
2636 + cmd->link_modes.supported, tp->support_2500full);
2637 +
2638 + if (tp->support_2500full) {
2639 + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
2640 + cmd->link_modes.advertising,
2641 + ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G);
2642 +
2643 + linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
2644 + cmd->link_modes.lp_advertising,
2645 + ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G);
2646 +
2647 + if (is_speed_2500(rtl8152_get_speed(tp)))
2648 + cmd->base.speed = SPEED_2500;
2649 + }
2650 +
2651 mutex_unlock(&tp->control);
2652
2653 usb_autopm_put_interface(tp->intf);
2654 @@ -6037,6 +7985,10 @@ static int rtl8152_set_link_ksettings(st
2655 cmd->link_modes.advertising))
2656 advertising |= RTL_ADVERTISED_1000_FULL;
2657
2658 + if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT,
2659 + cmd->link_modes.advertising))
2660 + advertising |= RTL_ADVERTISED_2500_FULL;
2661 +
2662 mutex_lock(&tp->control);
2663
2664 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed,
2665 @@ -6626,6 +8578,67 @@ static int rtl_ops_init(struct r8152 *tp
2666 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
2667 break;
2668
2669 + case RTL_VER_11:
2670 + tp->eee_en = true;
2671 + tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
2672 + fallthrough;
2673 + case RTL_VER_10:
2674 + ops->init = r8156_init;
2675 + ops->enable = rtl8156_enable;
2676 + ops->disable = rtl8153_disable;
2677 + ops->up = rtl8156_up;
2678 + ops->down = rtl8156_down;
2679 + ops->unload = rtl8153_unload;
2680 + ops->eee_get = r8153_get_eee;
2681 + ops->eee_set = r8152_set_eee;
2682 + ops->in_nway = rtl8153_in_nway;
2683 + ops->hw_phy_cfg = r8156_hw_phy_cfg;
2684 + ops->autosuspend_en = rtl8156_runtime_enable;
2685 + ops->change_mtu = rtl8156_change_mtu;
2686 + tp->rx_buf_sz = 48 * 1024;
2687 + tp->support_2500full = 1;
2688 + break;
2689 +
2690 + case RTL_VER_12:
2691 + case RTL_VER_13:
2692 + tp->support_2500full = 1;
2693 + fallthrough;
2694 + case RTL_VER_15:
2695 + tp->eee_en = true;
2696 + tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
2697 + ops->init = r8156b_init;
2698 + ops->enable = rtl8156b_enable;
2699 + ops->disable = rtl8153_disable;
2700 + ops->up = rtl8156_up;
2701 + ops->down = rtl8156_down;
2702 + ops->unload = rtl8153_unload;
2703 + ops->eee_get = r8153_get_eee;
2704 + ops->eee_set = r8152_set_eee;
2705 + ops->in_nway = rtl8153_in_nway;
2706 + ops->hw_phy_cfg = r8156b_hw_phy_cfg;
2707 + ops->autosuspend_en = rtl8156_runtime_enable;
2708 + ops->change_mtu = rtl8156_change_mtu;
2709 + tp->rx_buf_sz = 48 * 1024;
2710 + break;
2711 +
2712 + case RTL_VER_14:
2713 + ops->init = r8153c_init;
2714 + ops->enable = rtl8153_enable;
2715 + ops->disable = rtl8153_disable;
2716 + ops->up = rtl8153c_up;
2717 + ops->down = rtl8153b_down;
2718 + ops->unload = rtl8153_unload;
2719 + ops->eee_get = r8153_get_eee;
2720 + ops->eee_set = r8152_set_eee;
2721 + ops->in_nway = rtl8153_in_nway;
2722 + ops->hw_phy_cfg = r8153c_hw_phy_cfg;
2723 + ops->autosuspend_en = rtl8153c_runtime_enable;
2724 + ops->change_mtu = rtl8153c_change_mtu;
2725 + tp->rx_buf_sz = 32 * 1024;
2726 + tp->eee_en = true;
2727 + tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX;
2728 + break;
2729 +
2730 default:
2731 ret = -ENODEV;
2732 dev_err(&tp->intf->dev, "Unknown Device\n");
2733 @@ -6639,11 +8652,13 @@ static int rtl_ops_init(struct r8152 *tp
2734 #define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw"
2735 #define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw"
2736 #define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw"
2737 +#define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw"
2738
2739 MODULE_FIRMWARE(FIRMWARE_8153A_2);
2740 MODULE_FIRMWARE(FIRMWARE_8153A_3);
2741 MODULE_FIRMWARE(FIRMWARE_8153A_4);
2742 MODULE_FIRMWARE(FIRMWARE_8153B_2);
2743 +MODULE_FIRMWARE(FIRMWARE_8153C_1);
2744
2745 static int rtl_fw_init(struct r8152 *tp)
2746 {
2747 @@ -6669,6 +8684,11 @@ static int rtl_fw_init(struct r8152 *tp)
2748 rtl_fw->pre_fw = r8153b_pre_firmware_1;
2749 rtl_fw->post_fw = r8153b_post_firmware_1;
2750 break;
2751 + case RTL_VER_14:
2752 + rtl_fw->fw_name = FIRMWARE_8153C_1;
2753 + rtl_fw->pre_fw = r8153b_pre_firmware_1;
2754 + rtl_fw->post_fw = r8153c_post_firmware_1;
2755 + break;
2756 default:
2757 break;
2758 }
2759 @@ -6724,6 +8744,27 @@ u8 rtl8152_get_version(struct usb_interf
2760 case 0x6010:
2761 version = RTL_VER_09;
2762 break;
2763 + case 0x7010:
2764 + version = RTL_TEST_01;
2765 + break;
2766 + case 0x7020:
2767 + version = RTL_VER_10;
2768 + break;
2769 + case 0x7030:
2770 + version = RTL_VER_11;
2771 + break;
2772 + case 0x7400:
2773 + version = RTL_VER_12;
2774 + break;
2775 + case 0x7410:
2776 + version = RTL_VER_13;
2777 + break;
2778 + case 0x6400:
2779 + version = RTL_VER_14;
2780 + break;
2781 + case 0x7420:
2782 + version = RTL_VER_15;
2783 + break;
2784 default:
2785 version = RTL_VER_UNKNOWN;
2786 dev_info(&intf->dev, "Unknown version 0x%04x\n", ocp_data);
2787 @@ -6836,12 +8877,29 @@ static int rtl8152_probe(struct usb_inte
2788 /* MTU range: 68 - 1500 or 9194 */
2789 netdev->min_mtu = ETH_MIN_MTU;
2790 switch (tp->version) {
2791 + case RTL_VER_03:
2792 + case RTL_VER_04:
2793 + case RTL_VER_05:
2794 + case RTL_VER_06:
2795 + case RTL_VER_08:
2796 + case RTL_VER_09:
2797 + case RTL_VER_14:
2798 + netdev->max_mtu = size_to_mtu(9 * 1024);
2799 + break;
2800 + case RTL_VER_10:
2801 + case RTL_VER_11:
2802 + netdev->max_mtu = size_to_mtu(15 * 1024);
2803 + break;
2804 + case RTL_VER_12:
2805 + case RTL_VER_13:
2806 + case RTL_VER_15:
2807 + netdev->max_mtu = size_to_mtu(16 * 1024);
2808 + break;
2809 case RTL_VER_01:
2810 case RTL_VER_02:
2811 - netdev->max_mtu = ETH_DATA_LEN;
2812 - break;
2813 + case RTL_VER_07:
2814 default:
2815 - netdev->max_mtu = size_to_mtu(9 * 1024);
2816 + netdev->max_mtu = ETH_DATA_LEN;
2817 break;
2818 }
2819
2820 @@ -6857,7 +8915,13 @@ static int rtl8152_probe(struct usb_inte
2821 tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL |
2822 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL;
2823 if (tp->mii.supports_gmii) {
2824 - tp->speed = SPEED_1000;
2825 + if (tp->support_2500full &&
2826 + tp->udev->speed >= USB_SPEED_SUPER) {
2827 + tp->speed = SPEED_2500;
2828 + tp->advertising |= RTL_ADVERTISED_2500_FULL;
2829 + } else {
2830 + tp->speed = SPEED_1000;
2831 + }
2832 tp->advertising |= RTL_ADVERTISED_1000_FULL;
2833 }
2834 tp->duplex = DUPLEX_FULL;
2835 @@ -6881,7 +8945,11 @@ static int rtl8152_probe(struct usb_inte
2836 set_ethernet_addr(tp);
2837
2838 usb_set_intfdata(intf, tp);
2839 - netif_napi_add(netdev, &tp->napi, r8152_poll, RTL8152_NAPI_WEIGHT);
2840 +
2841 + if (tp->support_2500full)
2842 + netif_napi_add(netdev, &tp->napi, r8152_poll, 256);
2843 + else
2844 + netif_napi_add(netdev, &tp->napi, r8152_poll, 64);
2845
2846 ret = register_netdev(netdev);
2847 if (ret != 0) {
2848 @@ -6917,7 +8985,8 @@ static void rtl8152_disconnect(struct us
2849 unregister_netdev(tp->netdev);
2850 tasklet_kill(&tp->tx_tl);
2851 cancel_delayed_work_sync(&tp->hw_phy_work);
2852 - tp->rtl_ops.unload(tp);
2853 + if (tp->rtl_ops.unload)
2854 + tp->rtl_ops.unload(tp);
2855 rtl8152_release_firmware(tp);
2856 free_netdev(tp->netdev);
2857 }
2858 @@ -6937,13 +9006,28 @@ static void rtl8152_disconnect(struct us
2859 .idProduct = (prod), \
2860 .bInterfaceClass = USB_CLASS_COMM, \
2861 .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, \
2862 + .bInterfaceProtocol = USB_CDC_PROTO_NONE \
2863 +}, \
2864 +{ \
2865 + .match_flags = USB_DEVICE_ID_MATCH_INT_INFO | \
2866 + USB_DEVICE_ID_MATCH_DEVICE, \
2867 + .idVendor = (vend), \
2868 + .idProduct = (prod), \
2869 + .bInterfaceClass = USB_CLASS_COMM, \
2870 + .bInterfaceSubClass = USB_CDC_SUBCLASS_NCM, \
2871 .bInterfaceProtocol = USB_CDC_PROTO_NONE
2872
2873 /* table of devices that work with this driver */
2874 static const struct usb_device_id rtl8152_table[] = {
2875 + /* Realtek */
2876 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8050)},
2877 + {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8053)},
2878 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8152)},
2879 {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8153)},
2880 + {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8155)},
2881 + {REALTEK_USB_DEVICE(VENDOR_ID_REALTEK, 0x8156)},
2882 +
2883 + /* Microsoft */
2884 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab)},
2885 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6)},
2886 {REALTEK_USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927)},
Kevin D-Bs staging tree