target/linux/realtek/dts-5.10/rtl8382_apresia_aplgs120gtss.dts

   1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
   2
   3 #include "rtl838x.dtsi"
   4
   5 #include <dt-bindings/input/input.h>
   6 #include <dt-bindings/gpio/gpio.h>
   7 #include <dt-bindings/leds/common.h>
   8
   9 / {
  10         compatible = "apresia,aplgs120gtss", "realtek,rtl8382-soc";
  11         model = "APRESIA ApresiaLightGS120GT-SS";
  12
  13         aliases {
  14                 led-boot = &led_power;
  15                 led-failsafe = &led_power;
  16                 led-running = &led_power;
  17                 led-upgrade = &led_power;
  18         };
  19
  20         memory@0 {
  21                 device_type = "memory";
  22                 reg = <0x0 0x10000000>;
  23         };
  24
  25         leds {
  26                 compatible = "gpio-leds";
  27
  28                 led_power: led-0 {
  29                         label = "green:pwr";
  30                         gpios = <&gpio0 0 GPIO_ACTIVE_LOW>;
  31                         color = <LED_COLOR_ID_GREEN>;
  32                         function = LED_FUNCTION_POWER;
  33                 };
  34
  35                 led-1 {
  36                         label = "red:loop";
  37                         gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
  38                         color = <LED_COLOR_ID_RED>;
  39                         function = LED_FUNCTION_FAULT;
  40                 };
  41
  42                 /* LED chip is soldered, but no hole on the case */
  43                 led-2 {
  44                         label = "green:unused";
  45                         gpios = <&gpio1 36 GPIO_ACTIVE_LOW>;
  46                         color = <LED_COLOR_ID_GREEN>;
  47                 };
  48         };
  49
  50         keys {
  51                 compatible = "gpio-keys-polled";
  52                 poll-interval = <20>;
  53
  54                 reset {
  55                         label = "reset";
  56                         gpios = <&gpio1 33 GPIO_ACTIVE_LOW>;
  57                         linux,code = <KEY_RESTART>;
  58                 };
  59         };
  60
  61         gpio-restart {
  62                 compatible = "gpio-restart";
  63                 gpios = <&gpio1 34 GPIO_ACTIVE_LOW>;
  64                 open-source;
  65         };
  66
  67         gpio1: rtl8231-gpio {
  68                 compatible = "realtek,rtl8231-gpio";
  69                 #gpio-cells = <2>;
  70                 gpio-controller;
  71                 indirect-access-bus-id = <0>;
  72         };
  73
  74         i2c0: i2c-gpio-0 {
  75                 compatible = "i2c-gpio";
  76                 sda-gpios = <&gpio1 1 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  77                 scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  78                 i2c-gpio,delay-us = <2>;
  79                 #address-cells = <1>;
  80                 #size-cells = <0>;
  81         };
  82
  83         i2c1: i2c-gpio-1 {
  84                 compatible = "i2c-gpio";
  85                 sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  86                 scl-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  87                 i2c-gpio,delay-us = <2>;
  88                 #address-cells = <1>;
  89                 #size-cells = <0>;
  90         };
  91
  92         i2c2: i2c-gpio-2 {
  93                 compatible = "i2c-gpio";
  94                 sda-gpios = <&gpio1 11 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  95                 scl-gpios = <&gpio1 12 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
  96                 i2c-gpio,delay-us = <2>;
  97                 #address-cells = <1>;
  98                 #size-cells = <0>;
  99         };
 100
 101         i2c3: i2c-gpio-3 {
 102                 compatible = "i2c-gpio";
 103                 sda-gpios = <&gpio1 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 104                 scl-gpios = <&gpio1 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
 105                 i2c-gpio,delay-us = <2>;
 106                 #address-cells = <1>;
 107                 #size-cells = <0>;
 108         };
 109
 110         /* 4x TX-Disable lines are provided by RTL8214FC */
 111         sfp0: sfp-p17 {
 112                 compatible = "sff,sfp";
 113                 i2c-bus = <&i2c1>;
 114                 los-gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
 115                 mod-def0-gpio = <&gpio1 8 GPIO_ACTIVE_LOW>;
 116         };
 117
 118         sfp1: sfp-p18 {
 119                 compatible = "sff,sfp";
 120                 i2c-bus = <&i2c0>;
 121                 los-gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>;
 122                 mod-def0-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
 123         };
 124
 125         sfp2: sfp-p19 {
 126                 compatible = "sff,sfp";
 127                 i2c-bus = <&i2c3>;
 128                 los-gpio = <&gpio1 25 GPIO_ACTIVE_HIGH>;
 129                 mod-def0-gpio = <&gpio1 24 GPIO_ACTIVE_LOW>;
 130         };
 131
 132         sfp3: sfp-p20 {
 133                 compatible = "sff,sfp";
 134                 i2c-bus = <&i2c2>;
 135                 los-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
 136                 mod-def0-gpio = <&gpio1 13 GPIO_ACTIVE_LOW>;
 137         };
 138 };
 139
 140 &gpio0 {
 141         rtl8231_reset {
 142                 gpio-hog;
 143                 gpios = <1 GPIO_ACTIVE_HIGH>;
 144                 output-high;
 145                 line-name = "rtl8231-reset";
 146         };
 147 };
 148
 149 &spi0 {
 150         status = "okay";
 151
 152         flash@0 {
 153                 compatible = "jedec,spi-nor";
 154                 reg = <0>;
 155                 spi-max-frequency = <10000000>;
 156
 157                 partitions {
 158                         compatible = "fixed-partitions";
 159                         #address-cells = <1>;
 160                         #size-cells = <1>;
 161
 162                         partition@0 {
 163                                 label = "u-boot";
 164                                 reg = <0x0 0x80000>;
 165                                 read-only;
 166                         };
 167
 168                         partition@80000 {
 169                                 label = "u-boot-env";
 170                                 reg = <0x80000 0x40000>;
 171                         };
 172
 173                         partition@c0000 {
 174                                 label = "u-boot-env2";
 175                                 reg = <0xc0000 0x40000>;
 176                         };
 177
 178                         partition@100000 {
 179                                 compatible = "openwrt,uimage", "denx,uimage";
 180                                 label = "firmware";
 181                                 reg = <0x100000 0xe80000>;
 182                                 openwrt,ih-magic = <0x12345000>;
 183                         };
 184
 185                         partition@f80000 {
 186                                 label = "firmware2";
 187                                 reg = <0xf80000 0xe80000>;
 188                         };
 189
 190                         partition@1e00000 {
 191                                 label = "jffs2";
 192                                 reg = <0x1e00000 0x200000>;
 193                                 read-only;
 194                         };
 195                 };
 196         };
 197 };
 198
 199 &ethernet0 {
 200         mdio-bus {
 201                 compatible = "realtek,rtl838x-mdio";
 202                 regmap = <&ethernet0>;
 203                 #address-cells = <1>;
 204                 #size-cells = <0>;
 205
 206                 EXTERNAL_PHY(0)
 207                 EXTERNAL_PHY(1)
 208                 EXTERNAL_PHY(2)
 209                 EXTERNAL_PHY(3)
 210                 EXTERNAL_PHY(4)
 211                 EXTERNAL_PHY(5)
 212                 EXTERNAL_PHY(6)
 213                 EXTERNAL_PHY(7)
 214
 215                 INTERNAL_PHY(8)
 216                 INTERNAL_PHY(9)
 217                 INTERNAL_PHY(10)
 218                 INTERNAL_PHY(11)
 219                 INTERNAL_PHY(12)
 220                 INTERNAL_PHY(13)
 221                 INTERNAL_PHY(14)
 222                 INTERNAL_PHY(15)
 223
 224                 EXTERNAL_SFP_PHY_FULL(24, 0)
 225                 EXTERNAL_SFP_PHY_FULL(25, 1)
 226                 EXTERNAL_SFP_PHY_FULL(26, 2)
 227                 EXTERNAL_SFP_PHY_FULL(27, 3)
 228         };
 229 };
 230
 231 &switch0 {
 232         ports {
 233                 #address-cells = <1>;
 234                 #size-cells = <0>;
 235
 236                 SWITCH_PORT(0, 1, qsgmii)
 237                 SWITCH_PORT(1, 2, qsgmii)
 238                 SWITCH_PORT(2, 3, qsgmii)
 239                 SWITCH_PORT(3, 4, qsgmii)
 240                 SWITCH_PORT(4, 5, qsgmii)
 241                 SWITCH_PORT(5, 6, qsgmii)
 242                 SWITCH_PORT(6, 7, qsgmii)
 243                 SWITCH_PORT(7, 8, qsgmii)
 244
 245                 SWITCH_PORT(8, 9, internal)
 246                 SWITCH_PORT(9, 10, internal)
 247                 SWITCH_PORT(10, 11, internal)
 248                 SWITCH_PORT(11, 12, internal)
 249                 SWITCH_PORT(12, 13, internal)
 250                 SWITCH_PORT(13, 14, internal)
 251                 SWITCH_PORT(14, 15, internal)
 252                 SWITCH_PORT(15, 16, internal)
 253
 254                 SWITCH_PORT(24, 17, qsgmii)
 255                 SWITCH_PORT(25, 18, qsgmii)
 256                 SWITCH_PORT(26, 19, qsgmii)
 257                 SWITCH_PORT(27, 20, qsgmii)
 258
 259                 port@28 {
 260                         ethernet = <&ethernet0>;
 261                         reg = <28>;
 262                         phy-mode = "internal";
 263
 264                         fixed-link {
 265                                 speed = <1000>;
 266                                 full-duplex;
 267                         };
 268                 };
 269         };
 270 };