1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Realtek RTL838X SRAM clock setters
4 * Copyright (C) 2022 Markus Stockhausen <markus.stockhausen@gmx.de>
7 #include <dt-bindings/clock/rtl83xx-clk.h>
9 #include "clk-rtl83xx.h"
19 .globl rtcl_838x_dram_start
23 * Functions start here and should avoid access to normal memory. REMARK! Do not forget about
24 * stack pointer and dirty caches that might interfere.
27 .globl rtcl_838x_dram_set_rate
28 .ent rtcl_838x_dram_set_rate
29 rtcl_838x_dram_set_rate:
33 li rCTR, RTL_SW_CORE_BASE
34 addiu rGLB, rCTR, RTL838X_PLL_GLB_CTRL
36 beq $a0, rTMP, pre_cpu
38 beq $a0, rTMP, pre_mem
41 ori rSLP, $0, RTL838X_GLB_CTRL_LXB_PLL_READY_MASK
42 addiu rCTR, rCTR, RTL838X_PLL_LXB_CTRL0
44 ori rMSK, $0, RTL838X_GLB_CTRL_EN_LXB_PLL_MASK
46 /* simple 64K data cache flush to avoid unexpected memory access */
47 li rMSK, RTL_SRAM_BASE
53 bne rTMP, $0, pre_flush
56 ori rSLP, $0, RTL838X_GLB_CTRL_MEM_PLL_READY_MASK
57 addiu rCTR, rCTR, RTL838X_PLL_MEM_CTRL0
59 ori rMSK, $0, RTL838X_GLB_CTRL_EN_MEM_PLL_MASK
61 /* switch CPU to LXB clock */
62 ori rMSK, $0, RTL838X_GLB_CTRL_CPU_PLL_SC_MUX_MASK
70 ori rSLP, $0, RTL838X_GLB_CTRL_CPU_PLL_READY_MASK
71 addiu rCTR, rCTR, RTL838X_PLL_CPU_CTRL0
72 ori rMSK, $0, RTL838X_GLB_CTRL_EN_CPU_PLL_MASK
83 /* set new PLL values */
89 /* enable PLL (will reset it and clear ready status) */
98 /* wait for PLL to become ready */
102 bne rTMP, $0, wait_ready
105 /* branch to post processing */
106 ori rTMP, $0, CLK_CPU
107 beq $a0, rTMP, post_cpu
108 ori rTMP, $0, CLK_MEM
109 beq $a0, rTMP, post_mem
118 /* stabilize clock to avoid crash, empirically determined */
124 /* switch CPU to PLL clock */
125 ori rMSK, $0, RTL838X_GLB_CTRL_CPU_PLL_SC_MUX_MASK
134 #else /* !CONFIG_RTL838X */
141 .end rtcl_838x_dram_set_rate
144 * End marker. Do not delete.
146 .word RTL_SRAM_MARKER
147 .globl rtcl_838x_dram_size
149 .word .-rtcl_838x_dram_start