target/linux/realtek/files-5.10/drivers/clk/realtek/clk-rtl838x-sram.S

   1 /* SPDX-License-Identifier: GPL-2.0-only */
   2 /*
   3  * Realtek RTL838X SRAM clock setters
   4  * Copyright (C) 2022 Markus Stockhausen <markus.stockhausen@gmx.de>
   5  */
   6
   7 #include <dt-bindings/clock/rtl83xx-clk.h>
   8
   9 #include "clk-rtl83xx.h"
  10
  11 #define rGLB    $t0
  12 #define rCTR    $t1
  13 #define rMSK    $t2
  14 #define rSLP    $t3
  15 #define rTMP    $t4
  16
  17 .set    noreorder
  18
  19 .globl  rtcl_838x_dram_start
  20 rtcl_838x_dram_start:
  21
  22 /*
  23  * Functions start here and should avoid access to normal memory. REMARK! Do not forget about
  24  * stack pointer and dirty caches that might interfere.
  25  */
  26
  27 .globl  rtcl_838x_dram_set_rate
  28 .ent    rtcl_838x_dram_set_rate
  29 rtcl_838x_dram_set_rate:
  30
  31 #ifdef CONFIG_RTL838X
  32
  33         li      rCTR, RTL_SW_CORE_BASE
  34         addiu   rGLB, rCTR, RTL838X_PLL_GLB_CTRL
  35         ori     rTMP, $0, CLK_CPU
  36         beq     $a0, rTMP, pre_cpu
  37         ori     rTMP, $0, CLK_MEM
  38         beq     $a0, rTMP, pre_mem
  39         nop
  40 pre_lxb:
  41         ori     rSLP, $0, RTL838X_GLB_CTRL_LXB_PLL_READY_MASK
  42         addiu   rCTR, rCTR, RTL838X_PLL_LXB_CTRL0
  43         b       main_set
  44         ori     rMSK, $0, RTL838X_GLB_CTRL_EN_LXB_PLL_MASK
  45 pre_mem:
  46         /* simple 64K data cache flush to avoid unexpected memory access */
  47         li      rMSK, RTL_SRAM_BASE
  48         li      rTMP, 2048
  49 pre_flush:
  50         lw      $0, 0(rMSK)
  51         addiu   rMSK, rMSK, 32
  52         addiu   rTMP, rTMP, -1
  53         bne     rTMP, $0, pre_flush
  54         lw      $0, -4(rMSK)
  55
  56         ori     rSLP, $0, RTL838X_GLB_CTRL_MEM_PLL_READY_MASK
  57         addiu   rCTR, rCTR, RTL838X_PLL_MEM_CTRL0
  58         b       main_set
  59         ori     rMSK, $0, RTL838X_GLB_CTRL_EN_MEM_PLL_MASK
  60 pre_cpu:
  61         /* switch CPU to LXB clock */
  62         ori     rMSK, $0, RTL838X_GLB_CTRL_CPU_PLL_SC_MUX_MASK
  63         nor     rMSK, rMSK, $0
  64         sync
  65         lw      rTMP, 0(rGLB)
  66         and     rTMP, rTMP, rMSK
  67         sw      rTMP, 0(rGLB)
  68         sync
  69
  70         ori     rSLP, $0, RTL838X_GLB_CTRL_CPU_PLL_READY_MASK
  71         addiu   rCTR, rCTR, RTL838X_PLL_CPU_CTRL0
  72         ori     rMSK, $0, RTL838X_GLB_CTRL_EN_CPU_PLL_MASK
  73 main_set:
  74         /* disable PLL */
  75         nor     rMSK, rMSK, 0
  76         sync
  77         lw      rTMP, 0(rGLB)
  78         sync
  79         and     rTMP, rTMP, rMSK
  80         sync
  81         sw      rTMP, 0(rGLB)
  82
  83         /* set new PLL values */
  84         sync
  85         sw      $a1, 0(rCTR)
  86         sw      $a2, 4(rCTR)
  87         sync
  88
  89         /* enable PLL (will reset it and clear ready status) */
  90         nor     rMSK, rMSK, 0
  91         sync
  92         lw      rTMP, 0(rGLB)
  93         sync
  94         or      rTMP, rTMP, rMSK
  95         sync
  96         sw      rTMP, 0(rGLB)
  97
  98         /* wait for PLL to become ready */
  99 wait_ready:
 100         lw      rTMP, 0(rGLB)
 101         and     rTMP, rTMP, rSLP
 102         bne     rTMP, $0, wait_ready
 103         sync
 104
 105         /* branch to post processing */
 106         ori     rTMP, $0, CLK_CPU
 107         beq     $a0, rTMP, post_cpu
 108         ori     rTMP, $0, CLK_MEM
 109         beq     $a0, rTMP, post_mem
 110         nop
 111 post_lxb:
 112         jr      $ra
 113         nop
 114 post_mem:
 115         jr      $ra
 116         nop
 117 post_cpu:
 118         /* stabilize clock to avoid crash, empirically determined */
 119         ori     rSLP, $0, 0x3000
 120 wait_cpu:
 121         bnez    rSLP, wait_cpu
 122         addiu   rSLP, rSLP, -1
 123
 124         /* switch CPU to PLL clock */
 125         ori     rMSK, $0, RTL838X_GLB_CTRL_CPU_PLL_SC_MUX_MASK
 126         sync
 127         lw      rTMP, 0(rGLB)
 128         or      rTMP, rTMP, rMSK
 129         sw      rTMP, 0(rGLB)
 130         sync
 131         jr      $ra
 132         nop
 133
 134 #else /* !CONFIG_RTL838X */
 135
 136         jr      $ra
 137         nop
 138
 139 #endif
 140
 141 .end    rtcl_838x_dram_set_rate
 142
 143 /*
 144  * End marker. Do not delete.
 145  */
 146         .word RTL_SRAM_MARKER
 147 .globl  rtcl_838x_dram_size
 148 rtcl_838x_dram_size:
 149         .word .-rtcl_838x_dram_start
 150