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[openwrt/staging/ldir.git] / target / linux / realtek / files-5.10 / drivers / net / dsa / rtl83xx / rtl839x.c
1 // SPDX-License-Identifier: GPL-2.0-only
2
3 #include <asm/mach-rtl838x/mach-rtl83xx.h>
4 #include "rtl83xx.h"
5
6 #define RTL839X_VLAN_PORT_TAG_STS_UNTAG 0x0
7 #define RTL839X_VLAN_PORT_TAG_STS_TAGGED 0x1
8 #define RTL839X_VLAN_PORT_TAG_STS_PRIORITY_TAGGED 0x2
9
10 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_BASE 0x6828
11 /* port 0-52 */
12 #define RTL839X_VLAN_PORT_TAG_STS_CTRL(port) \
13 RTL839X_VLAN_PORT_TAG_STS_CTRL_BASE + (port << 2)
14 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK GENMASK(7,6)
15 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK GENMASK(5,4)
16 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_EGR_P_OTAG_KEEP_MASK GENMASK(3,3)
17 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_EGR_P_ITAG_KEEP_MASK GENMASK(2,2)
18 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_IGR_P_OTAG_KEEP_MASK GENMASK(1,1)
19 #define RTL839X_VLAN_PORT_TAG_STS_CTRL_IGR_P_ITAG_KEEP_MASK GENMASK(0,0)
20
21 extern struct mutex smi_lock;
22 extern struct rtl83xx_soc_info soc_info;
23
24 /* Definition of the RTL839X-specific template field IDs as used in the PIE */
25 enum template_field_id {
26 TEMPLATE_FIELD_SPMMASK = 0,
27 TEMPLATE_FIELD_SPM0 = 1, // Source portmask ports 0-15
28 TEMPLATE_FIELD_SPM1 = 2, // Source portmask ports 16-31
29 TEMPLATE_FIELD_SPM2 = 3, // Source portmask ports 32-47
30 TEMPLATE_FIELD_SPM3 = 4, // Source portmask ports 48-56
31 TEMPLATE_FIELD_DMAC0 = 5, // Destination MAC [15:0]
32 TEMPLATE_FIELD_DMAC1 = 6, // Destination MAC [31:16]
33 TEMPLATE_FIELD_DMAC2 = 7, // Destination MAC [47:32]
34 TEMPLATE_FIELD_SMAC0 = 8, // Source MAC [15:0]
35 TEMPLATE_FIELD_SMAC1 = 9, // Source MAC [31:16]
36 TEMPLATE_FIELD_SMAC2 = 10, // Source MAC [47:32]
37 TEMPLATE_FIELD_ETHERTYPE = 11, // Ethernet frame type field
38 // Field-ID 12 is not used
39 TEMPLATE_FIELD_OTAG = 13,
40 TEMPLATE_FIELD_ITAG = 14,
41 TEMPLATE_FIELD_SIP0 = 15,
42 TEMPLATE_FIELD_SIP1 = 16,
43 TEMPLATE_FIELD_DIP0 = 17,
44 TEMPLATE_FIELD_DIP1 = 18,
45 TEMPLATE_FIELD_IP_TOS_PROTO = 19,
46 TEMPLATE_FIELD_IP_FLAG = 20,
47 TEMPLATE_FIELD_L4_SPORT = 21,
48 TEMPLATE_FIELD_L4_DPORT = 22,
49 TEMPLATE_FIELD_L34_HEADER = 23,
50 TEMPLATE_FIELD_ICMP_IGMP = 24,
51 TEMPLATE_FIELD_VID_RANG0 = 25,
52 TEMPLATE_FIELD_VID_RANG1 = 26,
53 TEMPLATE_FIELD_L4_PORT_RANG = 27,
54 TEMPLATE_FIELD_FIELD_SELECTOR_VALID = 28,
55 TEMPLATE_FIELD_FIELD_SELECTOR_0 = 29,
56 TEMPLATE_FIELD_FIELD_SELECTOR_1 = 30,
57 TEMPLATE_FIELD_FIELD_SELECTOR_2 = 31,
58 TEMPLATE_FIELD_FIELD_SELECTOR_3 = 32,
59 TEMPLATE_FIELD_FIELD_SELECTOR_4 = 33,
60 TEMPLATE_FIELD_FIELD_SELECTOR_5 = 34,
61 TEMPLATE_FIELD_SIP2 = 35,
62 TEMPLATE_FIELD_SIP3 = 36,
63 TEMPLATE_FIELD_SIP4 = 37,
64 TEMPLATE_FIELD_SIP5 = 38,
65 TEMPLATE_FIELD_SIP6 = 39,
66 TEMPLATE_FIELD_SIP7 = 40,
67 TEMPLATE_FIELD_OLABEL = 41,
68 TEMPLATE_FIELD_ILABEL = 42,
69 TEMPLATE_FIELD_OILABEL = 43,
70 TEMPLATE_FIELD_DPMMASK = 44,
71 TEMPLATE_FIELD_DPM0 = 45,
72 TEMPLATE_FIELD_DPM1 = 46,
73 TEMPLATE_FIELD_DPM2 = 47,
74 TEMPLATE_FIELD_DPM3 = 48,
75 TEMPLATE_FIELD_L2DPM0 = 49,
76 TEMPLATE_FIELD_L2DPM1 = 50,
77 TEMPLATE_FIELD_L2DPM2 = 51,
78 TEMPLATE_FIELD_L2DPM3 = 52,
79 TEMPLATE_FIELD_IVLAN = 53,
80 TEMPLATE_FIELD_OVLAN = 54,
81 TEMPLATE_FIELD_FWD_VID = 55,
82 TEMPLATE_FIELD_DIP2 = 56,
83 TEMPLATE_FIELD_DIP3 = 57,
84 TEMPLATE_FIELD_DIP4 = 58,
85 TEMPLATE_FIELD_DIP5 = 59,
86 TEMPLATE_FIELD_DIP6 = 60,
87 TEMPLATE_FIELD_DIP7 = 61,
88 };
89
90 // Number of fixed templates predefined in the SoC
91 #define N_FIXED_TEMPLATES 5
92 static enum template_field_id fixed_templates[N_FIXED_TEMPLATES][N_FIXED_FIELDS] =
93 {
94 {
95 TEMPLATE_FIELD_SPM0, TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_ITAG,
96 TEMPLATE_FIELD_SMAC0, TEMPLATE_FIELD_SMAC1, TEMPLATE_FIELD_SMAC2,
97 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
98 TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
99 }, {
100 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0,
101 TEMPLATE_FIELD_DIP1,TEMPLATE_FIELD_IP_TOS_PROTO, TEMPLATE_FIELD_L4_SPORT,
102 TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_SPM0,
103 TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
104 }, {
105 TEMPLATE_FIELD_DMAC0, TEMPLATE_FIELD_DMAC1, TEMPLATE_FIELD_DMAC2,
106 TEMPLATE_FIELD_ITAG, TEMPLATE_FIELD_ETHERTYPE, TEMPLATE_FIELD_IP_TOS_PROTO,
107 TEMPLATE_FIELD_L4_DPORT, TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_SIP0,
108 TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1
109 }, {
110 TEMPLATE_FIELD_DIP0, TEMPLATE_FIELD_DIP1, TEMPLATE_FIELD_DIP2,
111 TEMPLATE_FIELD_DIP3, TEMPLATE_FIELD_DIP4, TEMPLATE_FIELD_DIP5,
112 TEMPLATE_FIELD_DIP6, TEMPLATE_FIELD_DIP7, TEMPLATE_FIELD_L4_DPORT,
113 TEMPLATE_FIELD_L4_SPORT, TEMPLATE_FIELD_ICMP_IGMP, TEMPLATE_FIELD_IP_TOS_PROTO
114 }, {
115 TEMPLATE_FIELD_SIP0, TEMPLATE_FIELD_SIP1, TEMPLATE_FIELD_SIP2,
116 TEMPLATE_FIELD_SIP3, TEMPLATE_FIELD_SIP4, TEMPLATE_FIELD_SIP5,
117 TEMPLATE_FIELD_SIP6, TEMPLATE_FIELD_SIP7, TEMPLATE_FIELD_SPM0,
118 TEMPLATE_FIELD_SPM1, TEMPLATE_FIELD_SPM2, TEMPLATE_FIELD_SPM3
119 },
120 };
121
122 void rtl839x_print_matrix(void)
123 {
124 volatile u64 *ptr9;
125 int i;
126
127 ptr9 = RTL838X_SW_BASE + RTL839X_PORT_ISO_CTRL(0);
128 for (i = 0; i < 52; i += 4)
129 pr_debug("> %16llx %16llx %16llx %16llx\n",
130 ptr9[i + 0], ptr9[i + 1], ptr9[i + 2], ptr9[i + 3]);
131 pr_debug("CPU_PORT> %16llx\n", ptr9[52]);
132 }
133
134 static inline int rtl839x_port_iso_ctrl(int p)
135 {
136 return RTL839X_PORT_ISO_CTRL(p);
137 }
138
139 static inline void rtl839x_exec_tbl0_cmd(u32 cmd)
140 {
141 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_0);
142 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_0) & BIT(16));
143 }
144
145 static inline void rtl839x_exec_tbl1_cmd(u32 cmd)
146 {
147 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_1);
148 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_1) & BIT(16));
149 }
150
151 inline void rtl839x_exec_tbl2_cmd(u32 cmd)
152 {
153 sw_w32(cmd, RTL839X_TBL_ACCESS_CTRL_2);
154 do { } while (sw_r32(RTL839X_TBL_ACCESS_CTRL_2) & (1 << 9));
155 }
156
157 static inline int rtl839x_tbl_access_data_0(int i)
158 {
159 return RTL839X_TBL_ACCESS_DATA_0(i);
160 }
161
162 static void rtl839x_vlan_tables_read(u32 vlan, struct rtl838x_vlan_info *info)
163 {
164 u32 u, v, w;
165 // Read VLAN table (0) via register 0
166 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0);
167
168 rtl_table_read(r, vlan);
169 u = sw_r32(rtl_table_data(r, 0));
170 v = sw_r32(rtl_table_data(r, 1));
171 w = sw_r32(rtl_table_data(r, 2));
172 rtl_table_release(r);
173
174 info->tagged_ports = u;
175 info->tagged_ports = (info->tagged_ports << 21) | ((v >> 11) & 0x1fffff);
176 info->profile_id = w >> 30 | ((v & 1) << 2);
177 info->hash_mc_fid = !!(w & BIT(2));
178 info->hash_uc_fid = !!(w & BIT(3));
179 info->fid = (v >> 3) & 0xff;
180
181 // Read UNTAG table (0) via table register 1
182 r = rtl_table_get(RTL8390_TBL_1, 0);
183 rtl_table_read(r, vlan);
184 u = sw_r32(rtl_table_data(r, 0));
185 v = sw_r32(rtl_table_data(r, 1));
186 rtl_table_release(r);
187
188 info->untagged_ports = u;
189 info->untagged_ports = (info->untagged_ports << 21) | ((v >> 11) & 0x1fffff);
190 }
191
192 static void rtl839x_vlan_set_tagged(u32 vlan, struct rtl838x_vlan_info *info)
193 {
194 u32 u, v, w;
195 // Access VLAN table (0) via register 0
196 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 0);
197
198 u = info->tagged_ports >> 21;
199 v = info->tagged_ports << 11;
200 v |= ((u32)info->fid) << 3;
201 v |= info->hash_uc_fid ? BIT(2) : 0;
202 v |= info->hash_mc_fid ? BIT(1) : 0;
203 v |= (info->profile_id & 0x4) ? 1 : 0;
204 w = ((u32)(info->profile_id & 3)) << 30;
205
206 sw_w32(u, rtl_table_data(r, 0));
207 sw_w32(v, rtl_table_data(r, 1));
208 sw_w32(w, rtl_table_data(r, 2));
209
210 rtl_table_write(r, vlan);
211 rtl_table_release(r);
212 }
213
214 static void rtl839x_vlan_set_untagged(u32 vlan, u64 portmask)
215 {
216 u32 u, v;
217
218 // Access UNTAG table (0) via table register 1
219 struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 0);
220
221 u = portmask >> 21;
222 v = portmask << 11;
223
224 sw_w32(u, rtl_table_data(r, 0));
225 sw_w32(v, rtl_table_data(r, 1));
226 rtl_table_write(r, vlan);
227
228 rtl_table_release(r);
229 }
230
231 /* Sets the L2 forwarding to be based on either the inner VLAN tag or the outer
232 */
233 static void rtl839x_vlan_fwd_on_inner(int port, bool is_set)
234 {
235 if (is_set)
236 rtl839x_mask_port_reg_be(BIT_ULL(port), 0ULL, RTL839X_VLAN_PORT_FWD);
237 else
238 rtl839x_mask_port_reg_be(0ULL, BIT_ULL(port), RTL839X_VLAN_PORT_FWD);
239 }
240
241 /*
242 * Hash seed is vid (actually rvid) concatenated with the MAC address
243 */
244 static u64 rtl839x_l2_hash_seed(u64 mac, u32 vid)
245 {
246 u64 v = vid;
247
248 v <<= 48;
249 v |= mac;
250
251 return v;
252 }
253
254 /*
255 * Applies the same hash algorithm as the one used currently by the ASIC to the seed
256 * and returns a key into the L2 hash table
257 */
258 static u32 rtl839x_l2_hash_key(struct rtl838x_switch_priv *priv, u64 seed)
259 {
260 u32 h1, h2, h;
261
262 if (sw_r32(priv->r->l2_ctrl_0) & 1) {
263 h1 = (u32) (((seed >> 60) & 0x3f) ^ ((seed >> 54) & 0x3f)
264 ^ ((seed >> 36) & 0x3f) ^ ((seed >> 30) & 0x3f)
265 ^ ((seed >> 12) & 0x3f) ^ ((seed >> 6) & 0x3f));
266 h2 = (u32) (((seed >> 48) & 0x3f) ^ ((seed >> 42) & 0x3f)
267 ^ ((seed >> 24) & 0x3f) ^ ((seed >> 18) & 0x3f)
268 ^ (seed & 0x3f));
269 h = (h1 << 6) | h2;
270 } else {
271 h = (seed >> 60)
272 ^ ((((seed >> 48) & 0x3f) << 6) | ((seed >> 54) & 0x3f))
273 ^ ((seed >> 36) & 0xfff) ^ ((seed >> 24) & 0xfff)
274 ^ ((seed >> 12) & 0xfff) ^ (seed & 0xfff);
275 }
276
277 return h;
278 }
279
280 static inline int rtl839x_mac_force_mode_ctrl(int p)
281 {
282 return RTL839X_MAC_FORCE_MODE_CTRL + (p << 2);
283 }
284
285 static inline int rtl839x_mac_port_ctrl(int p)
286 {
287 return RTL839X_MAC_PORT_CTRL(p);
288 }
289
290 static inline int rtl839x_l2_port_new_salrn(int p)
291 {
292 return RTL839X_L2_PORT_NEW_SALRN(p);
293 }
294
295 static inline int rtl839x_l2_port_new_sa_fwd(int p)
296 {
297 return RTL839X_L2_PORT_NEW_SA_FWD(p);
298 }
299
300 static inline int rtl839x_mac_link_spd_sts(int p)
301 {
302 return RTL839X_MAC_LINK_SPD_STS(p);
303 }
304
305 static inline int rtl839x_trk_mbr_ctr(int group)
306 {
307 return RTL839X_TRK_MBR_CTR + (group << 3);
308 }
309
310 static void rtl839x_fill_l2_entry(u32 r[], struct rtl838x_l2_entry *e)
311 {
312 /* Table contains different entry types, we need to identify the right one:
313 * Check for MC entries, first
314 */
315 e->is_ip_mc = !!(r[2] & BIT(31));
316 e->is_ipv6_mc = !!(r[2] & BIT(30));
317 e->type = L2_INVALID;
318 if (!e->is_ip_mc && !e->is_ipv6_mc) {
319 e->mac[0] = (r[0] >> 12);
320 e->mac[1] = (r[0] >> 4);
321 e->mac[2] = ((r[1] >> 28) | (r[0] << 4));
322 e->mac[3] = (r[1] >> 20);
323 e->mac[4] = (r[1] >> 12);
324 e->mac[5] = (r[1] >> 4);
325
326 e->vid = (r[2] >> 4) & 0xfff;
327 e->rvid = (r[0] >> 20) & 0xfff;
328
329 /* Is it a unicast entry? check multicast bit */
330 if (!(e->mac[0] & 1)) {
331 e->is_static = !!((r[2] >> 18) & 1);
332 e->port = (r[2] >> 24) & 0x3f;
333 e->block_da = !!(r[2] & (1 << 19));
334 e->block_sa = !!(r[2] & (1 << 20));
335 e->suspended = !!(r[2] & (1 << 17));
336 e->next_hop = !!(r[2] & (1 << 16));
337 if (e->next_hop) {
338 pr_debug("Found next hop entry, need to read data\n");
339 e->nh_vlan_target = !!(r[2] & BIT(15));
340 e->nh_route_id = (r[2] >> 4) & 0x1ff;
341 e->vid = e->rvid;
342 }
343 e->age = (r[2] >> 21) & 3;
344 e->valid = true;
345 if (!(r[2] & 0xc0fd0000)) /* Check for valid entry */
346 e->valid = false;
347 else
348 e->type = L2_UNICAST;
349 } else {
350 e->valid = true;
351 e->type = L2_MULTICAST;
352 e->mc_portmask_index = (r[2] >> 6) & 0xfff;
353 e->vid = e->rvid;
354 }
355 } else { // IPv4 and IPv6 multicast
356 e->vid = e->rvid = (r[0] << 20) & 0xfff;
357 e->mc_gip = r[1];
358 e->mc_portmask_index = (r[2] >> 6) & 0xfff;
359 }
360 if (e->is_ip_mc) {
361 e->valid = true;
362 e->type = IP4_MULTICAST;
363 }
364 if (e->is_ipv6_mc) {
365 e->valid = true;
366 e->type = IP6_MULTICAST;
367 }
368 // pr_info("%s: vid %d, rvid: %d\n", __func__, e->vid, e->rvid);
369 }
370
371 /*
372 * Fills the 3 SoC table registers r[] with the information in the rtl838x_l2_entry
373 */
374 static void rtl839x_fill_l2_row(u32 r[], struct rtl838x_l2_entry *e)
375 {
376 if (!e->valid) {
377 r[0] = r[1] = r[2] = 0;
378 return;
379 }
380
381 r[2] = e->is_ip_mc ? BIT(31) : 0;
382 r[2] |= e->is_ipv6_mc ? BIT(30) : 0;
383
384 if (!e->is_ip_mc && !e->is_ipv6_mc) {
385 r[0] = ((u32)e->mac[0]) << 12;
386 r[0] |= ((u32)e->mac[1]) << 4;
387 r[0] |= ((u32)e->mac[2]) >> 4;
388 r[1] = ((u32)e->mac[2]) << 28;
389 r[1] |= ((u32)e->mac[3]) << 20;
390 r[1] |= ((u32)e->mac[4]) << 12;
391 r[1] |= ((u32)e->mac[5]) << 4;
392
393 if (!(e->mac[0] & 1)) { // Not multicast
394 r[2] |= e->is_static ? BIT(18) : 0;
395 r[0] |= ((u32)e->rvid) << 20;
396 r[2] |= e->port << 24;
397 r[2] |= e->block_da ? BIT(19) : 0;
398 r[2] |= e->block_sa ? BIT(20) : 0;
399 r[2] |= e->suspended ? BIT(17) : 0;
400 r[2] |= ((u32)e->age) << 21;
401 if (e->next_hop) {
402 r[2] |= BIT(16);
403 r[2] |= e->nh_vlan_target ? BIT(15) : 0;
404 r[2] |= (e->nh_route_id & 0x7ff) << 4;
405 } else {
406 r[2] |= e->vid << 4;
407 }
408 pr_debug("Write L2 NH: %08x %08x %08x\n", r[0], r[1], r[2]);
409 } else { // L2 Multicast
410 r[0] |= ((u32)e->rvid) << 20;
411 r[2] |= ((u32)e->mc_portmask_index) << 6;
412 }
413 } else { // IPv4 or IPv6 MC entry
414 r[0] = ((u32)e->rvid) << 20;
415 r[1] = e->mc_gip;
416 r[2] |= ((u32)e->mc_portmask_index) << 6;
417 }
418 }
419
420 /*
421 * Read an L2 UC or MC entry out of a hash bucket of the L2 forwarding table
422 * hash is the id of the bucket and pos is the position of the entry in that bucket
423 * The data read from the SoC is filled into rtl838x_l2_entry
424 */
425 static u64 rtl839x_read_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
426 {
427 u32 r[3];
428 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0);
429 u32 idx = (0 << 14) | (hash << 2) | pos; // Search SRAM, with hash and at pos in bucket
430 int i;
431
432 rtl_table_read(q, idx);
433 for (i= 0; i < 3; i++)
434 r[i] = sw_r32(rtl_table_data(q, i));
435
436 rtl_table_release(q);
437
438 rtl839x_fill_l2_entry(r, e);
439 if (!e->valid)
440 return 0;
441
442 return rtl839x_l2_hash_seed(ether_addr_to_u64(&e->mac[0]), e->rvid);
443 }
444
445 static void rtl839x_write_l2_entry_using_hash(u32 hash, u32 pos, struct rtl838x_l2_entry *e)
446 {
447 u32 r[3];
448 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 0);
449 int i;
450
451 u32 idx = (0 << 14) | (hash << 2) | pos; // Access SRAM, with hash and at pos in bucket
452
453 rtl839x_fill_l2_row(r, e);
454
455 for (i= 0; i < 3; i++)
456 sw_w32(r[i], rtl_table_data(q, i));
457
458 rtl_table_write(q, idx);
459 rtl_table_release(q);
460 }
461
462 static u64 rtl839x_read_cam(int idx, struct rtl838x_l2_entry *e)
463 {
464 u32 r[3];
465 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); // Access L2 Table 1
466 int i;
467
468 rtl_table_read(q, idx);
469 for (i= 0; i < 3; i++)
470 r[i] = sw_r32(rtl_table_data(q, i));
471
472 rtl_table_release(q);
473
474 rtl839x_fill_l2_entry(r, e);
475 if (!e->valid)
476 return 0;
477
478 pr_debug("Found in CAM: R1 %x R2 %x R3 %x\n", r[0], r[1], r[2]);
479
480 // Return MAC with concatenated VID ac concatenated ID
481 return rtl839x_l2_hash_seed(ether_addr_to_u64(&e->mac[0]), e->rvid);
482 }
483
484 static void rtl839x_write_cam(int idx, struct rtl838x_l2_entry *e)
485 {
486 u32 r[3];
487 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 1); // Access L2 Table 1
488 int i;
489
490 rtl839x_fill_l2_row(r, e);
491
492 for (i= 0; i < 3; i++)
493 sw_w32(r[i], rtl_table_data(q, i));
494
495 rtl_table_write(q, idx);
496 rtl_table_release(q);
497 }
498
499 static u64 rtl839x_read_mcast_pmask(int idx)
500 {
501 u64 portmask;
502 // Read MC_PMSK (2) via register RTL8390_TBL_L2
503 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2);
504
505 rtl_table_read(q, idx);
506 portmask = sw_r32(rtl_table_data(q, 0));
507 portmask <<= 32;
508 portmask |= sw_r32(rtl_table_data(q, 1));
509 portmask >>= 11; // LSB is bit 11 in data registers
510 rtl_table_release(q);
511
512 return portmask;
513 }
514
515 static void rtl839x_write_mcast_pmask(int idx, u64 portmask)
516 {
517 // Access MC_PMSK (2) via register RTL8380_TBL_L2
518 struct table_reg *q = rtl_table_get(RTL8390_TBL_L2, 2);
519
520 portmask <<= 11; // LSB is bit 11 in data registers
521 sw_w32((u32)(portmask >> 32), rtl_table_data(q, 0));
522 sw_w32((u32)((portmask & 0xfffff800)), rtl_table_data(q, 1));
523 rtl_table_write(q, idx);
524 rtl_table_release(q);
525 }
526
527 static void rtl839x_vlan_profile_setup(int profile)
528 {
529 u32 p[2];
530 u32 pmask_id = UNKNOWN_MC_PMASK;
531
532 p[0] = pmask_id; // Use portmaks 0xfff for unknown IPv6 MC flooding
533 // Enable L2 Learning BIT 0, portmask UNKNOWN_MC_PMASK for IP/L2-MC traffic flooding
534 p[1] = 1 | pmask_id << 1 | pmask_id << 13;
535
536 sw_w32(p[0], RTL839X_VLAN_PROFILE(profile));
537 sw_w32(p[1], RTL839X_VLAN_PROFILE(profile) + 4);
538
539 rtl839x_write_mcast_pmask(UNKNOWN_MC_PMASK, 0x001fffffffffffff);
540 }
541
542 u64 rtl839x_traffic_get(int source)
543 {
544 return rtl839x_get_port_reg_be(rtl839x_port_iso_ctrl(source));
545 }
546
547 void rtl839x_traffic_set(int source, u64 dest_matrix)
548 {
549 rtl839x_set_port_reg_be(dest_matrix, rtl839x_port_iso_ctrl(source));
550 }
551
552 void rtl839x_traffic_enable(int source, int dest)
553 {
554 rtl839x_mask_port_reg_be(0, BIT_ULL(dest), rtl839x_port_iso_ctrl(source));
555 }
556
557 void rtl839x_traffic_disable(int source, int dest)
558 {
559 rtl839x_mask_port_reg_be(BIT_ULL(dest), 0, rtl839x_port_iso_ctrl(source));
560 }
561
562 static void rtl839x_l2_learning_setup(void)
563 {
564 /* Set portmask for broadcast (offset bit 12) and unknown unicast (offset 0)
565 * address flooding to the reserved entry in the portmask table used
566 * also for multicast flooding */
567 sw_w32(UNKNOWN_MC_PMASK << 12 | UNKNOWN_MC_PMASK, RTL839X_L2_FLD_PMSK);
568
569 // Limit learning to maximum: 32k entries, after that just flood (bits 0-1)
570 sw_w32((0x7fff << 2) | 0, RTL839X_L2_LRN_CONSTRT);
571
572 // Do not trap ARP packets to CPU_PORT
573 sw_w32(0, RTL839X_SPCL_TRAP_ARP_CTRL);
574 }
575
576 static void rtl839x_enable_learning(int port, bool enable)
577 {
578 // Limit learning to maximum: 32k entries
579
580 sw_w32_mask(0x7fff << 2, enable ? (0x7fff << 2) : 0,
581 RTL839X_L2_PORT_LRN_CONSTRT + (port << 2));
582 }
583
584 static void rtl839x_enable_flood(int port, bool enable)
585 {
586 /*
587 * 0: Forward
588 * 1: Disable
589 * 2: to CPU
590 * 3: Copy to CPU
591 */
592 sw_w32_mask(0x3, enable ? 0 : 1,
593 RTL839X_L2_PORT_LRN_CONSTRT + (port << 2));
594 }
595
596 static void rtl839x_enable_mcast_flood(int port, bool enable)
597 {
598
599 }
600
601 static void rtl839x_enable_bcast_flood(int port, bool enable)
602 {
603
604 }
605
606 static void rtl839x_set_static_move_action(int port, bool forward)
607 {
608 int shift = MV_ACT_PORT_SHIFT(port);
609 u32 val = forward ? MV_ACT_FORWARD : MV_ACT_DROP;
610
611 sw_w32_mask(MV_ACT_MASK << shift, val << shift,
612 RTL839X_L2_PORT_STATIC_MV_ACT(port));
613 }
614
615 irqreturn_t rtl839x_switch_irq(int irq, void *dev_id)
616 {
617 struct dsa_switch *ds = dev_id;
618 u32 status = sw_r32(RTL839X_ISR_GLB_SRC);
619 u64 ports = rtl839x_get_port_reg_le(RTL839X_ISR_PORT_LINK_STS_CHG);
620 u64 link;
621 int i;
622
623 /* Clear status */
624 rtl839x_set_port_reg_le(ports, RTL839X_ISR_PORT_LINK_STS_CHG);
625 pr_debug("RTL8390 Link change: status: %x, ports %llx\n", status, ports);
626
627 for (i = 0; i < RTL839X_CPU_PORT; i++) {
628 if (ports & BIT_ULL(i)) {
629 link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
630 if (link & BIT_ULL(i))
631 dsa_port_phylink_mac_change(ds, i, true);
632 else
633 dsa_port_phylink_mac_change(ds, i, false);
634 }
635 }
636 return IRQ_HANDLED;
637 }
638
639 // TODO: unused
640 int rtl8390_sds_power(int mac, int val)
641 {
642 u32 offset = (mac == 48) ? 0x0 : 0x100;
643 u32 mode = val ? 0 : 1;
644
645 pr_debug("In %s: mac %d, set %d\n", __func__, mac, val);
646
647 if ((mac != 48) && (mac != 49)) {
648 pr_err("%s: not an SFP port: %d\n", __func__, mac);
649 return -1;
650 }
651
652 // Set bit 1003. 1000 starts at 7c
653 sw_w32_mask(BIT(11), mode << 11, RTL839X_SDS12_13_PWR0 + offset);
654
655 return 0;
656 }
657
658 static int rtl839x_smi_wait_op(int timeout)
659 {
660 int ret = 0;
661 u32 val;
662
663 ret = readx_poll_timeout(sw_r32, RTL839X_PHYREG_ACCESS_CTRL,
664 val, !(val & 0x1), 20, timeout);
665 if (ret)
666 pr_err("%s: timeout\n", __func__);
667
668 return ret;
669 }
670
671 int rtl839x_read_phy(u32 port, u32 page, u32 reg, u32 *val)
672 {
673 u32 v;
674 int err = 0;
675
676 if (port > 63 || page > 4095 || reg > 31)
677 return -ENOTSUPP;
678
679 // Take bug on RTL839x Rev <= C into account
680 if (port >= RTL839X_CPU_PORT)
681 return -EIO;
682
683 mutex_lock(&smi_lock);
684
685 sw_w32_mask(0xffff0000, port << 16, RTL839X_PHYREG_DATA_CTRL);
686 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
687 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
688
689 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
690
691 v |= 1;
692 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
693
694 err = rtl839x_smi_wait_op(100000);
695 if (err)
696 goto errout;
697
698 *val = sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff;
699
700 errout:
701 mutex_unlock(&smi_lock);
702 return err;
703 }
704
705 int rtl839x_write_phy(u32 port, u32 page, u32 reg, u32 val)
706 {
707 u32 v;
708 int err = 0;
709
710 val &= 0xffff;
711 if (port > 63 || page > 4095 || reg > 31)
712 return -ENOTSUPP;
713
714 // Take bug on RTL839x Rev <= C into account
715 if (port >= RTL839X_CPU_PORT)
716 return -EIO;
717
718 mutex_lock(&smi_lock);
719
720 // Set PHY to access
721 rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL);
722
723 sw_w32_mask(0xffff0000, val << 16, RTL839X_PHYREG_DATA_CTRL);
724
725 v = reg << 5 | page << 10 | ((page == 0x1fff) ? 0x1f : 0) << 23;
726 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
727
728 sw_w32(0x1ff, RTL839X_PHYREG_CTRL);
729
730 v |= BIT(3) | 1; /* Write operation and execute */
731 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
732
733 err = rtl839x_smi_wait_op(100000);
734 if (err)
735 goto errout;
736
737 if (sw_r32(RTL839X_PHYREG_ACCESS_CTRL) & 0x2)
738 err = -EIO;
739
740 errout:
741 mutex_unlock(&smi_lock);
742 return err;
743 }
744
745 /*
746 * Read an mmd register of the PHY
747 */
748 int rtl839x_read_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 *val)
749 {
750 int err = 0;
751 u32 v;
752
753 // Take bug on RTL839x Rev <= C into account
754 if (port >= RTL839X_CPU_PORT)
755 return -EIO;
756
757 mutex_lock(&smi_lock);
758
759 // Set PHY to access
760 sw_w32_mask(0xffff << 16, port << 16, RTL839X_PHYREG_DATA_CTRL);
761
762 // Set MMD device number and register to write to
763 sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL);
764
765 v = BIT(2) | BIT(0); // MMD-access | EXEC
766 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
767
768 err = rtl839x_smi_wait_op(100000);
769 if (err)
770 goto errout;
771
772 // There is no error-checking via BIT 1 of v, as it does not seem to be set correctly
773 *val = (sw_r32(RTL839X_PHYREG_DATA_CTRL) & 0xffff);
774 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, *val, err);
775
776 errout:
777 mutex_unlock(&smi_lock);
778 return err;
779 }
780
781 /*
782 * Write to an mmd register of the PHY
783 */
784 int rtl839x_write_mmd_phy(u32 port, u32 devnum, u32 regnum, u32 val)
785 {
786 int err = 0;
787 u32 v;
788
789 // Take bug on RTL839x Rev <= C into account
790 if (port >= RTL839X_CPU_PORT)
791 return -EIO;
792
793 mutex_lock(&smi_lock);
794
795 // Set PHY to access
796 rtl839x_set_port_reg_le(BIT_ULL(port), RTL839X_PHYREG_PORT_CTRL);
797
798 // Set data to write
799 sw_w32_mask(0xffff << 16, val << 16, RTL839X_PHYREG_DATA_CTRL);
800
801 // Set MMD device number and register to write to
802 sw_w32(devnum << 16 | (regnum & 0xffff), RTL839X_PHYREG_MMD_CTRL);
803
804 v = BIT(3) | BIT(2) | BIT(0); // WRITE | MMD-access | EXEC
805 sw_w32(v, RTL839X_PHYREG_ACCESS_CTRL);
806
807 err = rtl839x_smi_wait_op(100000);
808 if (err)
809 goto errout;
810
811 pr_debug("%s: port %d, regnum: %x, val: %x (err %d)\n", __func__, port, regnum, val, err);
812
813 errout:
814 mutex_unlock(&smi_lock);
815 return err;
816 }
817
818 void rtl8390_get_version(struct rtl838x_switch_priv *priv)
819 {
820 u32 info, model;
821
822 sw_w32_mask(0xf << 28, 0xa << 28, RTL839X_CHIP_INFO);
823 info = sw_r32(RTL839X_CHIP_INFO);
824
825 model = sw_r32(RTL839X_MODEL_NAME_INFO);
826 priv->version = RTL8390_VERSION_A + ((model & 0x3f) >> 1);
827
828 pr_info("RTL839X Chip-Info: %x, version %c\n", info, priv->version);
829 }
830
831 void rtl839x_vlan_profile_dump(int profile)
832 {
833 u32 p[2];
834
835 if (profile < 0 || profile > 7)
836 return;
837
838 p[0] = sw_r32(RTL839X_VLAN_PROFILE(profile));
839 p[1] = sw_r32(RTL839X_VLAN_PROFILE(profile) + 4);
840
841 pr_info("VLAN profile %d: L2 learning: %d, UNKN L2MC FLD PMSK %d, \
842 UNKN IPMC FLD PMSK %d, UNKN IPv6MC FLD PMSK: %d",
843 profile, p[1] & 1, (p[1] >> 1) & 0xfff, (p[1] >> 13) & 0xfff,
844 (p[0]) & 0xfff);
845 pr_info("VLAN profile %d: raw %08x, %08x\n", profile, p[0], p[1]);
846 }
847
848 static void rtl839x_stp_get(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
849 {
850 int i;
851 u32 cmd = 1 << 16 /* Execute cmd */
852 | 0 << 15 /* Read */
853 | 5 << 12 /* Table type 0b101 */
854 | (msti & 0xfff);
855 priv->r->exec_tbl0_cmd(cmd);
856
857 for (i = 0; i < 4; i++)
858 port_state[i] = sw_r32(priv->r->tbl_access_data_0(i));
859 }
860
861 static void rtl839x_stp_set(struct rtl838x_switch_priv *priv, u16 msti, u32 port_state[])
862 {
863 int i;
864 u32 cmd = 1 << 16 /* Execute cmd */
865 | 1 << 15 /* Write */
866 | 5 << 12 /* Table type 0b101 */
867 | (msti & 0xfff);
868 for (i = 0; i < 4; i++)
869 sw_w32(port_state[i], priv->r->tbl_access_data_0(i));
870 priv->r->exec_tbl0_cmd(cmd);
871 }
872
873 /*
874 * Enables or disables the EEE/EEEP capability of a port
875 */
876 void rtl839x_port_eee_set(struct rtl838x_switch_priv *priv, int port, bool enable)
877 {
878 u32 v;
879
880 // This works only for Ethernet ports, and on the RTL839X, ports above 47 are SFP
881 if (port >= 48)
882 return;
883
884 enable = true;
885 pr_debug("In %s: setting port %d to %d\n", __func__, port, enable);
886 v = enable ? 0xf : 0x0;
887
888 // Set EEE for 100, 500, 1000MBit and 10GBit
889 sw_w32_mask(0xf << 8, v << 8, rtl839x_mac_force_mode_ctrl(port));
890
891 // Set TX/RX EEE state
892 v = enable ? 0x3 : 0x0;
893 sw_w32(v, RTL839X_EEE_CTRL(port));
894
895 priv->ports[port].eee_enabled = enable;
896 }
897
898 /*
899 * Get EEE own capabilities and negotiation result
900 */
901 int rtl839x_eee_port_ability(struct rtl838x_switch_priv *priv, struct ethtool_eee *e, int port)
902 {
903 u64 link, a;
904
905 if (port >= 48)
906 return 0;
907
908 link = rtl839x_get_port_reg_le(RTL839X_MAC_LINK_STS);
909 if (!(link & BIT_ULL(port)))
910 return 0;
911
912 if (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(8))
913 e->advertised |= ADVERTISED_100baseT_Full;
914
915 if (sw_r32(rtl839x_mac_force_mode_ctrl(port)) & BIT(10))
916 e->advertised |= ADVERTISED_1000baseT_Full;
917
918 a = rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY);
919 pr_info("Link partner: %016llx\n", a);
920 if (rtl839x_get_port_reg_le(RTL839X_MAC_EEE_ABLTY) & BIT_ULL(port)) {
921 e->lp_advertised = ADVERTISED_100baseT_Full;
922 e->lp_advertised |= ADVERTISED_1000baseT_Full;
923 return 1;
924 }
925
926 return 0;
927 }
928
929 static void rtl839x_init_eee(struct rtl838x_switch_priv *priv, bool enable)
930 {
931 int i;
932
933 pr_info("Setting up EEE, state: %d\n", enable);
934
935 // Set wake timer for TX and pause timer both to 0x21
936 sw_w32_mask(0xff << 20| 0xff, 0x21 << 20| 0x21, RTL839X_EEE_TX_TIMER_GELITE_CTRL);
937 // Set pause wake timer for GIGA-EEE to 0x11
938 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_GIGA_CTRL);
939 // Set pause wake timer for 10GBit ports to 0x11
940 sw_w32_mask(0xff << 20, 0x11 << 20, RTL839X_EEE_TX_TIMER_10G_CTRL);
941
942 // Setup EEE on all ports
943 for (i = 0; i < priv->cpu_port; i++) {
944 if (priv->ports[i].phy)
945 rtl839x_port_eee_set(priv, i, enable);
946 }
947 priv->eee_enabled = enable;
948 }
949
950 static void rtl839x_pie_lookup_enable(struct rtl838x_switch_priv *priv, int index)
951 {
952 int block = index / PIE_BLOCK_SIZE;
953
954 sw_w32_mask(0, BIT(block), RTL839X_ACL_BLK_LOOKUP_CTRL);
955 }
956
957 /*
958 * Delete a range of Packet Inspection Engine rules
959 */
960 static int rtl839x_pie_rule_del(struct rtl838x_switch_priv *priv, int index_from, int index_to)
961 {
962 u32 v = (index_from << 1)| (index_to << 13 ) | BIT(0);
963
964 pr_debug("%s: from %d to %d\n", __func__, index_from, index_to);
965 mutex_lock(&priv->reg_mutex);
966
967 // Write from-to and execute bit into control register
968 sw_w32(v, RTL839X_ACL_CLR_CTRL);
969
970 // Wait until command has completed
971 do {
972 } while (sw_r32(RTL839X_ACL_CLR_CTRL) & BIT(0));
973
974 mutex_unlock(&priv->reg_mutex);
975 return 0;
976 }
977
978 /*
979 * Reads the intermediate representation of the templated match-fields of the
980 * PIE rule in the pie_rule structure and fills in the raw data fields in the
981 * raw register space r[].
982 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
983 * however the RTL9310 has 2 more registers / fields and the physical field-ids are different
984 * on all SoCs
985 * On the RTL8390 the template mask registers are not word-aligned!
986 */
987 static void rtl839x_write_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
988 {
989 int i;
990 enum template_field_id field_type;
991 u16 data, data_m;
992
993 for (i = 0; i < N_FIXED_FIELDS; i++) {
994 field_type = t[i];
995 data = data_m = 0;
996
997 switch (field_type) {
998 case TEMPLATE_FIELD_SPM0:
999 data = pr->spm;
1000 data_m = pr->spm_m;
1001 break;
1002 case TEMPLATE_FIELD_SPM1:
1003 data = pr->spm >> 16;
1004 data_m = pr->spm_m >> 16;
1005 break;
1006 case TEMPLATE_FIELD_SPM2:
1007 data = pr->spm >> 32;
1008 data_m = pr->spm_m >> 32;
1009 break;
1010 case TEMPLATE_FIELD_SPM3:
1011 data = pr->spm >> 48;
1012 data_m = pr->spm_m >> 48;
1013 break;
1014 case TEMPLATE_FIELD_OTAG:
1015 data = pr->otag;
1016 data_m = pr->otag_m;
1017 break;
1018 case TEMPLATE_FIELD_SMAC0:
1019 data = pr->smac[4];
1020 data = (data << 8) | pr->smac[5];
1021 data_m = pr->smac_m[4];
1022 data_m = (data_m << 8) | pr->smac_m[5];
1023 break;
1024 case TEMPLATE_FIELD_SMAC1:
1025 data = pr->smac[2];
1026 data = (data << 8) | pr->smac[3];
1027 data_m = pr->smac_m[2];
1028 data_m = (data_m << 8) | pr->smac_m[3];
1029 break;
1030 case TEMPLATE_FIELD_SMAC2:
1031 data = pr->smac[0];
1032 data = (data << 8) | pr->smac[1];
1033 data_m = pr->smac_m[0];
1034 data_m = (data_m << 8) | pr->smac_m[1];
1035 break;
1036 case TEMPLATE_FIELD_DMAC0:
1037 data = pr->dmac[4];
1038 data = (data << 8) | pr->dmac[5];
1039 data_m = pr->dmac_m[4];
1040 data_m = (data_m << 8) | pr->dmac_m[5];
1041 break;
1042 case TEMPLATE_FIELD_DMAC1:
1043 data = pr->dmac[2];
1044 data = (data << 8) | pr->dmac[3];
1045 data_m = pr->dmac_m[2];
1046 data_m = (data_m << 8) | pr->dmac_m[3];
1047 break;
1048 case TEMPLATE_FIELD_DMAC2:
1049 data = pr->dmac[0];
1050 data = (data << 8) | pr->dmac[1];
1051 data_m = pr->dmac_m[0];
1052 data_m = (data_m << 8) | pr->dmac_m[1];
1053 break;
1054 case TEMPLATE_FIELD_ETHERTYPE:
1055 data = pr->ethertype;
1056 data_m = pr->ethertype_m;
1057 break;
1058 case TEMPLATE_FIELD_ITAG:
1059 data = pr->itag;
1060 data_m = pr->itag_m;
1061 break;
1062 case TEMPLATE_FIELD_SIP0:
1063 if (pr->is_ipv6) {
1064 data = pr->sip6.s6_addr16[7];
1065 data_m = pr->sip6_m.s6_addr16[7];
1066 } else {
1067 data = pr->sip;
1068 data_m = pr->sip_m;
1069 }
1070 break;
1071 case TEMPLATE_FIELD_SIP1:
1072 if (pr->is_ipv6) {
1073 data = pr->sip6.s6_addr16[6];
1074 data_m = pr->sip6_m.s6_addr16[6];
1075 } else {
1076 data = pr->sip >> 16;
1077 data_m = pr->sip_m >> 16;
1078 }
1079 break;
1080
1081 case TEMPLATE_FIELD_SIP2:
1082 case TEMPLATE_FIELD_SIP3:
1083 case TEMPLATE_FIELD_SIP4:
1084 case TEMPLATE_FIELD_SIP5:
1085 case TEMPLATE_FIELD_SIP6:
1086 case TEMPLATE_FIELD_SIP7:
1087 data = pr->sip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1088 data_m = pr->sip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_SIP2)];
1089 break;
1090
1091 case TEMPLATE_FIELD_DIP0:
1092 if (pr->is_ipv6) {
1093 data = pr->dip6.s6_addr16[7];
1094 data_m = pr->dip6_m.s6_addr16[7];
1095 } else {
1096 data = pr->dip;
1097 data_m = pr->dip_m;
1098 }
1099 break;
1100
1101 case TEMPLATE_FIELD_DIP1:
1102 if (pr->is_ipv6) {
1103 data = pr->dip6.s6_addr16[6];
1104 data_m = pr->dip6_m.s6_addr16[6];
1105 } else {
1106 data = pr->dip >> 16;
1107 data_m = pr->dip_m >> 16;
1108 }
1109 break;
1110
1111 case TEMPLATE_FIELD_DIP2:
1112 case TEMPLATE_FIELD_DIP3:
1113 case TEMPLATE_FIELD_DIP4:
1114 case TEMPLATE_FIELD_DIP5:
1115 case TEMPLATE_FIELD_DIP6:
1116 case TEMPLATE_FIELD_DIP7:
1117 data = pr->dip6.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1118 data_m = pr->dip6_m.s6_addr16[5 - (field_type - TEMPLATE_FIELD_DIP2)];
1119 break;
1120
1121 case TEMPLATE_FIELD_IP_TOS_PROTO:
1122 data = pr->tos_proto;
1123 data_m = pr->tos_proto_m;
1124 break;
1125 case TEMPLATE_FIELD_L4_SPORT:
1126 data = pr->sport;
1127 data_m = pr->sport_m;
1128 break;
1129 case TEMPLATE_FIELD_L4_DPORT:
1130 data = pr->dport;
1131 data_m = pr->dport_m;
1132 break;
1133 case TEMPLATE_FIELD_ICMP_IGMP:
1134 data = pr->icmp_igmp;
1135 data_m = pr->icmp_igmp_m;
1136 break;
1137 default:
1138 pr_info("%s: unknown field %d\n", __func__, field_type);
1139 }
1140
1141 // On the RTL8390, the mask fields are not word aligned!
1142 if (!(i % 2)) {
1143 r[5 - i / 2] = data;
1144 r[12 - i / 2] |= ((u32)data_m << 8);
1145 } else {
1146 r[5 - i / 2] |= ((u32)data) << 16;
1147 r[12 - i / 2] |= ((u32)data_m) << 24;
1148 r[11 - i / 2] |= ((u32)data_m) >> 8;
1149 }
1150 }
1151 }
1152
1153 /*
1154 * Creates the intermediate representation of the templated match-fields of the
1155 * PIE rule in the pie_rule structure by reading the raw data fields in the
1156 * raw register space r[].
1157 * The register space configuration size is identical for the RTL8380/90 and RTL9300,
1158 * however the RTL9310 has 2 more registers / fields and the physical field-ids
1159 * On the RTL8390 the template mask registers are not word-aligned!
1160 */
1161 void rtl839x_read_pie_templated(u32 r[], struct pie_rule *pr, enum template_field_id t[])
1162 {
1163 int i;
1164 enum template_field_id field_type;
1165 u16 data, data_m;
1166
1167 for (i = 0; i < N_FIXED_FIELDS; i++) {
1168 field_type = t[i];
1169 if (!(i % 2)) {
1170 data = r[5 - i / 2];
1171 data_m = r[12 - i / 2];
1172 } else {
1173 data = r[5 - i / 2] >> 16;
1174 data_m = r[12 - i / 2] >> 16;
1175 }
1176
1177 switch (field_type) {
1178 case TEMPLATE_FIELD_SPM0:
1179 pr->spm = (pr->spn << 16) | data;
1180 pr->spm_m = (pr->spn << 16) | data_m;
1181 break;
1182 case TEMPLATE_FIELD_SPM1:
1183 pr->spm = data;
1184 pr->spm_m = data_m;
1185 break;
1186 case TEMPLATE_FIELD_OTAG:
1187 pr->otag = data;
1188 pr->otag_m = data_m;
1189 break;
1190 case TEMPLATE_FIELD_SMAC0:
1191 pr->smac[4] = data >> 8;
1192 pr->smac[5] = data;
1193 pr->smac_m[4] = data >> 8;
1194 pr->smac_m[5] = data;
1195 break;
1196 case TEMPLATE_FIELD_SMAC1:
1197 pr->smac[2] = data >> 8;
1198 pr->smac[3] = data;
1199 pr->smac_m[2] = data >> 8;
1200 pr->smac_m[3] = data;
1201 break;
1202 case TEMPLATE_FIELD_SMAC2:
1203 pr->smac[0] = data >> 8;
1204 pr->smac[1] = data;
1205 pr->smac_m[0] = data >> 8;
1206 pr->smac_m[1] = data;
1207 break;
1208 case TEMPLATE_FIELD_DMAC0:
1209 pr->dmac[4] = data >> 8;
1210 pr->dmac[5] = data;
1211 pr->dmac_m[4] = data >> 8;
1212 pr->dmac_m[5] = data;
1213 break;
1214 case TEMPLATE_FIELD_DMAC1:
1215 pr->dmac[2] = data >> 8;
1216 pr->dmac[3] = data;
1217 pr->dmac_m[2] = data >> 8;
1218 pr->dmac_m[3] = data;
1219 break;
1220 case TEMPLATE_FIELD_DMAC2:
1221 pr->dmac[0] = data >> 8;
1222 pr->dmac[1] = data;
1223 pr->dmac_m[0] = data >> 8;
1224 pr->dmac_m[1] = data;
1225 break;
1226 case TEMPLATE_FIELD_ETHERTYPE:
1227 pr->ethertype = data;
1228 pr->ethertype_m = data_m;
1229 break;
1230 case TEMPLATE_FIELD_ITAG:
1231 pr->itag = data;
1232 pr->itag_m = data_m;
1233 break;
1234 case TEMPLATE_FIELD_SIP0:
1235 pr->sip = data;
1236 pr->sip_m = data_m;
1237 break;
1238 case TEMPLATE_FIELD_SIP1:
1239 pr->sip = (pr->sip << 16) | data;
1240 pr->sip_m = (pr->sip << 16) | data_m;
1241 break;
1242 case TEMPLATE_FIELD_SIP2:
1243 pr->is_ipv6 = true;
1244 // Make use of limitiations on the position of the match values
1245 ipv6_addr_set(&pr->sip6, pr->sip, r[5 - i / 2],
1246 r[4 - i / 2], r[3 - i / 2]);
1247 ipv6_addr_set(&pr->sip6_m, pr->sip_m, r[5 - i / 2],
1248 r[4 - i / 2], r[3 - i / 2]);
1249 case TEMPLATE_FIELD_SIP3:
1250 case TEMPLATE_FIELD_SIP4:
1251 case TEMPLATE_FIELD_SIP5:
1252 case TEMPLATE_FIELD_SIP6:
1253 case TEMPLATE_FIELD_SIP7:
1254 break;
1255
1256 case TEMPLATE_FIELD_DIP0:
1257 pr->dip = data;
1258 pr->dip_m = data_m;
1259 break;
1260
1261 case TEMPLATE_FIELD_DIP1:
1262 pr->dip = (pr->dip << 16) | data;
1263 pr->dip_m = (pr->dip << 16) | data_m;
1264 break;
1265
1266 case TEMPLATE_FIELD_DIP2:
1267 pr->is_ipv6 = true;
1268 ipv6_addr_set(&pr->dip6, pr->dip, r[5 - i / 2],
1269 r[4 - i / 2], r[3 - i / 2]);
1270 ipv6_addr_set(&pr->dip6_m, pr->dip_m, r[5 - i / 2],
1271 r[4 - i / 2], r[3 - i / 2]);
1272 case TEMPLATE_FIELD_DIP3:
1273 case TEMPLATE_FIELD_DIP4:
1274 case TEMPLATE_FIELD_DIP5:
1275 case TEMPLATE_FIELD_DIP6:
1276 case TEMPLATE_FIELD_DIP7:
1277 break;
1278 case TEMPLATE_FIELD_IP_TOS_PROTO:
1279 pr->tos_proto = data;
1280 pr->tos_proto_m = data_m;
1281 break;
1282 case TEMPLATE_FIELD_L4_SPORT:
1283 pr->sport = data;
1284 pr->sport_m = data_m;
1285 break;
1286 case TEMPLATE_FIELD_L4_DPORT:
1287 pr->dport = data;
1288 pr->dport_m = data_m;
1289 break;
1290 case TEMPLATE_FIELD_ICMP_IGMP:
1291 pr->icmp_igmp = data;
1292 pr->icmp_igmp_m = data_m;
1293 break;
1294 default:
1295 pr_info("%s: unknown field %d\n", __func__, field_type);
1296 }
1297 }
1298 }
1299
1300 static void rtl839x_read_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1301 {
1302 pr->spmmask_fix = (r[6] >> 30) & 0x3;
1303 pr->spn = (r[6] >> 24) & 0x3f;
1304 pr->mgnt_vlan = (r[6] >> 23) & 1;
1305 pr->dmac_hit_sw = (r[6] >> 22) & 1;
1306 pr->not_first_frag = (r[6] >> 21) & 1;
1307 pr->frame_type_l4 = (r[6] >> 18) & 7;
1308 pr->frame_type = (r[6] >> 16) & 3;
1309 pr->otag_fmt = (r[6] >> 15) & 1;
1310 pr->itag_fmt = (r[6] >> 14) & 1;
1311 pr->otag_exist = (r[6] >> 13) & 1;
1312 pr->itag_exist = (r[6] >> 12) & 1;
1313 pr->frame_type_l2 = (r[6] >> 10) & 3;
1314 pr->tid = (r[6] >> 8) & 3;
1315
1316 pr->spmmask_fix_m = (r[12] >> 6) & 0x3;
1317 pr->spn_m = r[12] & 0x3f;
1318 pr->mgnt_vlan_m = (r[13] >> 31) & 1;
1319 pr->dmac_hit_sw_m = (r[13] >> 30) & 1;
1320 pr->not_first_frag_m = (r[13] >> 29) & 1;
1321 pr->frame_type_l4_m = (r[13] >> 26) & 7;
1322 pr->frame_type_m = (r[13] >> 24) & 3;
1323 pr->otag_fmt_m = (r[13] >> 23) & 1;
1324 pr->itag_fmt_m = (r[13] >> 22) & 1;
1325 pr->otag_exist_m = (r[13] >> 21) & 1;
1326 pr->itag_exist_m = (r[13] >> 20) & 1;
1327 pr->frame_type_l2_m = (r[13] >> 18) & 3;
1328 pr->tid_m = (r[13] >> 16) & 3;
1329
1330 pr->valid = r[13] & BIT(15);
1331 pr->cond_not = r[13] & BIT(14);
1332 pr->cond_and1 = r[13] & BIT(13);
1333 pr->cond_and2 = r[13] & BIT(12);
1334 }
1335
1336 static void rtl839x_write_pie_fixed_fields(u32 r[], struct pie_rule *pr)
1337 {
1338 r[6] = ((u32) (pr->spmmask_fix & 0x3)) << 30;
1339 r[6] |= ((u32) (pr->spn & 0x3f)) << 24;
1340 r[6] |= pr->mgnt_vlan ? BIT(23) : 0;
1341 r[6] |= pr->dmac_hit_sw ? BIT(22) : 0;
1342 r[6] |= pr->not_first_frag ? BIT(21) : 0;
1343 r[6] |= ((u32) (pr->frame_type_l4 & 0x7)) << 18;
1344 r[6] |= ((u32) (pr->frame_type & 0x3)) << 16;
1345 r[6] |= pr->otag_fmt ? BIT(15) : 0;
1346 r[6] |= pr->itag_fmt ? BIT(14) : 0;
1347 r[6] |= pr->otag_exist ? BIT(13) : 0;
1348 r[6] |= pr->itag_exist ? BIT(12) : 0;
1349 r[6] |= ((u32) (pr->frame_type_l2 & 0x3)) << 10;
1350 r[6] |= ((u32) (pr->tid & 0x3)) << 8;
1351
1352 r[12] |= ((u32) (pr->spmmask_fix_m & 0x3)) << 6;
1353 r[12] |= (u32) (pr->spn_m & 0x3f);
1354 r[13] |= pr->mgnt_vlan_m ? BIT(31) : 0;
1355 r[13] |= pr->dmac_hit_sw_m ? BIT(30) : 0;
1356 r[13] |= pr->not_first_frag_m ? BIT(29) : 0;
1357 r[13] |= ((u32) (pr->frame_type_l4_m & 0x7)) << 26;
1358 r[13] |= ((u32) (pr->frame_type_m & 0x3)) << 24;
1359 r[13] |= pr->otag_fmt_m ? BIT(23) : 0;
1360 r[13] |= pr->itag_fmt_m ? BIT(22) : 0;
1361 r[13] |= pr->otag_exist_m ? BIT(21) : 0;
1362 r[13] |= pr->itag_exist_m ? BIT(20) : 0;
1363 r[13] |= ((u32) (pr->frame_type_l2_m & 0x3)) << 18;
1364 r[13] |= ((u32) (pr->tid_m & 0x3)) << 16;
1365
1366 r[13] |= pr->valid ? BIT(15) : 0;
1367 r[13] |= pr->cond_not ? BIT(14) : 0;
1368 r[13] |= pr->cond_and1 ? BIT(13) : 0;
1369 r[13] |= pr->cond_and2 ? BIT(12) : 0;
1370 }
1371
1372 static void rtl839x_write_pie_action(u32 r[], struct pie_rule *pr)
1373 {
1374 if (pr->drop) {
1375 r[13] |= 0x9; // Set ACT_MASK_FWD & FWD_ACT = DROP
1376 r[13] |= BIT(3);
1377 } else {
1378 r[13] |= pr->fwd_sel ? BIT(3) : 0;
1379 r[13] |= pr->fwd_act;
1380 }
1381 r[13] |= pr->bypass_sel ? BIT(11) : 0;
1382 r[13] |= pr->mpls_sel ? BIT(10) : 0;
1383 r[13] |= pr->nopri_sel ? BIT(9) : 0;
1384 r[13] |= pr->ovid_sel ? BIT(8) : 0;
1385 r[13] |= pr->ivid_sel ? BIT(7) : 0;
1386 r[13] |= pr->meter_sel ? BIT(6) : 0;
1387 r[13] |= pr->mir_sel ? BIT(5) : 0;
1388 r[13] |= pr->log_sel ? BIT(4) : 0;
1389
1390 r[14] |= ((u32)(pr->fwd_data & 0x3fff)) << 18;
1391 r[14] |= pr->log_octets ? BIT(17) : 0;
1392 r[14] |= ((u32)(pr->log_data & 0x7ff)) << 4;
1393 r[14] |= (pr->mir_data & 0x3) << 3;
1394 r[14] |= ((u32)(pr->meter_data >> 7)) & 0x7;
1395 r[15] |= (u32)(pr->meter_data) << 26;
1396 r[15] |= ((u32)(pr->ivid_act) << 23) & 0x3;
1397 r[15] |= ((u32)(pr->ivid_data) << 9) & 0xfff;
1398 r[15] |= ((u32)(pr->ovid_act) << 6) & 0x3;
1399 r[15] |= ((u32)(pr->ovid_data) >> 4) & 0xff;
1400 r[16] |= ((u32)(pr->ovid_data) & 0xf) << 28;
1401 r[16] |= ((u32)(pr->nopri_data) & 0x7) << 20;
1402 r[16] |= ((u32)(pr->mpls_act) & 0x7) << 20;
1403 r[16] |= ((u32)(pr->mpls_lib_idx) & 0x7) << 20;
1404 r[16] |= pr->bypass_all ? BIT(9) : 0;
1405 r[16] |= pr->bypass_igr_stp ? BIT(8) : 0;
1406 r[16] |= pr->bypass_ibc_sc ? BIT(7) : 0;
1407 }
1408
1409 static void rtl839x_read_pie_action(u32 r[], struct pie_rule *pr)
1410 {
1411 if (r[13] & BIT(3)) { // ACT_MASK_FWD set, is it a drop?
1412 if ((r[14] & 0x7) == 1) {
1413 pr->drop = true;
1414 } else {
1415 pr->fwd_sel = true;
1416 pr->fwd_act = r[14] & 0x7;
1417 }
1418 }
1419
1420 pr->bypass_sel = r[13] & BIT(11);
1421 pr->mpls_sel = r[13] & BIT(10);
1422 pr->nopri_sel = r[13] & BIT(9);
1423 pr->ovid_sel = r[13] & BIT(8);
1424 pr->ivid_sel = r[13] & BIT(7);
1425 pr->meter_sel = r[13] & BIT(6);
1426 pr->mir_sel = r[13] & BIT(5);
1427 pr->log_sel = r[13] & BIT(4);
1428
1429 // TODO: Read in data fields
1430
1431 pr->bypass_all = r[16] & BIT(9);
1432 pr->bypass_igr_stp = r[16] & BIT(8);
1433 pr->bypass_ibc_sc = r[16] & BIT(7);
1434 }
1435
1436 void rtl839x_pie_rule_dump_raw(u32 r[])
1437 {
1438 pr_info("Raw IACL table entry:\n");
1439 pr_info("Match : %08x %08x %08x %08x %08x %08x\n", r[0], r[1], r[2], r[3], r[4], r[5]);
1440 pr_info("Fixed : %06x\n", r[6] >> 8);
1441 pr_info("Match M: %08x %08x %08x %08x %08x %08x\n",
1442 (r[6] << 24) | (r[7] >> 8), (r[7] << 24) | (r[8] >> 8), (r[8] << 24) | (r[9] >> 8),
1443 (r[9] << 24) | (r[10] >> 8), (r[10] << 24) | (r[11] >> 8),
1444 (r[11] << 24) | (r[12] >> 8));
1445 pr_info("R[13]: %08x\n", r[13]);
1446 pr_info("Fixed M: %06x\n", ((r[12] << 16) | (r[13] >> 16)) & 0xffffff);
1447 pr_info("Valid / not / and1 / and2 : %1x\n", (r[13] >> 12) & 0xf);
1448 pr_info("r 13-16: %08x %08x %08x %08x\n", r[13], r[14], r[15], r[16]);
1449 }
1450
1451 void rtl839x_pie_rule_dump(struct pie_rule *pr)
1452 {
1453 pr_info("Drop: %d, fwd: %d, ovid: %d, ivid: %d, flt: %d, log: %d, rmk: %d, meter: %d tagst: %d, mir: %d, nopri: %d, cpupri: %d, otpid: %d, itpid: %d, shape: %d\n",
1454 pr->drop, pr->fwd_sel, pr->ovid_sel, pr->ivid_sel, pr->flt_sel, pr->log_sel, pr->rmk_sel, pr->log_sel, pr->tagst_sel, pr->mir_sel, pr->nopri_sel,
1455 pr->cpupri_sel, pr->otpid_sel, pr->itpid_sel, pr->shaper_sel);
1456 if (pr->fwd_sel)
1457 pr_info("FWD: %08x\n", pr->fwd_data);
1458 pr_info("TID: %x, %x\n", pr->tid, pr->tid_m);
1459 }
1460
1461 static int rtl839x_pie_rule_read(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1462 {
1463 // Read IACL table (2) via register 0
1464 struct table_reg *q = rtl_table_get(RTL8380_TBL_0, 2);
1465 u32 r[17];
1466 int i;
1467 int block = idx / PIE_BLOCK_SIZE;
1468 u32 t_select = sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block));
1469
1470 memset(pr, 0, sizeof(*pr));
1471 rtl_table_read(q, idx);
1472 for (i = 0; i < 17; i++)
1473 r[i] = sw_r32(rtl_table_data(q, i));
1474
1475 rtl_table_release(q);
1476
1477 rtl839x_read_pie_fixed_fields(r, pr);
1478 if (!pr->valid)
1479 return 0;
1480
1481 pr_debug("%s: template_selectors %08x, tid: %d\n", __func__, t_select, pr->tid);
1482 rtl839x_pie_rule_dump_raw(r);
1483
1484 rtl839x_read_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
1485
1486 rtl839x_read_pie_action(r, pr);
1487
1488 return 0;
1489 }
1490
1491 static int rtl839x_pie_rule_write(struct rtl838x_switch_priv *priv, int idx, struct pie_rule *pr)
1492 {
1493 // Access IACL table (2) via register 0
1494 struct table_reg *q = rtl_table_get(RTL8390_TBL_0, 2);
1495 u32 r[17];
1496 int i;
1497 int block = idx / PIE_BLOCK_SIZE;
1498 u32 t_select = sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block));
1499
1500 pr_debug("%s: %d, t_select: %08x\n", __func__, idx, t_select);
1501
1502 for (i = 0; i < 17; i++)
1503 r[i] = 0;
1504
1505 if (!pr->valid) {
1506 rtl_table_write(q, idx);
1507 rtl_table_release(q);
1508 return 0;
1509 }
1510 rtl839x_write_pie_fixed_fields(r, pr);
1511
1512 pr_debug("%s: template %d\n", __func__, (t_select >> (pr->tid * 3)) & 0x7);
1513 rtl839x_write_pie_templated(r, pr, fixed_templates[(t_select >> (pr->tid * 3)) & 0x7]);
1514
1515 rtl839x_write_pie_action(r, pr);
1516
1517 // rtl839x_pie_rule_dump_raw(r);
1518
1519 for (i = 0; i < 17; i++)
1520 sw_w32(r[i], rtl_table_data(q, i));
1521
1522 rtl_table_write(q, idx);
1523 rtl_table_release(q);
1524
1525 return 0;
1526 }
1527
1528 static bool rtl839x_pie_templ_has(int t, enum template_field_id field_type)
1529 {
1530 int i;
1531 enum template_field_id ft;
1532
1533 for (i = 0; i < N_FIXED_FIELDS; i++) {
1534 ft = fixed_templates[t][i];
1535 if (field_type == ft)
1536 return true;
1537 }
1538
1539 return false;
1540 }
1541
1542 static int rtl839x_pie_verify_template(struct rtl838x_switch_priv *priv,
1543 struct pie_rule *pr, int t, int block)
1544 {
1545 int i;
1546
1547 if (!pr->is_ipv6 && pr->sip_m && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SIP0))
1548 return -1;
1549
1550 if (!pr->is_ipv6 && pr->dip_m && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DIP0))
1551 return -1;
1552
1553 if (pr->is_ipv6) {
1554 if ((pr->sip6_m.s6_addr32[0] || pr->sip6_m.s6_addr32[1]
1555 || pr->sip6_m.s6_addr32[2] || pr->sip6_m.s6_addr32[3])
1556 && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SIP2))
1557 return -1;
1558 if ((pr->dip6_m.s6_addr32[0] || pr->dip6_m.s6_addr32[1]
1559 || pr->dip6_m.s6_addr32[2] || pr->dip6_m.s6_addr32[3])
1560 && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DIP2))
1561 return -1;
1562 }
1563
1564 if (ether_addr_to_u64(pr->smac) && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_SMAC0))
1565 return -1;
1566
1567 if (ether_addr_to_u64(pr->dmac) && !rtl839x_pie_templ_has(t, TEMPLATE_FIELD_DMAC0))
1568 return -1;
1569
1570 // TODO: Check more
1571
1572 i = find_first_zero_bit(&priv->pie_use_bm[block * 4], PIE_BLOCK_SIZE);
1573
1574 if (i >= PIE_BLOCK_SIZE)
1575 return -1;
1576
1577 return i + PIE_BLOCK_SIZE * block;
1578 }
1579
1580 static int rtl839x_pie_rule_add(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1581 {
1582 int idx, block, j, t;
1583 int min_block = 0;
1584 int max_block = priv->n_pie_blocks / 2;
1585
1586 if (pr->is_egress) {
1587 min_block = max_block;
1588 max_block = priv->n_pie_blocks;
1589 }
1590
1591 mutex_lock(&priv->pie_mutex);
1592
1593 for (block = min_block; block < max_block; block++) {
1594 for (j = 0; j < 2; j++) {
1595 t = (sw_r32(RTL839X_ACL_BLK_TMPLTE_CTRL(block)) >> (j * 3)) & 0x7;
1596 idx = rtl839x_pie_verify_template(priv, pr, t, block);
1597 if (idx >= 0)
1598 break;
1599 }
1600 if (j < 2)
1601 break;
1602 }
1603
1604 if (block >= priv->n_pie_blocks) {
1605 mutex_unlock(&priv->pie_mutex);
1606 return -EOPNOTSUPP;
1607 }
1608
1609 set_bit(idx, priv->pie_use_bm);
1610
1611 pr->valid = true;
1612 pr->tid = j; // Mapped to template number
1613 pr->tid_m = 0x3;
1614 pr->id = idx;
1615
1616 rtl839x_pie_lookup_enable(priv, idx);
1617 rtl839x_pie_rule_write(priv, idx, pr);
1618
1619 mutex_unlock(&priv->pie_mutex);
1620 return 0;
1621 }
1622
1623 static void rtl839x_pie_rule_rm(struct rtl838x_switch_priv *priv, struct pie_rule *pr)
1624 {
1625 int idx = pr->id;
1626
1627 rtl839x_pie_rule_del(priv, idx, idx);
1628 clear_bit(idx, priv->pie_use_bm);
1629 }
1630
1631 static void rtl839x_pie_init(struct rtl838x_switch_priv *priv)
1632 {
1633 int i;
1634 u32 template_selectors;
1635
1636 mutex_init(&priv->pie_mutex);
1637
1638 // Power on all PIE blocks
1639 for (i = 0; i < priv->n_pie_blocks; i++)
1640 sw_w32_mask(0, BIT(i), RTL839X_PS_ACL_PWR_CTRL);
1641
1642 // Set ingress and egress ACL blocks to 50/50: first Egress block is 9
1643 sw_w32_mask(0x1f, 9, RTL839X_ACL_CTRL); // Writes 9 to cutline field
1644
1645 // Include IPG in metering
1646 sw_w32(1, RTL839X_METER_GLB_CTRL);
1647
1648 // Delete all present rules
1649 rtl839x_pie_rule_del(priv, 0, priv->n_pie_blocks * PIE_BLOCK_SIZE - 1);
1650
1651 // Enable predefined templates 0, 1 for blocks 0-2
1652 template_selectors = 0 | (1 << 3);
1653 for (i = 0; i < 3; i++)
1654 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1655
1656 // Enable predefined templates 2, 3 for blocks 3-5
1657 template_selectors = 2 | (3 << 3);
1658 for (i = 3; i < 6; i++)
1659 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1660
1661 // Enable predefined templates 1, 4 for blocks 6-8
1662 template_selectors = 2 | (3 << 3);
1663 for (i = 6; i < 9; i++)
1664 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1665
1666 // Enable predefined templates 0, 1 for blocks 9-11
1667 template_selectors = 0 | (1 << 3);
1668 for (i = 9; i < 12; i++)
1669 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1670
1671 // Enable predefined templates 2, 3 for blocks 12-14
1672 template_selectors = 2 | (3 << 3);
1673 for (i = 12; i < 15; i++)
1674 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1675
1676 // Enable predefined templates 1, 4 for blocks 15-17
1677 template_selectors = 2 | (3 << 3);
1678 for (i = 15; i < 18; i++)
1679 sw_w32(template_selectors, RTL839X_ACL_BLK_TMPLTE_CTRL(i));
1680 }
1681
1682 static u32 rtl839x_packet_cntr_read(int counter)
1683 {
1684 u32 v;
1685
1686 // Read LOG table (4) via register RTL8390_TBL_0
1687 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 4);
1688
1689 pr_debug("In %s, id %d\n", __func__, counter);
1690 rtl_table_read(r, counter / 2);
1691
1692 // The table has a size of 2 registers
1693 if (counter % 2)
1694 v = sw_r32(rtl_table_data(r, 0));
1695 else
1696 v = sw_r32(rtl_table_data(r, 1));
1697
1698 rtl_table_release(r);
1699
1700 return v;
1701 }
1702
1703 static void rtl839x_packet_cntr_clear(int counter)
1704 {
1705 // Access LOG table (4) via register RTL8390_TBL_0
1706 struct table_reg *r = rtl_table_get(RTL8390_TBL_0, 4);
1707
1708 pr_debug("In %s, id %d\n", __func__, counter);
1709 // The table has a size of 2 registers
1710 if (counter % 2)
1711 sw_w32(0, rtl_table_data(r, 0));
1712 else
1713 sw_w32(0, rtl_table_data(r, 1));
1714
1715 rtl_table_write(r, counter / 2);
1716
1717 rtl_table_release(r);
1718 }
1719
1720 static void rtl839x_route_read(int idx, struct rtl83xx_route *rt)
1721 {
1722 u64 v;
1723 // Read ROUTING table (2) via register RTL8390_TBL_1
1724 struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 2);
1725
1726 pr_debug("In %s\n", __func__);
1727 rtl_table_read(r, idx);
1728
1729 // The table has a size of 2 registers
1730 v = sw_r32(rtl_table_data(r, 0));
1731 v <<= 32;
1732 v |= sw_r32(rtl_table_data(r, 1));
1733 rt->switch_mac_id = (v >> 12) & 0xf;
1734 rt->nh.gw = v >> 16;
1735
1736 rtl_table_release(r);
1737 }
1738
1739 static void rtl839x_route_write(int idx, struct rtl83xx_route *rt)
1740 {
1741 u32 v;
1742
1743 // Read ROUTING table (2) via register RTL8390_TBL_1
1744 struct table_reg *r = rtl_table_get(RTL8390_TBL_1, 2);
1745
1746 pr_debug("In %s\n", __func__);
1747 sw_w32(rt->nh.gw >> 16, rtl_table_data(r, 0));
1748 v = rt->nh.gw << 16;
1749 v |= rt->switch_mac_id << 12;
1750 sw_w32(v, rtl_table_data(r, 1));
1751 rtl_table_write(r, idx);
1752
1753 rtl_table_release(r);
1754 }
1755
1756 /*
1757 * Configure the switch's own MAC addresses used when routing packets
1758 */
1759 static void rtl839x_setup_port_macs(struct rtl838x_switch_priv *priv)
1760 {
1761 int i;
1762 struct net_device *dev;
1763 u64 mac;
1764
1765 pr_debug("%s: got port %08x\n", __func__, (u32)priv->ports[priv->cpu_port].dp);
1766 dev = priv->ports[priv->cpu_port].dp->slave;
1767 mac = ether_addr_to_u64(dev->dev_addr);
1768
1769 for (i = 0; i < 15; i++) {
1770 mac++; // BUG: VRRP for testing
1771 sw_w32(mac >> 32, RTL839X_ROUTING_SA_CTRL + i * 8);
1772 sw_w32(mac, RTL839X_ROUTING_SA_CTRL + i * 8 + 4);
1773 }
1774 }
1775
1776 int rtl839x_l3_setup(struct rtl838x_switch_priv *priv)
1777 {
1778 rtl839x_setup_port_macs(priv);
1779
1780 return 0;
1781 }
1782
1783 void rtl839x_vlan_port_keep_tag_set(int port, bool keep_outer, bool keep_inner)
1784 {
1785 sw_w32(FIELD_PREP(RTL839X_VLAN_PORT_TAG_STS_CTRL_OTAG_STS_MASK,
1786 keep_outer ? RTL839X_VLAN_PORT_TAG_STS_TAGGED : RTL839X_VLAN_PORT_TAG_STS_UNTAG) |
1787 FIELD_PREP(RTL839X_VLAN_PORT_TAG_STS_CTRL_ITAG_STS_MASK,
1788 keep_inner ? RTL839X_VLAN_PORT_TAG_STS_TAGGED : RTL839X_VLAN_PORT_TAG_STS_UNTAG),
1789 RTL839X_VLAN_PORT_TAG_STS_CTRL(port));
1790 }
1791
1792 void rtl839x_vlan_port_pvidmode_set(int port, enum pbvlan_type type, enum pbvlan_mode mode)
1793 {
1794 if (type == PBVLAN_TYPE_INNER)
1795 sw_w32_mask(0x3, mode, RTL839X_VLAN_PORT_PB_VLAN + (port << 2));
1796 else
1797 sw_w32_mask(0x3 << 14, mode << 14, RTL839X_VLAN_PORT_PB_VLAN + (port << 2));
1798 }
1799
1800 void rtl839x_vlan_port_pvid_set(int port, enum pbvlan_type type, int pvid)
1801 {
1802 if (type == PBVLAN_TYPE_INNER)
1803 sw_w32_mask(0xfff << 2, pvid << 2, RTL839X_VLAN_PORT_PB_VLAN + (port << 2));
1804 else
1805 sw_w32_mask(0xfff << 16, pvid << 16, RTL839X_VLAN_PORT_PB_VLAN + (port << 2));
1806 }
1807
1808 static int rtl839x_set_ageing_time(unsigned long msec)
1809 {
1810 int t = sw_r32(RTL839X_L2_CTRL_1);
1811
1812 t &= 0x1FFFFF;
1813 t = t * 3 / 5; /* Aging time in seconds. 0: L2 aging disabled */
1814 pr_debug("L2 AGING time: %d sec\n", t);
1815
1816 t = (msec * 5 + 2000) / 3000;
1817 t = t > 0x1FFFFF ? 0x1FFFFF : t;
1818 sw_w32_mask(0x1FFFFF, t, RTL839X_L2_CTRL_1);
1819 pr_debug("Dynamic aging for ports: %x\n", sw_r32(RTL839X_L2_PORT_AGING_OUT));
1820
1821 return 0;
1822 }
1823
1824 static void rtl839x_set_igr_filter(int port, enum igr_filter state)
1825 {
1826 sw_w32_mask(0x3 << ((port & 0xf)<<1), state << ((port & 0xf)<<1),
1827 RTL839X_VLAN_PORT_IGR_FLTR + (((port >> 4) << 2)));
1828 }
1829
1830 static void rtl839x_set_egr_filter(int port, enum egr_filter state)
1831 {
1832 sw_w32_mask(0x1 << (port % 0x20), state << (port % 0x20),
1833 RTL839X_VLAN_PORT_EGR_FLTR + (((port >> 5) << 2)));
1834 }
1835
1836 void rtl839x_set_distribution_algorithm(int group, int algoidx, u32 algomsk)
1837 {
1838 sw_w32_mask(3 << ((group & 0xf) << 1), algoidx << ((group & 0xf) << 1),
1839 RTL839X_TRK_HASH_IDX_CTRL + ((group >> 4) << 2));
1840 sw_w32(algomsk, RTL839X_TRK_HASH_CTRL + (algoidx << 2));
1841 }
1842
1843 void rtl839x_set_receive_management_action(int port, rma_ctrl_t type, action_type_t action)
1844 {
1845 switch(type) {
1846 case BPDU:
1847 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1848 RTL839X_RMA_BPDU_CTRL + ((port >> 4) << 2));
1849 break;
1850 case PTP:
1851 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1852 RTL839X_RMA_PTP_CTRL + ((port >> 4) << 2));
1853 break;
1854 case LLTP:
1855 sw_w32_mask(3 << ((port & 0xf) << 1), (action & 0x3) << ((port & 0xf) << 1),
1856 RTL839X_RMA_LLTP_CTRL + ((port >> 4) << 2));
1857 break;
1858 default:
1859 break;
1860 }
1861 }
1862
1863 const struct rtl838x_reg rtl839x_reg = {
1864 .mask_port_reg_be = rtl839x_mask_port_reg_be,
1865 .set_port_reg_be = rtl839x_set_port_reg_be,
1866 .get_port_reg_be = rtl839x_get_port_reg_be,
1867 .mask_port_reg_le = rtl839x_mask_port_reg_le,
1868 .set_port_reg_le = rtl839x_set_port_reg_le,
1869 .get_port_reg_le = rtl839x_get_port_reg_le,
1870 .stat_port_rst = RTL839X_STAT_PORT_RST,
1871 .stat_rst = RTL839X_STAT_RST,
1872 .stat_port_std_mib = RTL839X_STAT_PORT_STD_MIB,
1873 .traffic_enable = rtl839x_traffic_enable,
1874 .traffic_disable = rtl839x_traffic_disable,
1875 .traffic_get = rtl839x_traffic_get,
1876 .traffic_set = rtl839x_traffic_set,
1877 .port_iso_ctrl = rtl839x_port_iso_ctrl,
1878 .l2_ctrl_0 = RTL839X_L2_CTRL_0,
1879 .l2_ctrl_1 = RTL839X_L2_CTRL_1,
1880 .l2_port_aging_out = RTL839X_L2_PORT_AGING_OUT,
1881 .set_ageing_time = rtl839x_set_ageing_time,
1882 .smi_poll_ctrl = RTL839X_SMI_PORT_POLLING_CTRL,
1883 .l2_tbl_flush_ctrl = RTL839X_L2_TBL_FLUSH_CTRL,
1884 .exec_tbl0_cmd = rtl839x_exec_tbl0_cmd,
1885 .exec_tbl1_cmd = rtl839x_exec_tbl1_cmd,
1886 .tbl_access_data_0 = rtl839x_tbl_access_data_0,
1887 .isr_glb_src = RTL839X_ISR_GLB_SRC,
1888 .isr_port_link_sts_chg = RTL839X_ISR_PORT_LINK_STS_CHG,
1889 .imr_port_link_sts_chg = RTL839X_IMR_PORT_LINK_STS_CHG,
1890 .imr_glb = RTL839X_IMR_GLB,
1891 .vlan_tables_read = rtl839x_vlan_tables_read,
1892 .vlan_set_tagged = rtl839x_vlan_set_tagged,
1893 .vlan_set_untagged = rtl839x_vlan_set_untagged,
1894 .vlan_profile_dump = rtl839x_vlan_profile_dump,
1895 .vlan_profile_setup = rtl839x_vlan_profile_setup,
1896 .vlan_fwd_on_inner = rtl839x_vlan_fwd_on_inner,
1897 .vlan_port_keep_tag_set = rtl839x_vlan_port_keep_tag_set,
1898 .vlan_port_pvidmode_set = rtl839x_vlan_port_pvidmode_set,
1899 .vlan_port_pvid_set = rtl839x_vlan_port_pvid_set,
1900 .set_vlan_igr_filter = rtl839x_set_igr_filter,
1901 .set_vlan_egr_filter = rtl839x_set_egr_filter,
1902 .enable_learning = rtl839x_enable_learning,
1903 .enable_flood = rtl839x_enable_flood,
1904 .enable_mcast_flood = rtl839x_enable_mcast_flood,
1905 .enable_bcast_flood = rtl839x_enable_bcast_flood,
1906 .set_static_move_action = rtl839x_set_static_move_action,
1907 .stp_get = rtl839x_stp_get,
1908 .stp_set = rtl839x_stp_set,
1909 .mac_force_mode_ctrl = rtl839x_mac_force_mode_ctrl,
1910 .mac_port_ctrl = rtl839x_mac_port_ctrl,
1911 .l2_port_new_salrn = rtl839x_l2_port_new_salrn,
1912 .l2_port_new_sa_fwd = rtl839x_l2_port_new_sa_fwd,
1913 .mir_ctrl = RTL839X_MIR_CTRL,
1914 .mir_dpm = RTL839X_MIR_DPM_CTRL,
1915 .mir_spm = RTL839X_MIR_SPM_CTRL,
1916 .mac_link_sts = RTL839X_MAC_LINK_STS,
1917 .mac_link_dup_sts = RTL839X_MAC_LINK_DUP_STS,
1918 .mac_link_spd_sts = rtl839x_mac_link_spd_sts,
1919 .mac_rx_pause_sts = RTL839X_MAC_RX_PAUSE_STS,
1920 .mac_tx_pause_sts = RTL839X_MAC_TX_PAUSE_STS,
1921 .read_l2_entry_using_hash = rtl839x_read_l2_entry_using_hash,
1922 .write_l2_entry_using_hash = rtl839x_write_l2_entry_using_hash,
1923 .read_cam = rtl839x_read_cam,
1924 .write_cam = rtl839x_write_cam,
1925 .trk_mbr_ctr = rtl839x_trk_mbr_ctr,
1926 .rma_bpdu_fld_pmask = RTL839X_RMA_BPDU_FLD_PMSK,
1927 .spcl_trap_eapol_ctrl = RTL839X_SPCL_TRAP_EAPOL_CTRL,
1928 .init_eee = rtl839x_init_eee,
1929 .port_eee_set = rtl839x_port_eee_set,
1930 .eee_port_ability = rtl839x_eee_port_ability,
1931 .l2_hash_seed = rtl839x_l2_hash_seed,
1932 .l2_hash_key = rtl839x_l2_hash_key,
1933 .read_mcast_pmask = rtl839x_read_mcast_pmask,
1934 .write_mcast_pmask = rtl839x_write_mcast_pmask,
1935 .pie_init = rtl839x_pie_init,
1936 .pie_rule_read = rtl839x_pie_rule_read,
1937 .pie_rule_write = rtl839x_pie_rule_write,
1938 .pie_rule_add = rtl839x_pie_rule_add,
1939 .pie_rule_rm = rtl839x_pie_rule_rm,
1940 .l2_learning_setup = rtl839x_l2_learning_setup,
1941 .packet_cntr_read = rtl839x_packet_cntr_read,
1942 .packet_cntr_clear = rtl839x_packet_cntr_clear,
1943 .route_read = rtl839x_route_read,
1944 .route_write = rtl839x_route_write,
1945 .l3_setup = rtl839x_l3_setup,
1946 .set_distribution_algorithm = rtl839x_set_distribution_algorithm,
1947 .set_receive_management_action = rtl839x_set_receive_management_action,
1948 };
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