apm821xx: remove 4.4 kernel support

[openwrt/staging/lynxis/omap.git] / target / linux / apm821xx / patches-4.4 / 300-fix-atheros-nics-on-apm82181.patch

diff --git a/target/linux/apm821xx/patches-4.4/300-fix-atheros-nics-on-apm82181.patch b/target/linux/apm821xx/patches-4.4/300-fix-atheros-nics-on-apm82181.patch
deleted file mode 100644 (file)
index 0b1affc..0000000
--- a/target/linux/apm821xx/patches-4.4/300-fix-atheros-nics-on-apm82181.patch
+++ /dev/null
@@ -1,51 +0,0 @@
---- a/arch/powerpc/sysdev/ppc4xx_pci.c
-+++ b/arch/powerpc/sysdev/ppc4xx_pci.c
-@@ -1066,15 +1066,24 @@ static int __init apm821xx_pciex_init_po
-       u32 val;
- 
-       /*
--       * Do a software reset on PCIe ports.
--       * This code is to fix the issue that pci drivers doesn't re-assign
--       * bus number for PCIE devices after Uboot
--       * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
--       * PT quad port, SAS LSI 1064E)
-+       * Only reset the PHY when no link is currently established.
-+       * This is for the Atheros PCIe board which has problems to establish
-+       * the link (again) after this PHY reset. All other currently tested
-+       * PCIe boards don't show this problem.
-        */
--
--      mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
--      mdelay(10);
-+      val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
-+      if (!(val & 0x00001000)) {
-+              /*
-+               * Do a software reset on PCIe ports.
-+               * This code is to fix the issue that pci drivers doesn't re-assign
-+               * bus number for PCIE devices after Uboot
-+               * scanned and configured all the buses (eg. PCIE NIC IntelPro/1000
-+               * PT quad port, SAS LSI 1064E)
-+               */
-+
-+              mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x0);
-+              mdelay(10);
-+      }
- 
-       if (port->endpoint)
-               val = PTYPE_LEGACY_ENDPOINT << 20;
-@@ -1091,9 +1100,12 @@ static int __init apm821xx_pciex_init_po
-       mtdcri(SDR0, PESDR0_460EX_L0DRV, 0x00000130);
-       mtdcri(SDR0, PESDR0_460EX_L0CLK, 0x00000006);
- 
--      mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
--      mdelay(50);
--      mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
-+      val = mfdcri(SDR0, port->sdr_base + PESDRn_LOOP);
-+      if (!(val & 0x00001000)) {
-+              mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x10000000);
-+              mdelay(50);
-+              mtdcri(SDR0, PESDR0_460EX_PHY_CTL_RST, 0x30000000);
-+      }
- 
-       mtdcri(SDR0, port->sdr_base + PESDRn_RCSSET,
-               mfdcri(SDR0, port->sdr_base + PESDRn_RCSSET) |