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ramips: fix NAND flash driver ECC bit position mask
[openwrt/staging/mkresin.git] / target / linux / ath25 / patches-5.4 / 110-ar2313_ethernet.patch
1 --- a/drivers/net/ethernet/atheros/Makefile
2 +++ b/drivers/net/ethernet/atheros/Makefile
3 @@ -9,3 +9,4 @@ obj-$(CONFIG_ATL2) += atlx/
4 obj-$(CONFIG_ATL1E) += atl1e/
5 obj-$(CONFIG_ATL1C) += atl1c/
6 obj-$(CONFIG_ALX) += alx/
7 +obj-$(CONFIG_NET_AR231X) += ar231x/
8 --- a/drivers/net/ethernet/atheros/Kconfig
9 +++ b/drivers/net/ethernet/atheros/Kconfig
10 @@ -6,7 +6,7 @@
11 config NET_VENDOR_ATHEROS
12 bool "Atheros devices"
13 default y
14 - depends on (PCI || ATH79)
15 + depends on (PCI || ATH25 || ATH79)
16 ---help---
17 If you have a network (Ethernet) card belonging to this class, say Y.
18
19 @@ -87,4 +87,10 @@ config ALX
20 To compile this driver as a module, choose M here. The module
21 will be called alx.
22
23 +config NET_AR231X
24 + tristate "Atheros AR231X built-in Ethernet support"
25 + depends on ATH25
26 + help
27 + Support for the AR231x/531x ethernet controller
28 +
29 endif # NET_VENDOR_ATHEROS
30 --- /dev/null
31 +++ b/drivers/net/ethernet/atheros/ar231x/Makefile
32 @@ -0,0 +1 @@
33 +obj-$(CONFIG_NET_AR231X) += ar231x.o
34 --- /dev/null
35 +++ b/drivers/net/ethernet/atheros/ar231x/ar231x.c
36 @@ -0,0 +1,1120 @@
37 +/*
38 + * ar231x.c: Linux driver for the Atheros AR231x Ethernet device.
39 + *
40 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
41 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
42 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@nbd.name>
43 + *
44 + * Thanks to Atheros for providing hardware and documentation
45 + * enabling me to write this driver.
46 + *
47 + * This program is free software; you can redistribute it and/or modify
48 + * it under the terms of the GNU General Public License as published by
49 + * the Free Software Foundation; either version 2 of the License, or
50 + * (at your option) any later version.
51 + *
52 + * Additional credits:
53 + * This code is taken from John Taylor's Sibyte driver and then
54 + * modified for the AR2313.
55 + */
56 +
57 +#include <linux/module.h>
58 +#include <linux/types.h>
59 +#include <linux/errno.h>
60 +#include <linux/ioport.h>
61 +#include <linux/netdevice.h>
62 +#include <linux/etherdevice.h>
63 +#include <linux/interrupt.h>
64 +#include <linux/skbuff.h>
65 +#include <linux/init.h>
66 +#include <linux/delay.h>
67 +#include <linux/mm.h>
68 +#include <linux/mii.h>
69 +#include <linux/phy.h>
70 +#include <linux/platform_device.h>
71 +#include <linux/io.h>
72 +
73 +#define AR2313_MTU 1692
74 +#define AR2313_PRIOS 1
75 +#define AR2313_QUEUES (2*AR2313_PRIOS)
76 +#define AR2313_DESCR_ENTRIES 64
77 +
78 +#ifndef min
79 +#define min(a, b) (((a) < (b)) ? (a) : (b))
80 +#endif
81 +
82 +#ifndef SMP_CACHE_BYTES
83 +#define SMP_CACHE_BYTES L1_CACHE_BYTES
84 +#endif
85 +
86 +#define AR2313_MBOX_SET_BIT 0x8
87 +
88 +#include "ar231x.h"
89 +
90 +/**
91 + * New interrupt handler strategy:
92 + *
93 + * An old interrupt handler worked using the traditional method of
94 + * replacing an skbuff with a new one when a packet arrives. However
95 + * the rx rings do not need to contain a static number of buffer
96 + * descriptors, thus it makes sense to move the memory allocation out
97 + * of the main interrupt handler and do it in a bottom half handler
98 + * and only allocate new buffers when the number of buffers in the
99 + * ring is below a certain threshold. In order to avoid starving the
100 + * NIC under heavy load it is however necessary to force allocation
101 + * when hitting a minimum threshold. The strategy for alloction is as
102 + * follows:
103 + *
104 + * RX_LOW_BUF_THRES - allocate buffers in the bottom half
105 + * RX_PANIC_LOW_THRES - we are very low on buffers, allocate
106 + * the buffers in the interrupt handler
107 + * RX_RING_THRES - maximum number of buffers in the rx ring
108 + *
109 + * One advantagous side effect of this allocation approach is that the
110 + * entire rx processing can be done without holding any spin lock
111 + * since the rx rings and registers are totally independent of the tx
112 + * ring and its registers. This of course includes the kmalloc's of
113 + * new skb's. Thus start_xmit can run in parallel with rx processing
114 + * and the memory allocation on SMP systems.
115 + *
116 + * Note that running the skb reallocation in a bottom half opens up
117 + * another can of races which needs to be handled properly. In
118 + * particular it can happen that the interrupt handler tries to run
119 + * the reallocation while the bottom half is either running on another
120 + * CPU or was interrupted on the same CPU. To get around this the
121 + * driver uses bitops to prevent the reallocation routines from being
122 + * reentered.
123 + *
124 + * TX handling can also be done without holding any spin lock, wheee
125 + * this is fun! since tx_csm is only written to by the interrupt
126 + * handler.
127 + */
128 +
129 +/**
130 + * Threshold values for RX buffer allocation - the low water marks for
131 + * when to start refilling the rings are set to 75% of the ring
132 + * sizes. It seems to make sense to refill the rings entirely from the
133 + * intrrupt handler once it gets below the panic threshold, that way
134 + * we don't risk that the refilling is moved to another CPU when the
135 + * one running the interrupt handler just got the slab code hot in its
136 + * cache.
137 + */
138 +#define RX_RING_SIZE AR2313_DESCR_ENTRIES
139 +#define RX_PANIC_THRES (RX_RING_SIZE/4)
140 +#define RX_LOW_THRES ((3*RX_RING_SIZE)/4)
141 +#define CRC_LEN 4
142 +#define RX_OFFSET 2
143 +
144 +#if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
145 +#define VLAN_HDR 4
146 +#else
147 +#define VLAN_HDR 0
148 +#endif
149 +
150 +#define AR2313_BUFSIZE (AR2313_MTU + VLAN_HDR + ETH_HLEN + CRC_LEN + \
151 + RX_OFFSET)
152 +
153 +#ifdef MODULE
154 +MODULE_LICENSE("GPL");
155 +MODULE_AUTHOR("Sameer Dekate <sdekate@arubanetworks.com>, Imre Kaloz <kaloz@openwrt.org>, Felix Fietkau <nbd@nbd.name>");
156 +MODULE_DESCRIPTION("AR231x Ethernet driver");
157 +#endif
158 +
159 +#define virt_to_phys(x) ((u32)(x) & 0x1fffffff)
160 +
161 +/* prototypes */
162 +static void ar231x_halt(struct net_device *dev);
163 +static void rx_tasklet_func(unsigned long data);
164 +static void rx_tasklet_cleanup(struct net_device *dev);
165 +static void ar231x_multicast_list(struct net_device *dev);
166 +static void ar231x_tx_timeout(struct net_device *dev);
167 +
168 +static int ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum);
169 +static int ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum,
170 + u16 value);
171 +static int ar231x_mdiobus_reset(struct mii_bus *bus);
172 +static int ar231x_mdiobus_probe(struct net_device *dev);
173 +static void ar231x_adjust_link(struct net_device *dev);
174 +
175 +#ifndef ERR
176 +#define ERR(fmt, args...) printk("%s: " fmt, __func__, ##args)
177 +#endif
178 +
179 +#ifdef CONFIG_NET_POLL_CONTROLLER
180 +static void
181 +ar231x_netpoll(struct net_device *dev)
182 +{
183 + unsigned long flags;
184 +
185 + local_irq_save(flags);
186 + ar231x_interrupt(dev->irq, dev);
187 + local_irq_restore(flags);
188 +}
189 +#endif
190 +
191 +static const struct net_device_ops ar231x_ops = {
192 + .ndo_open = ar231x_open,
193 + .ndo_stop = ar231x_close,
194 + .ndo_start_xmit = ar231x_start_xmit,
195 + .ndo_set_rx_mode = ar231x_multicast_list,
196 + .ndo_do_ioctl = ar231x_ioctl,
197 + .ndo_change_mtu = eth_change_mtu,
198 + .ndo_validate_addr = eth_validate_addr,
199 + .ndo_set_mac_address = eth_mac_addr,
200 + .ndo_tx_timeout = ar231x_tx_timeout,
201 +#ifdef CONFIG_NET_POLL_CONTROLLER
202 + .ndo_poll_controller = ar231x_netpoll,
203 +#endif
204 +};
205 +
206 +static int ar231x_probe(struct platform_device *pdev)
207 +{
208 + struct net_device *dev;
209 + struct ar231x_private *sp;
210 + struct resource *res;
211 + unsigned long ar_eth_base;
212 + char buf[64];
213 +
214 + dev = alloc_etherdev(sizeof(struct ar231x_private));
215 +
216 + if (dev == NULL) {
217 + printk(KERN_ERR
218 + "ar231x: Unable to allocate net_device structure!\n");
219 + return -ENOMEM;
220 + }
221 +
222 + platform_set_drvdata(pdev, dev);
223 +
224 + SET_NETDEV_DEV(dev, &pdev->dev);
225 +
226 + sp = netdev_priv(dev);
227 + sp->dev = dev;
228 + sp->pdev = pdev;
229 + sp->cfg = pdev->dev.platform_data;
230 +
231 + sprintf(buf, "eth%d_membase", pdev->id);
232 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, buf);
233 + if (!res)
234 + return -ENODEV;
235 +
236 + sp->link = 0;
237 + ar_eth_base = res->start;
238 +
239 + sprintf(buf, "eth%d_irq", pdev->id);
240 + dev->irq = platform_get_irq_byname(pdev, buf);
241 +
242 + spin_lock_init(&sp->lock);
243 +
244 + dev->features |= NETIF_F_HIGHDMA;
245 + dev->netdev_ops = &ar231x_ops;
246 +
247 + tasklet_init(&sp->rx_tasklet, rx_tasklet_func, (unsigned long)dev);
248 + tasklet_disable(&sp->rx_tasklet);
249 +
250 + sp->eth_regs = ioremap_nocache(ar_eth_base, sizeof(*sp->eth_regs));
251 + if (!sp->eth_regs) {
252 + printk("Can't remap eth registers\n");
253 + return -ENXIO;
254 + }
255 +
256 + /**
257 + * When there's only one MAC, PHY regs are typically on ENET0,
258 + * even though the MAC might be on ENET1.
259 + * So remap PHY regs separately.
260 + */
261 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "eth0_mii");
262 + if (!res) {
263 + res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
264 + "eth1_mii");
265 + if (!res)
266 + return -ENODEV;
267 + }
268 + sp->phy_regs = ioremap_nocache(res->start, resource_size(res));
269 + if (!sp->phy_regs) {
270 + printk("Can't remap phy registers\n");
271 + return -ENXIO;
272 + }
273 +
274 + sp->dma_regs = ioremap_nocache(ar_eth_base + 0x1000,
275 + sizeof(*sp->dma_regs));
276 + if (!sp->dma_regs) {
277 + printk("Can't remap DMA registers\n");
278 + return -ENXIO;
279 + }
280 + dev->base_addr = ar_eth_base + 0x1000;
281 +
282 + strncpy(sp->name, "Atheros AR231x", sizeof(sp->name) - 1);
283 + sp->name[sizeof(sp->name) - 1] = '\0';
284 + memcpy(dev->dev_addr, sp->cfg->macaddr, 6);
285 +
286 + if (ar231x_init(dev)) {
287 + /* ar231x_init() calls ar231x_init_cleanup() on error */
288 + kfree(dev);
289 + return -ENODEV;
290 + }
291 +
292 + if (register_netdev(dev)) {
293 + printk("%s: register_netdev failed\n", __func__);
294 + return -1;
295 + }
296 +
297 + printk("%s: %s: %pM, irq %d\n", dev->name, sp->name, dev->dev_addr,
298 + dev->irq);
299 +
300 + sp->mii_bus = mdiobus_alloc();
301 + if (sp->mii_bus == NULL)
302 + return -1;
303 +
304 + sp->mii_bus->priv = dev;
305 + sp->mii_bus->read = ar231x_mdiobus_read;
306 + sp->mii_bus->write = ar231x_mdiobus_write;
307 + sp->mii_bus->reset = ar231x_mdiobus_reset;
308 + sp->mii_bus->name = "ar231x_eth_mii";
309 + snprintf(sp->mii_bus->id, MII_BUS_ID_SIZE, "%d", pdev->id);
310 +
311 + mdiobus_register(sp->mii_bus);
312 +
313 + if (ar231x_mdiobus_probe(dev) != 0) {
314 + printk(KERN_ERR "%s: mdiobus_probe failed\n", dev->name);
315 + rx_tasklet_cleanup(dev);
316 + ar231x_init_cleanup(dev);
317 + unregister_netdev(dev);
318 + kfree(dev);
319 + return -ENODEV;
320 + }
321 +
322 + return 0;
323 +}
324 +
325 +static void ar231x_multicast_list(struct net_device *dev)
326 +{
327 + struct ar231x_private *sp = netdev_priv(dev);
328 + unsigned int filter;
329 +
330 + filter = sp->eth_regs->mac_control;
331 +
332 + if (dev->flags & IFF_PROMISC)
333 + filter |= MAC_CONTROL_PR;
334 + else
335 + filter &= ~MAC_CONTROL_PR;
336 + if ((dev->flags & IFF_ALLMULTI) || (netdev_mc_count(dev) > 0))
337 + filter |= MAC_CONTROL_PM;
338 + else
339 + filter &= ~MAC_CONTROL_PM;
340 +
341 + sp->eth_regs->mac_control = filter;
342 +}
343 +
344 +static void rx_tasklet_cleanup(struct net_device *dev)
345 +{
346 + struct ar231x_private *sp = netdev_priv(dev);
347 +
348 + /**
349 + * Tasklet may be scheduled. Need to get it removed from the list
350 + * since we're about to free the struct.
351 + */
352 +
353 + sp->unloading = 1;
354 + tasklet_enable(&sp->rx_tasklet);
355 + tasklet_kill(&sp->rx_tasklet);
356 +}
357 +
358 +static int ar231x_remove(struct platform_device *pdev)
359 +{
360 + struct net_device *dev = platform_get_drvdata(pdev);
361 + struct ar231x_private *sp = netdev_priv(dev);
362 +
363 + rx_tasklet_cleanup(dev);
364 + ar231x_init_cleanup(dev);
365 + unregister_netdev(dev);
366 + mdiobus_unregister(sp->mii_bus);
367 + mdiobus_free(sp->mii_bus);
368 + kfree(dev);
369 + return 0;
370 +}
371 +
372 +/**
373 + * Restart the AR2313 ethernet controller.
374 + */
375 +static int ar231x_restart(struct net_device *dev)
376 +{
377 + /* disable interrupts */
378 + disable_irq(dev->irq);
379 +
380 + /* stop mac */
381 + ar231x_halt(dev);
382 +
383 + /* initialize */
384 + ar231x_init(dev);
385 +
386 + /* enable interrupts */
387 + enable_irq(dev->irq);
388 +
389 + return 0;
390 +}
391 +
392 +static struct platform_driver ar231x_driver = {
393 + .driver.name = "ar231x-eth",
394 + .probe = ar231x_probe,
395 + .remove = ar231x_remove,
396 +};
397 +
398 +module_platform_driver(ar231x_driver);
399 +
400 +static void ar231x_free_descriptors(struct net_device *dev)
401 +{
402 + struct ar231x_private *sp = netdev_priv(dev);
403 +
404 + if (sp->rx_ring != NULL) {
405 + kfree((void *)KSEG0ADDR(sp->rx_ring));
406 + sp->rx_ring = NULL;
407 + sp->tx_ring = NULL;
408 + }
409 +}
410 +
411 +static int ar231x_allocate_descriptors(struct net_device *dev)
412 +{
413 + struct ar231x_private *sp = netdev_priv(dev);
414 + int size;
415 + int j;
416 + ar231x_descr_t *space;
417 +
418 + if (sp->rx_ring != NULL) {
419 + printk("%s: already done.\n", __func__);
420 + return 0;
421 + }
422 +
423 + size = sizeof(ar231x_descr_t) * (AR2313_DESCR_ENTRIES * AR2313_QUEUES);
424 + space = kmalloc(size, GFP_KERNEL);
425 + if (space == NULL)
426 + return 1;
427 +
428 + /* invalidate caches */
429 + dma_cache_inv((unsigned int)space, size);
430 +
431 + /* now convert pointer to KSEG1 */
432 + space = (ar231x_descr_t *)KSEG1ADDR(space);
433 +
434 + memset((void *)space, 0, size);
435 +
436 + sp->rx_ring = space;
437 + space += AR2313_DESCR_ENTRIES;
438 +
439 + sp->tx_ring = space;
440 + space += AR2313_DESCR_ENTRIES;
441 +
442 + /* Initialize the transmit Descriptors */
443 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
444 + ar231x_descr_t *td = &sp->tx_ring[j];
445 +
446 + td->status = 0;
447 + td->devcs = DMA_TX1_CHAINED;
448 + td->addr = 0;
449 + td->descr = virt_to_phys(&sp->tx_ring[DSC_NEXT(j)]);
450 + }
451 +
452 + return 0;
453 +}
454 +
455 +/**
456 + * Generic cleanup handling data allocated during init. Used when the
457 + * module is unloaded or if an error occurs during initialization
458 + */
459 +static void ar231x_init_cleanup(struct net_device *dev)
460 +{
461 + struct ar231x_private *sp = netdev_priv(dev);
462 + struct sk_buff *skb;
463 + int j;
464 +
465 + ar231x_free_descriptors(dev);
466 +
467 + if (sp->eth_regs)
468 + iounmap((void *)sp->eth_regs);
469 + if (sp->dma_regs)
470 + iounmap((void *)sp->dma_regs);
471 + if (sp->phy_regs)
472 + iounmap((void *)sp->phy_regs);
473 +
474 + if (sp->rx_skb) {
475 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
476 + skb = sp->rx_skb[j];
477 + if (skb) {
478 + sp->rx_skb[j] = NULL;
479 + dev_kfree_skb(skb);
480 + }
481 + }
482 + kfree(sp->rx_skb);
483 + sp->rx_skb = NULL;
484 + }
485 +
486 + if (sp->tx_skb) {
487 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
488 + skb = sp->tx_skb[j];
489 + if (skb) {
490 + sp->tx_skb[j] = NULL;
491 + dev_kfree_skb(skb);
492 + }
493 + }
494 + kfree(sp->tx_skb);
495 + sp->tx_skb = NULL;
496 + }
497 +}
498 +
499 +static int ar231x_reset_reg(struct net_device *dev)
500 +{
501 + struct ar231x_private *sp = netdev_priv(dev);
502 + unsigned int ethsal, ethsah;
503 + unsigned int flags;
504 +
505 + sp->cfg->reset_set(sp->cfg->reset_mac);
506 + mdelay(10);
507 + sp->cfg->reset_clear(sp->cfg->reset_mac);
508 + mdelay(10);
509 + sp->cfg->reset_set(sp->cfg->reset_phy);
510 + mdelay(10);
511 + sp->cfg->reset_clear(sp->cfg->reset_phy);
512 + mdelay(10);
513 +
514 + sp->dma_regs->bus_mode = (DMA_BUS_MODE_SWR);
515 + mdelay(10);
516 + sp->dma_regs->bus_mode =
517 + ((32 << DMA_BUS_MODE_PBL_SHIFT) | DMA_BUS_MODE_BLE);
518 +
519 + /* enable interrupts */
520 + sp->dma_regs->intr_ena = DMA_STATUS_AIS | DMA_STATUS_NIS |
521 + DMA_STATUS_RI | DMA_STATUS_TI |
522 + DMA_STATUS_FBE;
523 + sp->dma_regs->xmt_base = virt_to_phys(sp->tx_ring);
524 + sp->dma_regs->rcv_base = virt_to_phys(sp->rx_ring);
525 + sp->dma_regs->control =
526 + (DMA_CONTROL_SR | DMA_CONTROL_ST | DMA_CONTROL_SF);
527 +
528 + sp->eth_regs->flow_control = (FLOW_CONTROL_FCE);
529 + sp->eth_regs->vlan_tag = (0x8100);
530 +
531 + /* Enable Ethernet Interface */
532 + flags = (MAC_CONTROL_TE | /* transmit enable */
533 + MAC_CONTROL_PM | /* pass mcast */
534 + MAC_CONTROL_F | /* full duplex */
535 + MAC_CONTROL_HBD); /* heart beat disabled */
536 +
537 + if (dev->flags & IFF_PROMISC) { /* set promiscuous mode */
538 + flags |= MAC_CONTROL_PR;
539 + }
540 + sp->eth_regs->mac_control = flags;
541 +
542 + /* Set all Ethernet station address registers to their initial values */
543 + ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
544 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
545 +
546 + ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
547 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
548 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
549 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
550 +
551 + sp->eth_regs->mac_addr[0] = ethsah;
552 + sp->eth_regs->mac_addr[1] = ethsal;
553 +
554 + mdelay(10);
555 +
556 + return 0;
557 +}
558 +
559 +static int ar231x_init(struct net_device *dev)
560 +{
561 + struct ar231x_private *sp = netdev_priv(dev);
562 + int ecode = 0;
563 +
564 + /* Allocate descriptors */
565 + if (ar231x_allocate_descriptors(dev)) {
566 + printk("%s: %s: ar231x_allocate_descriptors failed\n",
567 + dev->name, __func__);
568 + ecode = -EAGAIN;
569 + goto init_error;
570 + }
571 +
572 + /* Get the memory for the skb rings */
573 + if (sp->rx_skb == NULL) {
574 + sp->rx_skb =
575 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
576 + GFP_KERNEL);
577 + if (!(sp->rx_skb)) {
578 + printk("%s: %s: rx_skb kmalloc failed\n",
579 + dev->name, __func__);
580 + ecode = -EAGAIN;
581 + goto init_error;
582 + }
583 + }
584 + memset(sp->rx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
585 +
586 + if (sp->tx_skb == NULL) {
587 + sp->tx_skb =
588 + kmalloc(sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES,
589 + GFP_KERNEL);
590 + if (!(sp->tx_skb)) {
591 + printk("%s: %s: tx_skb kmalloc failed\n",
592 + dev->name, __func__);
593 + ecode = -EAGAIN;
594 + goto init_error;
595 + }
596 + }
597 + memset(sp->tx_skb, 0, sizeof(struct sk_buff *) * AR2313_DESCR_ENTRIES);
598 +
599 + /**
600 + * Set tx_csm before we start receiving interrupts, otherwise
601 + * the interrupt handler might think it is supposed to process
602 + * tx ints before we are up and running, which may cause a null
603 + * pointer access in the int handler.
604 + */
605 + sp->rx_skbprd = 0;
606 + sp->cur_rx = 0;
607 + sp->tx_prd = 0;
608 + sp->tx_csm = 0;
609 +
610 + /* Zero the stats before starting the interface */
611 + memset(&dev->stats, 0, sizeof(dev->stats));
612 +
613 + /**
614 + * We load the ring here as there seem to be no way to tell the
615 + * firmware to wipe the ring without re-initializing it.
616 + */
617 + ar231x_load_rx_ring(dev, RX_RING_SIZE);
618 +
619 + /* Init hardware */
620 + ar231x_reset_reg(dev);
621 +
622 + /* Get the IRQ */
623 + ecode = request_irq(dev->irq, &ar231x_interrupt, 0,
624 + dev->name, dev);
625 + if (ecode) {
626 + printk(KERN_WARNING "%s: %s: Requested IRQ %d is busy\n",
627 + dev->name, __func__, dev->irq);
628 + goto init_error;
629 + }
630 +
631 + tasklet_enable(&sp->rx_tasklet);
632 +
633 + return 0;
634 +
635 +init_error:
636 + ar231x_init_cleanup(dev);
637 + return ecode;
638 +}
639 +
640 +/**
641 + * Load the rx ring.
642 + *
643 + * Loading rings is safe without holding the spin lock since this is
644 + * done only before the device is enabled, thus no interrupts are
645 + * generated and by the interrupt handler/tasklet handler.
646 + */
647 +static void ar231x_load_rx_ring(struct net_device *dev, int nr_bufs)
648 +{
649 + struct ar231x_private *sp = netdev_priv(dev);
650 + short i, idx;
651 +
652 + idx = sp->rx_skbprd;
653 +
654 + for (i = 0; i < nr_bufs; i++) {
655 + struct sk_buff *skb;
656 + ar231x_descr_t *rd;
657 +
658 + if (sp->rx_skb[idx])
659 + break;
660 +
661 + skb = netdev_alloc_skb_ip_align(dev, AR2313_BUFSIZE);
662 + if (!skb) {
663 + printk("\n\n\n\n %s: No memory in system\n\n\n\n",
664 + __func__);
665 + break;
666 + }
667 +
668 + /* Make sure IP header starts on a fresh cache line */
669 + skb->dev = dev;
670 + sp->rx_skb[idx] = skb;
671 +
672 + rd = (ar231x_descr_t *)&sp->rx_ring[idx];
673 +
674 + /* initialize dma descriptor */
675 + rd->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
676 + DMA_RX1_CHAINED);
677 + rd->addr = virt_to_phys(skb->data);
678 + rd->descr = virt_to_phys(&sp->rx_ring[DSC_NEXT(idx)]);
679 + rd->status = DMA_RX_OWN;
680 +
681 + idx = DSC_NEXT(idx);
682 + }
683 +
684 + if (i)
685 + sp->rx_skbprd = idx;
686 +}
687 +
688 +#define AR2313_MAX_PKTS_PER_CALL 64
689 +
690 +static int ar231x_rx_int(struct net_device *dev)
691 +{
692 + struct ar231x_private *sp = netdev_priv(dev);
693 + struct sk_buff *skb, *skb_new;
694 + ar231x_descr_t *rxdesc;
695 + unsigned int status;
696 + u32 idx;
697 + int pkts = 0;
698 + int rval;
699 +
700 + idx = sp->cur_rx;
701 +
702 + /* process at most the entire ring and then wait for another int */
703 + while (1) {
704 + rxdesc = &sp->rx_ring[idx];
705 + status = rxdesc->status;
706 +
707 + if (status & DMA_RX_OWN) {
708 + /* SiByte owns descriptor or descr not yet filled in */
709 + rval = 0;
710 + break;
711 + }
712 +
713 + if (++pkts > AR2313_MAX_PKTS_PER_CALL) {
714 + rval = 1;
715 + break;
716 + }
717 +
718 + if ((status & DMA_RX_ERROR) && !(status & DMA_RX_LONG)) {
719 + dev->stats.rx_errors++;
720 + dev->stats.rx_dropped++;
721 +
722 + /* add statistics counters */
723 + if (status & DMA_RX_ERR_CRC)
724 + dev->stats.rx_crc_errors++;
725 + if (status & DMA_RX_ERR_COL)
726 + dev->stats.rx_over_errors++;
727 + if (status & DMA_RX_ERR_LENGTH)
728 + dev->stats.rx_length_errors++;
729 + if (status & DMA_RX_ERR_RUNT)
730 + dev->stats.rx_over_errors++;
731 + if (status & DMA_RX_ERR_DESC)
732 + dev->stats.rx_over_errors++;
733 +
734 + } else {
735 + /* alloc new buffer. */
736 + skb_new = netdev_alloc_skb_ip_align(dev,
737 + AR2313_BUFSIZE);
738 + if (skb_new != NULL) {
739 + skb = sp->rx_skb[idx];
740 + /* set skb */
741 + skb_put(skb, ((status >> DMA_RX_LEN_SHIFT) &
742 + 0x3fff) - CRC_LEN);
743 +
744 + dev->stats.rx_bytes += skb->len;
745 + skb->protocol = eth_type_trans(skb, dev);
746 + /* pass the packet to upper layers */
747 + netif_rx(skb);
748 +
749 + skb_new->dev = dev;
750 + /* reset descriptor's curr_addr */
751 + rxdesc->addr = virt_to_phys(skb_new->data);
752 +
753 + dev->stats.rx_packets++;
754 + sp->rx_skb[idx] = skb_new;
755 + } else {
756 + dev->stats.rx_dropped++;
757 + }
758 + }
759 +
760 + rxdesc->devcs = ((AR2313_BUFSIZE << DMA_RX1_BSIZE_SHIFT) |
761 + DMA_RX1_CHAINED);
762 + rxdesc->status = DMA_RX_OWN;
763 +
764 + idx = DSC_NEXT(idx);
765 + }
766 +
767 + sp->cur_rx = idx;
768 +
769 + return rval;
770 +}
771 +
772 +static void ar231x_tx_int(struct net_device *dev)
773 +{
774 + struct ar231x_private *sp = netdev_priv(dev);
775 + u32 idx;
776 + struct sk_buff *skb;
777 + ar231x_descr_t *txdesc;
778 + unsigned int status = 0;
779 +
780 + idx = sp->tx_csm;
781 +
782 + while (idx != sp->tx_prd) {
783 + txdesc = &sp->tx_ring[idx];
784 + status = txdesc->status;
785 +
786 + if (status & DMA_TX_OWN) {
787 + /* ar231x dma still owns descr */
788 + break;
789 + }
790 + /* done with this descriptor */
791 + dma_unmap_single(&sp->pdev->dev, txdesc->addr,
792 + txdesc->devcs & DMA_TX1_BSIZE_MASK,
793 + DMA_TO_DEVICE);
794 + txdesc->status = 0;
795 +
796 + if (status & DMA_TX_ERROR) {
797 + dev->stats.tx_errors++;
798 + dev->stats.tx_dropped++;
799 + if (status & DMA_TX_ERR_UNDER)
800 + dev->stats.tx_fifo_errors++;
801 + if (status & DMA_TX_ERR_HB)
802 + dev->stats.tx_heartbeat_errors++;
803 + if (status & (DMA_TX_ERR_LOSS | DMA_TX_ERR_LINK))
804 + dev->stats.tx_carrier_errors++;
805 + if (status & (DMA_TX_ERR_LATE | DMA_TX_ERR_COL |
806 + DMA_TX_ERR_JABBER | DMA_TX_ERR_DEFER))
807 + dev->stats.tx_aborted_errors++;
808 + } else {
809 + /* transmit OK */
810 + dev->stats.tx_packets++;
811 + }
812 +
813 + skb = sp->tx_skb[idx];
814 + sp->tx_skb[idx] = NULL;
815 + idx = DSC_NEXT(idx);
816 + dev->stats.tx_bytes += skb->len;
817 + dev_kfree_skb_irq(skb);
818 + }
819 +
820 + sp->tx_csm = idx;
821 +}
822 +
823 +static void rx_tasklet_func(unsigned long data)
824 +{
825 + struct net_device *dev = (struct net_device *)data;
826 + struct ar231x_private *sp = netdev_priv(dev);
827 +
828 + if (sp->unloading)
829 + return;
830 +
831 + if (ar231x_rx_int(dev)) {
832 + tasklet_hi_schedule(&sp->rx_tasklet);
833 + } else {
834 + unsigned long flags;
835 +
836 + spin_lock_irqsave(&sp->lock, flags);
837 + sp->dma_regs->intr_ena |= DMA_STATUS_RI;
838 + spin_unlock_irqrestore(&sp->lock, flags);
839 + }
840 +}
841 +
842 +static void rx_schedule(struct net_device *dev)
843 +{
844 + struct ar231x_private *sp = netdev_priv(dev);
845 +
846 + sp->dma_regs->intr_ena &= ~DMA_STATUS_RI;
847 +
848 + tasklet_hi_schedule(&sp->rx_tasklet);
849 +}
850 +
851 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id)
852 +{
853 + struct net_device *dev = (struct net_device *)dev_id;
854 + struct ar231x_private *sp = netdev_priv(dev);
855 + unsigned int status, enabled;
856 +
857 + /* clear interrupt */
858 + /* Don't clear RI bit if currently disabled */
859 + status = sp->dma_regs->status;
860 + enabled = sp->dma_regs->intr_ena;
861 + sp->dma_regs->status = status & enabled;
862 +
863 + if (status & DMA_STATUS_NIS) {
864 + /* normal status */
865 + /**
866 + * Don't schedule rx processing if interrupt
867 + * is already disabled.
868 + */
869 + if (status & enabled & DMA_STATUS_RI) {
870 + /* receive interrupt */
871 + rx_schedule(dev);
872 + }
873 + if (status & DMA_STATUS_TI) {
874 + /* transmit interrupt */
875 + ar231x_tx_int(dev);
876 + }
877 + }
878 +
879 + /* abnormal status */
880 + if (status & (DMA_STATUS_FBE | DMA_STATUS_TPS))
881 + ar231x_restart(dev);
882 +
883 + return IRQ_HANDLED;
884 +}
885 +
886 +static int ar231x_open(struct net_device *dev)
887 +{
888 + struct ar231x_private *sp = netdev_priv(dev);
889 + unsigned int ethsal, ethsah;
890 +
891 + /* reset the hardware, in case the MAC address changed */
892 + ethsah = (((u_int) (dev->dev_addr[5]) << 8) & (u_int) 0x0000FF00) |
893 + (((u_int) (dev->dev_addr[4]) << 0) & (u_int) 0x000000FF);
894 +
895 + ethsal = (((u_int) (dev->dev_addr[3]) << 24) & (u_int) 0xFF000000) |
896 + (((u_int) (dev->dev_addr[2]) << 16) & (u_int) 0x00FF0000) |
897 + (((u_int) (dev->dev_addr[1]) << 8) & (u_int) 0x0000FF00) |
898 + (((u_int) (dev->dev_addr[0]) << 0) & (u_int) 0x000000FF);
899 +
900 + sp->eth_regs->mac_addr[0] = ethsah;
901 + sp->eth_regs->mac_addr[1] = ethsal;
902 +
903 + mdelay(10);
904 +
905 + dev->mtu = 1500;
906 + netif_start_queue(dev);
907 +
908 + sp->eth_regs->mac_control |= MAC_CONTROL_RE;
909 +
910 + phy_start(sp->phy_dev);
911 +
912 + return 0;
913 +}
914 +
915 +static void ar231x_tx_timeout(struct net_device *dev)
916 +{
917 + struct ar231x_private *sp = netdev_priv(dev);
918 + unsigned long flags;
919 +
920 + spin_lock_irqsave(&sp->lock, flags);
921 + ar231x_restart(dev);
922 + spin_unlock_irqrestore(&sp->lock, flags);
923 +}
924 +
925 +static void ar231x_halt(struct net_device *dev)
926 +{
927 + struct ar231x_private *sp = netdev_priv(dev);
928 + int j;
929 +
930 + tasklet_disable(&sp->rx_tasklet);
931 +
932 + /* kill the MAC */
933 + sp->eth_regs->mac_control &= ~(MAC_CONTROL_RE | /* disable Receives */
934 + MAC_CONTROL_TE); /* disable Transmits */
935 + /* stop dma */
936 + sp->dma_regs->control = 0;
937 + sp->dma_regs->bus_mode = DMA_BUS_MODE_SWR;
938 +
939 + /* place phy and MAC in reset */
940 + sp->cfg->reset_set(sp->cfg->reset_mac);
941 + sp->cfg->reset_set(sp->cfg->reset_phy);
942 +
943 + /* free buffers on tx ring */
944 + for (j = 0; j < AR2313_DESCR_ENTRIES; j++) {
945 + struct sk_buff *skb;
946 + ar231x_descr_t *txdesc;
947 +
948 + txdesc = &sp->tx_ring[j];
949 + txdesc->descr = 0;
950 +
951 + skb = sp->tx_skb[j];
952 + if (skb) {
953 + dev_kfree_skb(skb);
954 + sp->tx_skb[j] = NULL;
955 + }
956 + }
957 +}
958 +
959 +/**
960 + * close should do nothing. Here's why. It's called when
961 + * 'ifconfig bond0 down' is run. If it calls free_irq then
962 + * the irq is gone forever ! When bond0 is made 'up' again,
963 + * the ar231x_open () does not call request_irq (). Worse,
964 + * the call to ar231x_halt() generates a WDOG reset due to
965 + * the write to reset register and the box reboots.
966 + * Commenting this out is good since it allows the
967 + * system to resume when bond0 is made up again.
968 + */
969 +static int ar231x_close(struct net_device *dev)
970 +{
971 + struct ar231x_private *sp = netdev_priv(dev);
972 +#if 0
973 + /* Disable interrupts */
974 + disable_irq(dev->irq);
975 +
976 + /**
977 + * Without (or before) releasing irq and stopping hardware, this
978 + * is an absolute non-sense, by the way. It will be reset instantly
979 + * by the first irq.
980 + */
981 + netif_stop_queue(dev);
982 +
983 + /* stop the MAC and DMA engines */
984 + ar231x_halt(dev);
985 +
986 + /* release the interrupt */
987 + free_irq(dev->irq, dev);
988 +
989 +#endif
990 +
991 + phy_stop(sp->phy_dev);
992 +
993 + return 0;
994 +}
995 +
996 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev)
997 +{
998 + struct ar231x_private *sp = netdev_priv(dev);
999 + ar231x_descr_t *td;
1000 + u32 idx;
1001 +
1002 + idx = sp->tx_prd;
1003 + td = &sp->tx_ring[idx];
1004 +
1005 + if (td->status & DMA_TX_OWN) {
1006 + /* free skbuf and lie to the caller that we sent it out */
1007 + dev->stats.tx_dropped++;
1008 + dev_kfree_skb(skb);
1009 +
1010 + /* restart transmitter in case locked */
1011 + sp->dma_regs->xmt_poll = 0;
1012 + return 0;
1013 + }
1014 +
1015 + /* Setup the transmit descriptor. */
1016 + td->devcs = ((skb->len << DMA_TX1_BSIZE_SHIFT) |
1017 + (DMA_TX1_LS | DMA_TX1_IC | DMA_TX1_CHAINED));
1018 + td->addr = dma_map_single(&sp->pdev->dev, skb->data, skb->len, DMA_TO_DEVICE);
1019 + td->status = DMA_TX_OWN;
1020 +
1021 + /* kick transmitter last */
1022 + sp->dma_regs->xmt_poll = 0;
1023 +
1024 + sp->tx_skb[idx] = skb;
1025 + idx = DSC_NEXT(idx);
1026 + sp->tx_prd = idx;
1027 +
1028 + return 0;
1029 +}
1030 +
1031 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1032 +{
1033 + struct ar231x_private *sp = netdev_priv(dev);
1034 +
1035 + switch (cmd) {
1036 + case SIOCGMIIPHY:
1037 + case SIOCGMIIREG:
1038 + case SIOCSMIIREG:
1039 + return phy_mii_ioctl(sp->phy_dev, ifr, cmd);
1040 +
1041 + default:
1042 + break;
1043 + }
1044 +
1045 + return -EOPNOTSUPP;
1046 +}
1047 +
1048 +static void ar231x_adjust_link(struct net_device *dev)
1049 +{
1050 + struct ar231x_private *sp = netdev_priv(dev);
1051 + struct phy_device *phydev = sp->phy_dev;
1052 + u32 mc;
1053 +
1054 + if (!phydev->link) {
1055 + if (sp->link) {
1056 + pr_info("%s: link down\n", dev->name);
1057 + sp->link = 0;
1058 + }
1059 + return;
1060 + }
1061 + sp->link = 1;
1062 +
1063 + pr_info("%s: link up (%uMbps/%s duplex)\n", dev->name,
1064 + phydev->speed, phydev->duplex ? "full" : "half");
1065 +
1066 + mc = sp->eth_regs->mac_control;
1067 + if (phydev->duplex)
1068 + mc = (mc | MAC_CONTROL_F) & ~MAC_CONTROL_DRO;
1069 + else
1070 + mc = (mc | MAC_CONTROL_DRO) & ~MAC_CONTROL_F;
1071 + sp->eth_regs->mac_control = mc;
1072 + sp->duplex = phydev->duplex;
1073 +}
1074 +
1075 +#define MII_ADDR(phy, reg) \
1076 + ((reg << MII_ADDR_REG_SHIFT) | (phy << MII_ADDR_PHY_SHIFT))
1077 +
1078 +static int
1079 +ar231x_mdiobus_read(struct mii_bus *bus, int phy_addr, int regnum)
1080 +{
1081 + struct net_device *const dev = bus->priv;
1082 + struct ar231x_private *sp = netdev_priv(dev);
1083 + volatile MII *ethernet = sp->phy_regs;
1084 +
1085 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum);
1086 + while (ethernet->mii_addr & MII_ADDR_BUSY)
1087 + ;
1088 + return ethernet->mii_data >> MII_DATA_SHIFT;
1089 +}
1090 +
1091 +static int
1092 +ar231x_mdiobus_write(struct mii_bus *bus, int phy_addr, int regnum, u16 value)
1093 +{
1094 + struct net_device *const dev = bus->priv;
1095 + struct ar231x_private *sp = netdev_priv(dev);
1096 + volatile MII *ethernet = sp->phy_regs;
1097 +
1098 + while (ethernet->mii_addr & MII_ADDR_BUSY)
1099 + ;
1100 + ethernet->mii_data = value << MII_DATA_SHIFT;
1101 + ethernet->mii_addr = MII_ADDR(phy_addr, regnum) | MII_ADDR_WRITE;
1102 +
1103 + return 0;
1104 +}
1105 +
1106 +static int ar231x_mdiobus_reset(struct mii_bus *bus)
1107 +{
1108 + struct net_device *const dev = bus->priv;
1109 +
1110 + ar231x_reset_reg(dev);
1111 +
1112 + return 0;
1113 +}
1114 +
1115 +static int ar231x_mdiobus_probe(struct net_device *dev)
1116 +{
1117 + __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
1118 + struct ar231x_private *const sp = netdev_priv(dev);
1119 + struct phy_device *phydev = NULL;
1120 +
1121 + /* find the first (lowest address) PHY on the current MAC's MII bus */
1122 + phydev = phy_find_first(sp->mii_bus);
1123 + if (!phydev) {
1124 + printk(KERN_ERR "ar231x: %s: no PHY found\n", dev->name);
1125 + return -1;
1126 + }
1127 +
1128 + /* now we are supposed to have a proper phydev, to attach to... */
1129 + BUG_ON(phydev->attached_dev);
1130 +
1131 + phydev = phy_connect(dev, phydev_name(phydev), &ar231x_adjust_link,
1132 + PHY_INTERFACE_MODE_MII);
1133 + if (IS_ERR(phydev)) {
1134 + printk(KERN_ERR "%s: Could not attach to PHY\n", dev->name);
1135 + return PTR_ERR(phydev);
1136 + }
1137 +
1138 + /* mask with MAC supported features */
1139 + linkmode_set_bit_array(phy_10_100_features_array,
1140 + ARRAY_SIZE(phy_10_100_features_array),
1141 + mask);
1142 + linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, mask);
1143 + linkmode_set_bit(ETHTOOL_LINK_MODE_MII_BIT, mask);
1144 + linkmode_set_bit(ETHTOOL_LINK_MODE_TP_BIT, mask);
1145 +
1146 + linkmode_and(phydev->supported, phydev->supported, mask);
1147 + linkmode_copy(phydev->advertising, phydev->supported);
1148 +
1149 + sp->phy_dev = phydev;
1150 +
1151 + printk(KERN_INFO "%s: attached PHY driver [%s] (mii_bus:phy_addr=%s)\n",
1152 + dev->name, phydev->drv->name, phydev_name(phydev));
1153 +
1154 + return 0;
1155 +}
1156 +
1157 --- /dev/null
1158 +++ b/drivers/net/ethernet/atheros/ar231x/ar231x.h
1159 @@ -0,0 +1,282 @@
1160 +/*
1161 + * ar231x.h: Linux driver for the Atheros AR231x Ethernet device.
1162 + *
1163 + * Copyright (C) 2004 by Sameer Dekate <sdekate@arubanetworks.com>
1164 + * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
1165 + * Copyright (C) 2006-2009 Felix Fietkau <nbd@nbd.name>
1166 + *
1167 + * Thanks to Atheros for providing hardware and documentation
1168 + * enabling me to write this driver.
1169 + *
1170 + * This program is free software; you can redistribute it and/or modify
1171 + * it under the terms of the GNU General Public License as published by
1172 + * the Free Software Foundation; either version 2 of the License, or
1173 + * (at your option) any later version.
1174 + */
1175 +
1176 +#ifndef _AR2313_H_
1177 +#define _AR2313_H_
1178 +
1179 +#include <linux/interrupt.h>
1180 +#include <generated/autoconf.h>
1181 +#include <linux/bitops.h>
1182 +#include <ath25_platform.h>
1183 +
1184 +/* probe link timer - 5 secs */
1185 +#define LINK_TIMER (5*HZ)
1186 +
1187 +#define IS_DMA_TX_INT(X) (((X) & (DMA_STATUS_TI)) != 0)
1188 +#define IS_DMA_RX_INT(X) (((X) & (DMA_STATUS_RI)) != 0)
1189 +#define IS_DRIVER_OWNED(X) (((X) & (DMA_TX_OWN)) == 0)
1190 +
1191 +#define AR2313_TX_TIMEOUT (HZ/4)
1192 +
1193 +/* Rings */
1194 +#define DSC_RING_ENTRIES_SIZE (AR2313_DESCR_ENTRIES * sizeof(struct desc))
1195 +#define DSC_NEXT(idx) ((idx + 1) & (AR2313_DESCR_ENTRIES - 1))
1196 +
1197 +#define AR2313_MBGET 2
1198 +#define AR2313_MBSET 3
1199 +#define AR2313_PCI_RECONFIG 4
1200 +#define AR2313_PCI_DUMP 5
1201 +#define AR2313_TEST_PANIC 6
1202 +#define AR2313_TEST_NULLPTR 7
1203 +#define AR2313_READ_DATA 8
1204 +#define AR2313_WRITE_DATA 9
1205 +#define AR2313_GET_VERSION 10
1206 +#define AR2313_TEST_HANG 11
1207 +#define AR2313_SYNC 12
1208 +
1209 +#define DMA_RX_ERR_CRC BIT(1)
1210 +#define DMA_RX_ERR_DRIB BIT(2)
1211 +#define DMA_RX_ERR_MII BIT(3)
1212 +#define DMA_RX_EV2 BIT(5)
1213 +#define DMA_RX_ERR_COL BIT(6)
1214 +#define DMA_RX_LONG BIT(7)
1215 +#define DMA_RX_LS BIT(8) /* last descriptor */
1216 +#define DMA_RX_FS BIT(9) /* first descriptor */
1217 +#define DMA_RX_MF BIT(10) /* multicast frame */
1218 +#define DMA_RX_ERR_RUNT BIT(11) /* runt frame */
1219 +#define DMA_RX_ERR_LENGTH BIT(12) /* length error */
1220 +#define DMA_RX_ERR_DESC BIT(14) /* descriptor error */
1221 +#define DMA_RX_ERROR BIT(15) /* error summary */
1222 +#define DMA_RX_LEN_MASK 0x3fff0000
1223 +#define DMA_RX_LEN_SHIFT 16
1224 +#define DMA_RX_FILT BIT(30)
1225 +#define DMA_RX_OWN BIT(31) /* desc owned by DMA controller */
1226 +
1227 +#define DMA_RX1_BSIZE_MASK 0x000007ff
1228 +#define DMA_RX1_BSIZE_SHIFT 0
1229 +#define DMA_RX1_CHAINED BIT(24)
1230 +#define DMA_RX1_RER BIT(25)
1231 +
1232 +#define DMA_TX_ERR_UNDER BIT(1) /* underflow error */
1233 +#define DMA_TX_ERR_DEFER BIT(2) /* excessive deferral */
1234 +#define DMA_TX_COL_MASK 0x78
1235 +#define DMA_TX_COL_SHIFT 3
1236 +#define DMA_TX_ERR_HB BIT(7) /* hearbeat failure */
1237 +#define DMA_TX_ERR_COL BIT(8) /* excessive collisions */
1238 +#define DMA_TX_ERR_LATE BIT(9) /* late collision */
1239 +#define DMA_TX_ERR_LINK BIT(10) /* no carrier */
1240 +#define DMA_TX_ERR_LOSS BIT(11) /* loss of carrier */
1241 +#define DMA_TX_ERR_JABBER BIT(14) /* transmit jabber timeout */
1242 +#define DMA_TX_ERROR BIT(15) /* frame aborted */
1243 +#define DMA_TX_OWN BIT(31) /* descr owned by DMA controller */
1244 +
1245 +#define DMA_TX1_BSIZE_MASK 0x000007ff
1246 +#define DMA_TX1_BSIZE_SHIFT 0
1247 +#define DMA_TX1_CHAINED BIT(24) /* chained descriptors */
1248 +#define DMA_TX1_TER BIT(25) /* transmit end of ring */
1249 +#define DMA_TX1_FS BIT(29) /* first segment */
1250 +#define DMA_TX1_LS BIT(30) /* last segment */
1251 +#define DMA_TX1_IC BIT(31) /* interrupt on completion */
1252 +
1253 +#define RCVPKT_LENGTH(X) (X >> 16) /* Received pkt Length */
1254 +
1255 +#define MAC_CONTROL_RE BIT(2) /* receive enable */
1256 +#define MAC_CONTROL_TE BIT(3) /* transmit enable */
1257 +#define MAC_CONTROL_DC BIT(5) /* Deferral check */
1258 +#define MAC_CONTROL_ASTP BIT(8) /* Auto pad strip */
1259 +#define MAC_CONTROL_DRTY BIT(10) /* Disable retry */
1260 +#define MAC_CONTROL_DBF BIT(11) /* Disable bcast frames */
1261 +#define MAC_CONTROL_LCC BIT(12) /* late collision ctrl */
1262 +#define MAC_CONTROL_HP BIT(13) /* Hash Perfect filtering */
1263 +#define MAC_CONTROL_HASH BIT(14) /* Unicast hash filtering */
1264 +#define MAC_CONTROL_HO BIT(15) /* Hash only filtering */
1265 +#define MAC_CONTROL_PB BIT(16) /* Pass Bad frames */
1266 +#define MAC_CONTROL_IF BIT(17) /* Inverse filtering */
1267 +#define MAC_CONTROL_PR BIT(18) /* promis mode (valid frames only) */
1268 +#define MAC_CONTROL_PM BIT(19) /* pass multicast */
1269 +#define MAC_CONTROL_F BIT(20) /* full-duplex */
1270 +#define MAC_CONTROL_DRO BIT(23) /* Disable Receive Own */
1271 +#define MAC_CONTROL_HBD BIT(28) /* heart-beat disabled (MUST BE SET) */
1272 +#define MAC_CONTROL_BLE BIT(30) /* big endian mode */
1273 +#define MAC_CONTROL_RA BIT(31) /* rcv all (valid and invalid frames) */
1274 +
1275 +#define MII_ADDR_BUSY BIT(0)
1276 +#define MII_ADDR_WRITE BIT(1)
1277 +#define MII_ADDR_REG_SHIFT 6
1278 +#define MII_ADDR_PHY_SHIFT 11
1279 +#define MII_DATA_SHIFT 0
1280 +
1281 +#define FLOW_CONTROL_FCE BIT(1)
1282 +
1283 +#define DMA_BUS_MODE_SWR BIT(0) /* software reset */
1284 +#define DMA_BUS_MODE_BLE BIT(7) /* big endian mode */
1285 +#define DMA_BUS_MODE_PBL_SHIFT 8 /* programmable burst length 32 */
1286 +#define DMA_BUS_MODE_DBO BIT(20) /* big-endian descriptors */
1287 +
1288 +#define DMA_STATUS_TI BIT(0) /* transmit interrupt */
1289 +#define DMA_STATUS_TPS BIT(1) /* transmit process stopped */
1290 +#define DMA_STATUS_TU BIT(2) /* transmit buffer unavailable */
1291 +#define DMA_STATUS_TJT BIT(3) /* transmit buffer timeout */
1292 +#define DMA_STATUS_UNF BIT(5) /* transmit underflow */
1293 +#define DMA_STATUS_RI BIT(6) /* receive interrupt */
1294 +#define DMA_STATUS_RU BIT(7) /* receive buffer unavailable */
1295 +#define DMA_STATUS_RPS BIT(8) /* receive process stopped */
1296 +#define DMA_STATUS_ETI BIT(10) /* early transmit interrupt */
1297 +#define DMA_STATUS_FBE BIT(13) /* fatal bus interrupt */
1298 +#define DMA_STATUS_ERI BIT(14) /* early receive interrupt */
1299 +#define DMA_STATUS_AIS BIT(15) /* abnormal interrupt summary */
1300 +#define DMA_STATUS_NIS BIT(16) /* normal interrupt summary */
1301 +#define DMA_STATUS_RS_SHIFT 17 /* receive process state */
1302 +#define DMA_STATUS_TS_SHIFT 20 /* transmit process state */
1303 +#define DMA_STATUS_EB_SHIFT 23 /* error bits */
1304 +
1305 +#define DMA_CONTROL_SR BIT(1) /* start receive */
1306 +#define DMA_CONTROL_ST BIT(13) /* start transmit */
1307 +#define DMA_CONTROL_SF BIT(21) /* store and forward */
1308 +
1309 +typedef struct {
1310 + volatile unsigned int status; /* OWN, Device control and status. */
1311 + volatile unsigned int devcs; /* pkt Control bits + Length */
1312 + volatile unsigned int addr; /* Current Address. */
1313 + volatile unsigned int descr; /* Next descriptor in chain. */
1314 +} ar231x_descr_t;
1315 +
1316 +/**
1317 + * New Combo structure for Both Eth0 AND eth1
1318 + *
1319 + * Don't directly access MII related regs since phy chip could be actually
1320 + * connected to another ethernet block.
1321 + */
1322 +typedef struct {
1323 + volatile unsigned int mac_control; /* 0x00 */
1324 + volatile unsigned int mac_addr[2]; /* 0x04 - 0x08 */
1325 + volatile unsigned int mcast_table[2]; /* 0x0c - 0x10 */
1326 + volatile unsigned int __mii_addr; /* 0x14 */
1327 + volatile unsigned int __mii_data; /* 0x18 */
1328 + volatile unsigned int flow_control; /* 0x1c */
1329 + volatile unsigned int vlan_tag; /* 0x20 */
1330 + volatile unsigned int pad[7]; /* 0x24 - 0x3c */
1331 + volatile unsigned int ucast_table[8]; /* 0x40-0x5c */
1332 +} ETHERNET_STRUCT;
1333 +
1334 +typedef struct {
1335 + volatile unsigned int mii_addr;
1336 + volatile unsigned int mii_data;
1337 +} MII;
1338 +
1339 +/********************************************************************
1340 + * Interrupt controller
1341 + ********************************************************************/
1342 +
1343 +typedef struct {
1344 + volatile unsigned int wdog_control; /* 0x08 */
1345 + volatile unsigned int wdog_timer; /* 0x0c */
1346 + volatile unsigned int misc_status; /* 0x10 */
1347 + volatile unsigned int misc_mask; /* 0x14 */
1348 + volatile unsigned int global_status; /* 0x18 */
1349 + volatile unsigned int reserved; /* 0x1c */
1350 + volatile unsigned int reset_control; /* 0x20 */
1351 +} INTERRUPT;
1352 +
1353 +/********************************************************************
1354 + * DMA controller
1355 + ********************************************************************/
1356 +typedef struct {
1357 + volatile unsigned int bus_mode; /* 0x00 (CSR0) */
1358 + volatile unsigned int xmt_poll; /* 0x04 (CSR1) */
1359 + volatile unsigned int rcv_poll; /* 0x08 (CSR2) */
1360 + volatile unsigned int rcv_base; /* 0x0c (CSR3) */
1361 + volatile unsigned int xmt_base; /* 0x10 (CSR4) */
1362 + volatile unsigned int status; /* 0x14 (CSR5) */
1363 + volatile unsigned int control; /* 0x18 (CSR6) */
1364 + volatile unsigned int intr_ena; /* 0x1c (CSR7) */
1365 + volatile unsigned int rcv_missed; /* 0x20 (CSR8) */
1366 + volatile unsigned int reserved[11]; /* 0x24-0x4c (CSR9-19) */
1367 + volatile unsigned int cur_tx_buf_addr; /* 0x50 (CSR20) */
1368 + volatile unsigned int cur_rx_buf_addr; /* 0x50 (CSR21) */
1369 +} DMA;
1370 +
1371 +/**
1372 + * Struct private for the Sibyte.
1373 + *
1374 + * Elements are grouped so variables used by the tx handling goes
1375 + * together, and will go into the same cache lines etc. in order to
1376 + * avoid cache line contention between the rx and tx handling on SMP.
1377 + *
1378 + * Frequently accessed variables are put at the beginning of the
1379 + * struct to help the compiler generate better/shorter code.
1380 + */
1381 +struct ar231x_private {
1382 + struct net_device *dev;
1383 + struct platform_device *pdev;
1384 + int version;
1385 + u32 mb[2];
1386 +
1387 + volatile MII *phy_regs;
1388 + volatile ETHERNET_STRUCT *eth_regs;
1389 + volatile DMA *dma_regs;
1390 + struct ar231x_eth *cfg;
1391 +
1392 + spinlock_t lock; /* Serialise access to device */
1393 +
1394 + /* RX and TX descriptors, must be adjacent */
1395 + ar231x_descr_t *rx_ring;
1396 + ar231x_descr_t *tx_ring;
1397 +
1398 + struct sk_buff **rx_skb;
1399 + struct sk_buff **tx_skb;
1400 +
1401 + /* RX elements */
1402 + u32 rx_skbprd;
1403 + u32 cur_rx;
1404 +
1405 + /* TX elements */
1406 + u32 tx_prd;
1407 + u32 tx_csm;
1408 +
1409 + /* Misc elements */
1410 + char name[48];
1411 + struct {
1412 + u32 address;
1413 + u32 length;
1414 + char *mapping;
1415 + } desc;
1416 +
1417 + unsigned short link; /* 0 - link down, 1 - link up */
1418 + unsigned short duplex; /* 0 - half, 1 - full */
1419 +
1420 + struct tasklet_struct rx_tasklet;
1421 + int unloading;
1422 +
1423 + struct phy_device *phy_dev;
1424 + struct mii_bus *mii_bus;
1425 +};
1426 +
1427 +/* Prototypes */
1428 +static int ar231x_init(struct net_device *dev);
1429 +#ifdef TX_TIMEOUT
1430 +static void ar231x_tx_timeout(struct net_device *dev);
1431 +#endif
1432 +static int ar231x_restart(struct net_device *dev);
1433 +static void ar231x_load_rx_ring(struct net_device *dev, int bufs);
1434 +static irqreturn_t ar231x_interrupt(int irq, void *dev_id);
1435 +static int ar231x_open(struct net_device *dev);
1436 +static int ar231x_start_xmit(struct sk_buff *skb, struct net_device *dev);
1437 +static int ar231x_close(struct net_device *dev);
1438 +static int ar231x_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd);
1439 +static void ar231x_init_cleanup(struct net_device *dev);
1440 +
1441 +#endif /* _AR2313_H_ */
1442 --- a/arch/mips/ath25/ar2315_regs.h
1443 +++ b/arch/mips/ath25/ar2315_regs.h
1444 @@ -57,6 +57,9 @@
1445 #define AR2315_PCI_EXT_BASE 0x80000000 /* PCI external */
1446 #define AR2315_PCI_EXT_SIZE 0x40000000
1447
1448 +/* MII registers offset inside Ethernet MMR region */
1449 +#define AR2315_ENET0_MII_BASE (AR2315_ENET0_BASE + 0x14)
1450 +
1451 /*
1452 * Configuration registers
1453 */
1454 --- a/arch/mips/ath25/ar5312_regs.h
1455 +++ b/arch/mips/ath25/ar5312_regs.h
1456 @@ -64,6 +64,10 @@
1457 #define AR5312_AR5312_REV7 0x0057 /* AR5312 WMAC (AP30-040) */
1458 #define AR5312_AR2313_REV8 0x0058 /* AR2313 WMAC (AP43-030) */
1459
1460 +/* MII registers offset inside Ethernet MMR region */
1461 +#define AR5312_ENET0_MII_BASE (AR5312_ENET0_BASE + 0x14)
1462 +#define AR5312_ENET1_MII_BASE (AR5312_ENET1_BASE + 0x14)
1463 +
1464 /* Reset/Timer Block Address Map */
1465 #define AR5312_TIMER 0x0000 /* countdown timer */
1466 #define AR5312_RELOAD 0x0004 /* timer reload value */
1467 --- a/arch/mips/ath25/ar2315.c
1468 +++ b/arch/mips/ath25/ar2315.c
1469 @@ -136,6 +136,8 @@ static void ar2315_irq_dispatch(void)
1470
1471 if (pending & CAUSEF_IP3)
1472 do_IRQ(AR2315_IRQ_WLAN0);
1473 + else if (pending & CAUSEF_IP4)
1474 + do_IRQ(AR2315_IRQ_ENET0);
1475 #ifdef CONFIG_PCI_AR2315
1476 else if (pending & CAUSEF_IP5)
1477 do_IRQ(AR2315_IRQ_LCBUS_PCI);
1478 @@ -169,6 +171,29 @@ void __init ar2315_arch_init_irq(void)
1479 ar2315_misc_irq_domain = domain;
1480 }
1481
1482 +static void ar2315_device_reset_set(u32 mask)
1483 +{
1484 + u32 val;
1485 +
1486 + val = ar2315_rst_reg_read(AR2315_RESET);
1487 + ar2315_rst_reg_write(AR2315_RESET, val | mask);
1488 +}
1489 +
1490 +static void ar2315_device_reset_clear(u32 mask)
1491 +{
1492 + u32 val;
1493 +
1494 + val = ar2315_rst_reg_read(AR2315_RESET);
1495 + ar2315_rst_reg_write(AR2315_RESET, val & ~mask);
1496 +}
1497 +
1498 +static struct ar231x_eth ar2315_eth_data = {
1499 + .reset_set = ar2315_device_reset_set,
1500 + .reset_clear = ar2315_device_reset_clear,
1501 + .reset_mac = AR2315_RESET_ENET0,
1502 + .reset_phy = AR2315_RESET_EPHY0,
1503 +};
1504 +
1505 static struct resource ar2315_gpio_res[] = {
1506 {
1507 .name = "ar2315-gpio",
1508 @@ -205,6 +230,11 @@ void __init ar2315_init_devices(void)
1509 ar2315_gpio_res[1].end = ar2315_gpio_res[1].start;
1510 platform_device_register(&ar2315_gpio);
1511
1512 + ar2315_eth_data.macaddr = ath25_board.config->enet0_mac;
1513 + ath25_add_ethernet(0, AR2315_ENET0_BASE, "eth0_mii",
1514 + AR2315_ENET0_MII_BASE, AR2315_IRQ_ENET0,
1515 + &ar2315_eth_data);
1516 +
1517 ath25_add_wmac(0, AR2315_WLAN0_BASE, AR2315_IRQ_WLAN0);
1518 }
1519
1520 --- a/arch/mips/ath25/ar5312.c
1521 +++ b/arch/mips/ath25/ar5312.c
1522 @@ -132,6 +132,10 @@ static void ar5312_irq_dispatch(void)
1523
1524 if (pending & CAUSEF_IP2)
1525 do_IRQ(AR5312_IRQ_WLAN0);
1526 + else if (pending & CAUSEF_IP3)
1527 + do_IRQ(AR5312_IRQ_ENET0);
1528 + else if (pending & CAUSEF_IP4)
1529 + do_IRQ(AR5312_IRQ_ENET1);
1530 else if (pending & CAUSEF_IP5)
1531 do_IRQ(AR5312_IRQ_WLAN1);
1532 else if (pending & CAUSEF_IP6)
1533 @@ -163,6 +167,36 @@ void __init ar5312_arch_init_irq(void)
1534 ar5312_misc_irq_domain = domain;
1535 }
1536
1537 +static void ar5312_device_reset_set(u32 mask)
1538 +{
1539 + u32 val;
1540 +
1541 + val = ar5312_rst_reg_read(AR5312_RESET);
1542 + ar5312_rst_reg_write(AR5312_RESET, val | mask);
1543 +}
1544 +
1545 +static void ar5312_device_reset_clear(u32 mask)
1546 +{
1547 + u32 val;
1548 +
1549 + val = ar5312_rst_reg_read(AR5312_RESET);
1550 + ar5312_rst_reg_write(AR5312_RESET, val & ~mask);
1551 +}
1552 +
1553 +static struct ar231x_eth ar5312_eth0_data = {
1554 + .reset_set = ar5312_device_reset_set,
1555 + .reset_clear = ar5312_device_reset_clear,
1556 + .reset_mac = AR5312_RESET_ENET0,
1557 + .reset_phy = AR5312_RESET_EPHY0,
1558 +};
1559 +
1560 +static struct ar231x_eth ar5312_eth1_data = {
1561 + .reset_set = ar5312_device_reset_set,
1562 + .reset_clear = ar5312_device_reset_clear,
1563 + .reset_mac = AR5312_RESET_ENET1,
1564 + .reset_phy = AR5312_RESET_EPHY1,
1565 +};
1566 +
1567 static struct physmap_flash_data ar5312_flash_data = {
1568 .width = 2,
1569 };
1570 @@ -243,6 +277,7 @@ static void __init ar5312_flash_init(voi
1571 void __init ar5312_init_devices(void)
1572 {
1573 struct ath25_boarddata *config;
1574 + u8 *c;
1575
1576 ar5312_flash_init();
1577
1578 @@ -266,8 +301,30 @@ void __init ar5312_init_devices(void)
1579
1580 platform_device_register(&ar5312_gpio);
1581
1582 + /* Fix up MAC addresses if necessary */
1583 + if (is_broadcast_ether_addr(config->enet0_mac))
1584 + ether_addr_copy(config->enet0_mac, config->enet1_mac);
1585 +
1586 + /* If ENET0 and ENET1 have the same mac address,
1587 + * increment the one from ENET1 */
1588 + if (ether_addr_equal(config->enet0_mac, config->enet1_mac)) {
1589 + c = config->enet1_mac + 5;
1590 + while ((c >= config->enet1_mac) && !(++(*c)))
1591 + c--;
1592 + }
1593 +
1594 switch (ath25_soc) {
1595 case ATH25_SOC_AR5312:
1596 + ar5312_eth0_data.macaddr = config->enet0_mac;
1597 + ath25_add_ethernet(0, AR5312_ENET0_BASE, "eth0_mii",
1598 + AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET0,
1599 + &ar5312_eth0_data);
1600 +
1601 + ar5312_eth1_data.macaddr = config->enet1_mac;
1602 + ath25_add_ethernet(1, AR5312_ENET1_BASE, "eth1_mii",
1603 + AR5312_ENET1_MII_BASE, AR5312_IRQ_ENET1,
1604 + &ar5312_eth1_data);
1605 +
1606 if (!ath25_board.radio)
1607 return;
1608
1609 @@ -276,8 +333,18 @@ void __init ar5312_init_devices(void)
1610
1611 ath25_add_wmac(0, AR5312_WLAN0_BASE, AR5312_IRQ_WLAN0);
1612 break;
1613 + /*
1614 + * AR2312/3 ethernet uses the PHY of ENET0, but the MAC
1615 + * of ENET1. Atheros calls it 'twisted' for a reason :)
1616 + */
1617 case ATH25_SOC_AR2312:
1618 case ATH25_SOC_AR2313:
1619 + ar5312_eth1_data.reset_phy = ar5312_eth0_data.reset_phy;
1620 + ar5312_eth1_data.macaddr = config->enet0_mac;
1621 + ath25_add_ethernet(1, AR5312_ENET1_BASE, "eth0_mii",
1622 + AR5312_ENET0_MII_BASE, AR5312_IRQ_ENET1,
1623 + &ar5312_eth1_data);
1624 +
1625 if (!ath25_board.radio)
1626 return;
1627 break;
1628 --- a/arch/mips/ath25/devices.h
1629 +++ b/arch/mips/ath25/devices.h
1630 @@ -33,6 +33,8 @@ extern struct ar231x_board_config ath25_
1631 extern void (*ath25_irq_dispatch)(void);
1632
1633 int ath25_find_config(phys_addr_t offset, unsigned long size);
1634 +int ath25_add_ethernet(int nr, u32 base, const char *mii_name, u32 mii_base,
1635 + int irq, void *pdata);
1636 void ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk);
1637 int ath25_add_wmac(int nr, u32 base, int irq);
1638
1639 --- a/arch/mips/ath25/devices.c
1640 +++ b/arch/mips/ath25/devices.c
1641 @@ -13,6 +13,51 @@
1642 struct ar231x_board_config ath25_board;
1643 enum ath25_soc_type ath25_soc = ATH25_SOC_UNKNOWN;
1644
1645 +static struct resource ath25_eth0_res[] = {
1646 + {
1647 + .name = "eth0_membase",
1648 + .flags = IORESOURCE_MEM,
1649 + },
1650 + {
1651 + .name = "eth0_mii",
1652 + .flags = IORESOURCE_MEM,
1653 + },
1654 + {
1655 + .name = "eth0_irq",
1656 + .flags = IORESOURCE_IRQ,
1657 + }
1658 +};
1659 +
1660 +static struct resource ath25_eth1_res[] = {
1661 + {
1662 + .name = "eth1_membase",
1663 + .flags = IORESOURCE_MEM,
1664 + },
1665 + {
1666 + .name = "eth1_mii",
1667 + .flags = IORESOURCE_MEM,
1668 + },
1669 + {
1670 + .name = "eth1_irq",
1671 + .flags = IORESOURCE_IRQ,
1672 + }
1673 +};
1674 +
1675 +static struct platform_device ath25_eth[] = {
1676 + {
1677 + .id = 0,
1678 + .name = "ar231x-eth",
1679 + .resource = ath25_eth0_res,
1680 + .num_resources = ARRAY_SIZE(ath25_eth0_res)
1681 + },
1682 + {
1683 + .id = 1,
1684 + .name = "ar231x-eth",
1685 + .resource = ath25_eth1_res,
1686 + .num_resources = ARRAY_SIZE(ath25_eth1_res)
1687 + }
1688 +};
1689 +
1690 static struct resource ath25_wmac0_res[] = {
1691 {
1692 .name = "wmac0_membase",
1693 @@ -71,6 +116,25 @@ const char *get_system_type(void)
1694 return soc_type_strings[ath25_soc];
1695 }
1696
1697 +int __init ath25_add_ethernet(int nr, u32 base, const char *mii_name,
1698 + u32 mii_base, int irq, void *pdata)
1699 +{
1700 + struct resource *res;
1701 +
1702 + ath25_eth[nr].dev.platform_data = pdata;
1703 + res = &ath25_eth[nr].resource[0];
1704 + res->start = base;
1705 + res->end = base + 0x2000 - 1;
1706 + res++;
1707 + res->name = mii_name;
1708 + res->start = mii_base;
1709 + res->end = mii_base + 8 - 1;
1710 + res++;
1711 + res->start = irq;
1712 + res->end = irq;
1713 + return platform_device_register(&ath25_eth[nr]);
1714 +}
1715 +
1716 void __init ath25_serial_setup(u32 mapbase, int irq, unsigned int uartclk)
1717 {
1718 #ifdef CONFIG_SERIAL_8250_CONSOLE
1719 --- a/arch/mips/include/asm/mach-ath25/ath25_platform.h
1720 +++ b/arch/mips/include/asm/mach-ath25/ath25_platform.h
1721 @@ -71,4 +71,15 @@ struct ar231x_board_config {
1722 const char *radio;
1723 };
1724
1725 +/*
1726 + * Platform device information for the Ethernet MAC
1727 + */
1728 +struct ar231x_eth {
1729 + void (*reset_set)(u32);
1730 + void (*reset_clear)(u32);
1731 + u32 reset_mac;
1732 + u32 reset_phy;
1733 + char *macaddr;
1734 +};
1735 +
1736 #endif /* __ASM_MACH_ATH25_PLATFORM_H */
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