target/linux/lantiq/files-5.4/arch/mips/boot/dts/lantiq/vr9_tplink_vr200.dtsi

   1 #include "vr9.dtsi"
   2
   3 #include <dt-bindings/input/input.h>
   4 #include <dt-bindings/mips/lantiq_rcu_gphy.h>
   5
   6 / {
   7         memory@0 {
   8                 device_type = "memory";
   9                 reg = <0x0 0x7f00000>;
  10         };
  11
  12         usb_vbus: regulator-usb-vbus {
  13                 compatible = "regulator-fixed";
  14
  15                 regulator-name = "USB_VBUS";
  16
  17                 regulator-min-microvolt = <5000000>;
  18                 regulator-max-microvolt = <5000000>;
  19
  20                 gpio = <&gpio 33 GPIO_ACTIVE_HIGH>;
  21                 enable-active-high;
  22         };
  23 };
  24
  25 &eth0 {
  26         pinctrl-0 = <&mdio_pins>, <&gphy0_led1_pins>, <&gphy1_led1_pins>;
  27         pinctrl-names = "default";
  28
  29         lan: interface@0 {
  30                 compatible = "lantiq,xrx200-pdi";
  31                 #address-cells = <1>;
  32                 #size-cells = <0>;
  33                 reg = <0>;
  34                 mtd-mac-address = <&romfile 0xf100>;
  35                 lantiq,switch;
  36
  37                 ethernet@0 {
  38                         compatible = "lantiq,xrx200-pdi-port";
  39                         reg = <0>;
  40                         phy-mode = "rgmii";
  41                         phy-handle = <&phy0>;
  42                         // gpios = <&gpio 42 GPIO_ACTIVE_LOW>;
  43                 };
  44                 ethernet@2 {
  45                         compatible = "lantiq,xrx200-pdi-port";
  46                         reg = <2>;
  47                         phy-mode = "gmii";
  48                         phy-handle = <&phy11>;
  49                 };
  50                 ethernet@4 {
  51                         compatible = "lantiq,xrx200-pdi-port";
  52                         reg = <4>;
  53                         phy-mode = "gmii";
  54                         phy-handle = <&phy13>;
  55                 };
  56                 ethernet@5 {
  57                         compatible = "lantiq,xrx200-pdi-port";
  58                         reg = <5>;
  59                         phy-mode = "rgmii";
  60                         phy-handle = <&phy5>;
  61                 };
  62         };
  63
  64         mdio {
  65                 #address-cells = <1>;
  66                 #size-cells = <0>;
  67                 compatible = "lantiq,xrx200-mdio";
  68
  69                 phy0: ethernet-phy@0 {
  70                         reg = <0x0>;
  71                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  72                 };
  73                 phy5: ethernet-phy@5 {
  74                         reg = <0x5>;
  75                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  76                 };
  77                 phy11: ethernet-phy@11 {
  78                         reg = <0x11>;
  79                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  80                 };
  81                 phy13: ethernet-phy@13 {
  82                         reg = <0x13>;
  83                         compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
  84                 };
  85         };
  86 };
  87
  88 &gphy0 {
  89         lantiq,gphy-mode = <GPHY_MODE_GE>;
  90 };
  91
  92 &gphy1 {
  93         lantiq,gphy-mode = <GPHY_MODE_GE>;
  94 };
  95
  96 &gpio {
  97         pinctrl-names = "default";
  98         pinctrl-0 = <&state_default>;
  99
 100         state_default: pinmux {
 101                 phy-rst {
 102                         lantiq,pins = "io42";
 103                         lantiq,pull = <0>;
 104                         lantiq,open-drain = <0>;
 105                         lantiq,output = <1>;
 106                 };
 107                 pcie-rst {
 108                         lantiq,pins = "io38";
 109                         lantiq,pull = <0>;
 110                         lantiq,output = <1>;
 111                 };
 112         };
 113 };
 114
 115 &pcie0 {
 116         pcie@0 {
 117                 reg = <0 0 0 0 0>;
 118                 #interrupt-cells = <1>;
 119                 #size-cells = <2>;
 120                 #address-cells = <3>;
 121                 device_type = "pci";
 122
 123                 wifi@0,0 {
 124                         reg = <0 0 0 0 0>;
 125                         mediatek,mtd-eeprom = <&radio 0x0000>;
 126                         big-endian;
 127                         ieee80211-freq-limit = <5000000 6000000>;
 128                         mtd-mac-address = <&romfile 0xf100>;
 129                         mtd-mac-address-increment = <2>;
 130                 };
 131         };
 132 };
 133
 134 &pci0 {
 135         status = "okay";
 136         gpio-reset = <&gpio 21 GPIO_ACTIVE_HIGH>;
 137 };
 138
 139 &spi {
 140         status = "okay";
 141
 142         flash@4 {
 143                 compatible = "jedec,spi-nor";
 144                 reg = <4>;
 145                 spi-max-frequency = <33250000>;
 146                 m25p,fast-read;
 147
 148                 partitions {
 149                         compatible = "fixed-partitions";
 150                         #address-cells = <1>;
 151                         #size-cells = <1>;
 152
 153                         partition@0 {
 154                                 reg = <0x0 0x20000>;
 155                                 label = "u-boot";
 156                                 read-only;
 157                         };
 158
 159                         partition@20000 {
 160                                 reg = <0x20000 0xf90000>;
 161                                 label = "firmware";
 162                         };
 163
 164                         partition@fb0000 {
 165                                 reg = <0xfb0000 0x10000>;
 166                                 label = "radioDECT";
 167                                 read-only;
 168                         };
 169
 170                         partition@fc0000 {
 171                                 reg = <0xfc0000 0x10000>;
 172                                 label = "config";
 173                                 read-only;
 174                         };
 175
 176                         romfile: partition@fd0000 {
 177                                 reg = <0xfd0000 0x10000>;
 178                                 label = "romfile";
 179                                 read-only;
 180                         };
 181
 182                         partition@fe0000 {
 183                                 reg = <0xfe0000 0x10000>;
 184                                 label = "rom";
 185                                 read-only;
 186                         };
 187
 188                         radio: partition@ff0000 {
 189                                 reg = <0xff0000 0x10000>;
 190                                 label = "radio";
 191                                 read-only;
 192                         };
 193                 };
 194         };
 195 };
 196
 197 &usb_phy0 {
 198         status = "okay";
 199 };
 200
 201 &usb_phy1 {
 202         status = "okay";
 203 };
 204
 205 &usb0 {
 206         status = "okay";
 207         vbus-supply = <&usb_vbus>;
 208 };
 209
 210 &usb1 {
 211         status = "okay";
 212         vbus-supply = <&usb_vbus>;
 213 };