target/linux/mediatek/dts/mt7622-linksys-e8450.dts

   1 // SPDX-License-Identifier: (GPL-2.0-only OR MIT)
   2
   3 /dts-v1/;
   4 #include <dt-bindings/input/input.h>
   5 #include <dt-bindings/gpio/gpio.h>
   6
   7 #include "mt7622.dtsi"
   8 #include "mt6380.dtsi"
   9
  10 / {
  11         model = "Linksys E8450";
  12         compatible = "linksys,e8450", "mediatek,mt7622";
  13
  14         aliases {
  15                 serial0 = &uart0;
  16                 led-boot = &led_power;
  17                 led-failsafe = &led_power;
  18                 led-running = &led_power;
  19                 led-upgrade = &led_power;
  20         };
  21
  22         chosen {
  23                 stdout-path = "serial0:115200n8";
  24                 bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
  25         };
  26
  27         cpus {
  28                 cpu@0 {
  29                         proc-supply = <&mt6380_vcpu_reg>;
  30                         sram-supply = <&mt6380_vm_reg>;
  31                 };
  32
  33                 cpu@1 {
  34                         proc-supply = <&mt6380_vcpu_reg>;
  35                         sram-supply = <&mt6380_vm_reg>;
  36                 };
  37         };
  38
  39         gpio-keys {
  40                 compatible = "gpio-keys";
  41
  42                 factory {
  43                         label = "reset";
  44                         linux,code = <KEY_RESTART>;
  45                         gpios = <&pio 0 GPIO_ACTIVE_LOW>;
  46                 };
  47
  48                 wps {
  49                         label = "wps";
  50                         linux,code = <KEY_WPS_BUTTON>;
  51                         gpios = <&pio 102 GPIO_ACTIVE_LOW>;
  52                 };
  53         };
  54
  55         gpio-leds {
  56                 compatible = "gpio-leds";
  57
  58                 led_power: power_blue {
  59                         label = "power:blue";
  60                         gpios = <&pio 95 GPIO_ACTIVE_LOW>;
  61                         default-state = "on";
  62                 };
  63
  64                 power_orange {
  65                         label = "power:orange";
  66                         gpios = <&pio 96 GPIO_ACTIVE_LOW>;
  67                         default-state = "off";
  68                 };
  69
  70                 inet_blue {
  71                         label = "inet:blue";
  72                         gpios = <&pio 97 GPIO_ACTIVE_LOW>;
  73                         default-state = "off";
  74                 };
  75
  76                 inet_orange {
  77                         label = "inet:orange";
  78                         gpios = <&pio 98 GPIO_ACTIVE_LOW>;
  79                         default-state = "off";
  80                 };
  81         };
  82
  83         memory {
  84                 reg = <0 0x40000000 0 0x40000000>;
  85         };
  86
  87         reg_1p8v: regulator-1p8v {
  88                 compatible = "regulator-fixed";
  89                 regulator-name = "fixed-1.8V";
  90                 regulator-min-microvolt = <1800000>;
  91                 regulator-max-microvolt = <1800000>;
  92                 regulator-always-on;
  93         };
  94
  95         reg_3p3v: regulator-3p3v {
  96                 compatible = "regulator-fixed";
  97                 regulator-name = "fixed-3.3V";
  98                 regulator-min-microvolt = <3300000>;
  99                 regulator-max-microvolt = <3300000>;
 100                 regulator-boot-on;
 101                 regulator-always-on;
 102         };
 103
 104         reg_5v: regulator-5v {
 105                 compatible = "regulator-fixed";
 106                 regulator-name = "fixed-5V";
 107                 regulator-min-microvolt = <5000000>;
 108                 regulator-max-microvolt = <5000000>;
 109                 regulator-boot-on;
 110                 regulator-always-on;
 111         };
 112 };
 113
 114 &bch {
 115         status = "okay";
 116 };
 117
 118 &btif {
 119         status = "okay";
 120 };
 121
 122 &cir {
 123         pinctrl-names = "default";
 124         pinctrl-0 = <&irrx_pins>;
 125         status = "okay";
 126 };
 127
 128 &eth {
 129         pinctrl-names = "default";
 130         pinctrl-0 = <&eth_pins>;
 131         status = "okay";
 132
 133         gmac0: mac@0 {
 134                 compatible = "mediatek,eth-mac";
 135                 reg = <0>;
 136                 phy-mode = "2500base-x";
 137
 138                 fixed-link {
 139                         speed = <2500>;
 140                         full-duplex;
 141                         pause;
 142                 };
 143         };
 144
 145         mdio-bus {
 146                 #address-cells = <1>;
 147                 #size-cells = <0>;
 148
 149                 switch@0 {
 150                         compatible = "mediatek,mt7531";
 151                         reg = <0>;
 152                         reset-gpios = <&pio 54 0>;
 153
 154                         ports {
 155                                 #address-cells = <1>;
 156                                 #size-cells = <0>;
 157
 158                                 port@0 {
 159                                         reg = <0>;
 160                                         label = "lan1";
 161                                 };
 162
 163                                 port@1 {
 164                                         reg = <1>;
 165                                         label = "lan2";
 166                                 };
 167
 168                                 port@2 {
 169                                         reg = <2>;
 170                                         label = "lan3";
 171                                 };
 172
 173                                 port@3 {
 174                                         reg = <3>;
 175                                         label = "lan4";
 176                                 };
 177
 178                                 port@4 {
 179                                         reg = <4>;
 180                                         label = "wan";
 181                                 };
 182
 183                                 port@6 {
 184                                         reg = <6>;
 185                                         label = "cpu";
 186                                         ethernet = <&gmac0>;
 187                                         phy-mode = "2500base-x";
 188
 189                                         fixed-link {
 190                                                 speed = <2500>;
 191                                                 full-duplex;
 192                                                 pause;
 193                                         };
 194                                 };
 195                         };
 196                 };
 197
 198         };
 199 };
 200
 201 &pcie0 {
 202         pinctrl-names = "default";
 203         pinctrl-0 = <&pcie0_pins>;
 204         status = "okay";
 205 };
 206
 207 &pcie1 {
 208         pinctrl-names = "default";
 209         pinctrl-0 = <&pcie1_pins>;
 210         status = "okay";
 211 };
 212
 213 &slot0 {
 214         mt7915@0,0 {
 215                 reg = <0x0000 0 0 0 0>;
 216                 mediatek,mtd-eeprom = <&factory 0x05000>;
 217         };
 218 };
 219
 220 &pio {
 221         /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
 222          * SATA functions. i.e. output-high: PCIe, output-low: SATA
 223          */
 224 //      asm_sel {
 225 //              gpio-hog;
 226 //              gpios = <90 GPIO_ACTIVE_HIGH>;
 227 //              output-high;
 228 //      };
 229
 230         eth_pins: eth-pins {
 231                 mux {
 232                         function = "eth";
 233                         groups = "mdc_mdio", "rgmii_via_gmac2";
 234                 };
 235         };
 236
 237         irrx_pins: irrx-pins {
 238                 mux {
 239                         function = "ir";
 240                         groups =  "ir_1_rx";
 241                 };
 242         };
 243
 244         irtx_pins: irtx-pins {
 245                 mux {
 246                         function = "ir";
 247                         groups =  "ir_1_tx";
 248                 };
 249         };
 250
 251         pcie0_pins: pcie0-pins {
 252                 mux {
 253                         function = "pcie";
 254                         groups = "pcie0_pad_perst",
 255                                  "pcie0_1_waken",
 256                                  "pcie0_1_clkreq";
 257                 };
 258         };
 259
 260         pcie1_pins: pcie1-pins {
 261                 mux {
 262                         function = "pcie";
 263                         groups = "pcie1_pad_perst",
 264                                  "pcie1_0_waken",
 265                                  "pcie1_0_clkreq";
 266                 };
 267         };
 268
 269         pmic_bus_pins: pmic-bus-pins {
 270                 mux {
 271                         function = "pmic";
 272                         groups = "pmic_bus";
 273                 };
 274         };
 275
 276         pwm7_pins: pwm1-2-pins {
 277                 mux {
 278                         function = "pwm";
 279                         groups = "pwm_ch7_2";
 280                 };
 281         };
 282
 283         wled_pins: wled-pins {
 284                 mux {
 285                         function = "led";
 286                         groups = "wled";
 287                 };
 288         };
 289
 290         /* Serial NAND is shared pin with SPI-NOR */
 291         serial_nand_pins: serial-nand-pins {
 292                 mux {
 293                         function = "flash";
 294                         groups = "snfi";
 295                 };
 296         };
 297
 298         spic0_pins: spic0-pins {
 299                 mux {
 300                         function = "spi";
 301                         groups = "spic0_0";
 302                 };
 303         };
 304
 305         spic1_pins: spic1-pins {
 306                 mux {
 307                         function = "spi";
 308                         groups = "spic1_0";
 309                 };
 310         };
 311
 312         uart0_pins: uart0-pins {
 313                 mux {
 314                         function = "uart";
 315                         groups = "uart0_0_tx_rx" ;
 316                 };
 317         };
 318
 319         uart2_pins: uart2-pins {
 320                 mux {
 321                         function = "uart";
 322                         groups = "uart2_1_tx_rx" ;
 323                 };
 324         };
 325
 326         watchdog_pins: watchdog-pins {
 327                 mux {
 328                         function = "watchdog";
 329                         groups = "watchdog";
 330                 };
 331         };
 332 };
 333
 334 &pwm {
 335         pinctrl-names = "default";
 336         pinctrl-0 = <&pwm7_pins>;
 337         status = "okay";
 338 };
 339
 340 &pwrap {
 341         pinctrl-names = "default";
 342         pinctrl-0 = <&pmic_bus_pins>;
 343
 344         status = "okay";
 345 };
 346
 347 &sata {
 348         status = "disabled";
 349 };
 350
 351 &sata_phy {
 352         status = "disabled";
 353 };
 354
 355 &snfi {
 356         pinctrl-names = "default";
 357         pinctrl-0 = <&serial_nand_pins>;
 358         status = "okay";
 359
 360         spi_nand@0 {
 361                 #address-cells = <1>;
 362                 #size-cells = <1>;
 363                 compatible = "spi-nand";
 364                 spi-max-frequency = <104000000>;
 365                 reg = <0>;
 366
 367                 mediatek,bmt-v2;
 368                 mediatek,bmt-table-size = <0x1000>;
 369
 370                 partitions {
 371                         compatible = "fixed-partitions";
 372                         #address-cells = <1>;
 373                         #size-cells = <1>;
 374
 375                         partition@0 {
 376                                 label = "Preloader";
 377                                 reg = <0x00000 0x0080000>;
 378                                 read-only;
 379                         };
 380
 381                         partition@80000 {
 382                                 label = "ATF";
 383                                 reg = <0x80000 0x0040000>;
 384                         };
 385
 386                         partition@c0000 {
 387                                 label = "u-boot";
 388                                 reg = <0xc0000 0x0080000>;
 389                         };
 390
 391                         partition@140000 {
 392                                 label = "u-boot-env";
 393                                 reg = <0x140000 0x0080000>;
 394                         };
 395
 396                         factory: partition@1c0000 {
 397                                 label = "factory";
 398                                 reg = <0x1c0000 0x0100000>;
 399                         };
 400
 401                         partition@300000 {
 402                                 label = "devinfo";
 403                                 reg = <0x300000 0x020000>;
 404                         };
 405
 406                         partition@320000 {
 407                                 label = "senv";
 408                                 reg = <0x320000 0x020000>;
 409                         };
 410
 411                         partition@360000 {
 412                                 label = "bootseq";
 413                                 reg = <0x360000 0x020000>;
 414                         };
 415
 416                         partition@500000 {
 417                                 label = "firmware1";
 418                                 compatible = "denx,fit";
 419                                 openwrt,cmdline-match = "mtdparts=master";
 420                                 reg = <0x500000 0x1E00000>;
 421                         };
 422
 423                         partition@2300000 {
 424                                 label = "firmware2";
 425                                 compatible = "denx,fit";
 426                                 openwrt,cmdline-match = "mtdparts=slave";
 427                                 reg = <0x2300000 0x1E00000>;
 428                         };
 429
 430                         partition@4100000 {
 431                                 label = "data";
 432                                 reg = <0x4100000 0x1900000>;
 433                         };
 434
 435                         partition@5100000 {
 436                                 label = "mfg";
 437                                 reg = <0x5a00000 0x1400000>;
 438                         };
 439                 };
 440         };
 441 };
 442
 443 &spi0 {
 444         pinctrl-names = "default";
 445         pinctrl-0 = <&spic0_pins>;
 446         status = "okay";
 447 };
 448
 449 &spi1 {
 450         pinctrl-names = "default";
 451         pinctrl-0 = <&spic1_pins>;
 452         status = "okay";
 453 };
 454
 455 &ssusb {
 456         vusb33-supply = <&reg_3p3v>;
 457         vbus-supply = <&reg_5v>;
 458         status = "okay";
 459 };
 460
 461 &u3phy {
 462         status = "okay";
 463 };
 464
 465 &uart0 {
 466         pinctrl-names = "default";
 467         pinctrl-0 = <&uart0_pins>;
 468         status = "okay";
 469 };
 470
 471 &uart2 {
 472         pinctrl-names = "default";
 473         pinctrl-0 = <&uart2_pins>;
 474         status = "okay";
 475 };
 476
 477 &watchdog {
 478         pinctrl-names = "default";
 479         pinctrl-0 = <&watchdog_pins>;
 480         status = "okay";
 481 };
 482
 483 &wmac {
 484         mediatek,mtd-eeprom = <&factory 0x0000>;
 485         status = "okay";
 486 };