target/linux/mvebu/patches-5.4/004-v5.5-arm64-dts-marvell-Add-AP807-quad-cache-description.patch

   1 From 30d53abdc60a6515f02f181e7c39b7b23d5fb3aa Mon Sep 17 00:00:00 2001
   2 From: Grzegorz Jaszczyk <jaz@semihalf.com>
   3 Date: Fri, 4 Oct 2019 16:27:27 +0200
   4 Subject: [PATCH] arm64: dts: marvell: Add AP807-quad cache description
   5
   6 Adding appropriate entries to device-tree allows the cache description
   7 to show up in sysfs under: /sys/devices/system/cpu/cpuX/cache/.
   8
   9 Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com>
  10 Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
  11 Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
  12 ---
  13  .../boot/dts/marvell/armada-ap807-quad.dtsi   | 42 +++++++++++++++++++
  14  1 file changed, 42 insertions(+)
  15
  16 --- a/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
  17 +++ b/arch/arm64/boot/dts/marvell/armada-ap807-quad.dtsi
  18 @@ -22,6 +22,13 @@
  19                         enable-method = "psci";
  20                         #cooling-cells = <2>;
  21                         clocks = <&cpu_clk 0>;
  22 +                       i-cache-size = <0xc000>;
  23 +                       i-cache-line-size = <64>;
  24 +                       i-cache-sets = <256>;
  25 +                       d-cache-size = <0x8000>;
  26 +                       d-cache-line-size = <64>;
  27 +                       d-cache-sets = <256>;
  28 +                       next-level-cache = <&l2_0>;
  29                 };
  30                 cpu1: cpu@1 {
  31                         device_type = "cpu";
  32 @@ -30,6 +37,13 @@
  33                         enable-method = "psci";
  34                         #cooling-cells = <2>;
  35                         clocks = <&cpu_clk 0>;
  36 +                       i-cache-size = <0xc000>;
  37 +                       i-cache-line-size = <64>;
  38 +                       i-cache-sets = <256>;
  39 +                       d-cache-size = <0x8000>;
  40 +                       d-cache-line-size = <64>;
  41 +                       d-cache-sets = <256>;
  42 +                       next-level-cache = <&l2_0>;
  43                 };
  44                 cpu2: cpu@100 {
  45                         device_type = "cpu";
  46 @@ -38,6 +52,13 @@
  47                         enable-method = "psci";
  48                         #cooling-cells = <2>;
  49                         clocks = <&cpu_clk 1>;
  50 +                       i-cache-size = <0xc000>;
  51 +                       i-cache-line-size = <64>;
  52 +                       i-cache-sets = <256>;
  53 +                       d-cache-size = <0x8000>;
  54 +                       d-cache-line-size = <64>;
  55 +                       d-cache-sets = <256>;
  56 +                       next-level-cache = <&l2_1>;
  57                 };
  58                 cpu3: cpu@101 {
  59                         device_type = "cpu";
  60 @@ -46,6 +67,27 @@
  61                         enable-method = "psci";
  62                         #cooling-cells = <2>;
  63                         clocks = <&cpu_clk 1>;
  64 +                       i-cache-size = <0xc000>;
  65 +                       i-cache-line-size = <64>;
  66 +                       i-cache-sets = <256>;
  67 +                       d-cache-size = <0x8000>;
  68 +                       d-cache-line-size = <64>;
  69 +                       d-cache-sets = <256>;
  70 +                       next-level-cache = <&l2_1>;
  71 +               };
  72 +
  73 +               l2_0: l2-cache0 {
  74 +                       compatible = "cache";
  75 +                       cache-size = <0x80000>;
  76 +                       cache-line-size = <64>;
  77 +                       cache-sets = <512>;
  78 +               };
  79 +
  80 +               l2_1: l2-cache1 {
  81 +                       compatible = "cache";
  82 +                       cache-size = <0x80000>;
  83 +                       cache-line-size = <64>;
  84 +                       cache-sets = <512>;
  85                 };
  86         };
  87  };