target/linux/mvebu/patches-5.4/016-PCI-aardvark-Train-link-immediately-after-enabling-t.patch

   1 From 6964494582f56a3882c2c53b0edbfe99eb32b2e1 Mon Sep 17 00:00:00 2001
   2 From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
   3 Date: Thu, 30 Apr 2020 10:06:14 +0200
   4 Subject: [PATCH] PCI: aardvark: Train link immediately after enabling training
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8
   9 Adding even 100ms (PCI_PM_D3COLD_WAIT) delay between enabling link
  10 training and starting link training causes detection issues with some
  11 buggy cards (such as Compex WLE900VX).
  12
  13 Move the code which enables link training immediately before the one
  14 which starts link traning.
  15
  16 This fixes detection issues of Compex WLE900VX card on Turris MOX after
  17 cold boot.
  18
  19 Link: https://lore.kernel.org/r/20200430080625.26070-2-pali@kernel.org
  20 Fixes: f4c7d053d7f7 ("PCI: aardvark: Wait for endpoint to be ready...")
  21 Tested-by: Tomasz Maciej Nowak <tmn505@gmail.com>
  22 Signed-off-by: Pali Rohár <pali@kernel.org>
  23 Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
  24 Acked-by: Rob Herring <robh@kernel.org>
  25 Acked-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
  26 ---
  27  drivers/pci/controller/pci-aardvark.c | 15 +++++++++------
  28  1 file changed, 9 insertions(+), 6 deletions(-)
  29
  30 --- a/drivers/pci/controller/pci-aardvark.c
  31 +++ b/drivers/pci/controller/pci-aardvark.c
  32 @@ -315,11 +315,6 @@ static void advk_pcie_setup_hw(struct ad
  33         reg |= LANE_COUNT_1;
  34         advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  35
  36 -       /* Enable link training */
  37 -       reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  38 -       reg |= LINK_TRAINING_EN;
  39 -       advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  40 -
  41         /* Enable MSI */
  42         reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
  43         reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
  44 @@ -361,7 +356,15 @@ static void advk_pcie_setup_hw(struct ad
  45          */
  46         msleep(PCI_PM_D3COLD_WAIT);
  47
  48 -       /* Start link training */
  49 +       /* Enable link training */
  50 +       reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
  51 +       reg |= LINK_TRAINING_EN;
  52 +       advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
  53 +
  54 +       /*
  55 +        * Start link training immediately after enabling it.
  56 +        * This solves problems for some buggy cards.
  57 +        */
  58         reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
  59         reg |= PCIE_CORE_LINK_TRAINING;
  60         advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);