target/linux/ramips/dts/UBNT-ER-e50.dtsi

   1 #include "mt7621.dtsi"
   2
   3 #include <dt-bindings/gpio/gpio.h>
   4 #include <dt-bindings/input/input.h>
   5
   6 / {
   7         compatible = "ubiquiti,edgerouterx", "mediatek,mt7621-soc";
   8
   9         memory@0 {
  10                 device_type = "memory";
  11                 reg = <0x0 0x10000000>;
  12         };
  13
  14         chosen {
  15                 bootargs = "console=ttyS0,57600";
  16         };
  17
  18         gpio-keys-polled {
  19                 compatible = "gpio-keys-polled";
  20                 poll-interval = <20>;
  21
  22                 reset {
  23                         label = "reset";
  24                         gpios = <&gpio0 12 GPIO_ACTIVE_LOW>;
  25                         linux,code = <KEY_RESTART>;
  26                 };
  27         };
  28 };
  29
  30 &ethernet {
  31         mtd-mac-address = <&factory 0x22>;
  32 };
  33
  34 &nand {
  35         status = "okay";
  36
  37         partition@0 {
  38                 label = "u-boot";
  39                 reg = <0x0 0x80000>;
  40                 read-only;
  41         };
  42
  43         partition@80000 {
  44                 label = "u-boot-env";
  45                 reg = <0x80000 0x60000>;
  46                 read-only;
  47         };
  48
  49         factory: partition@e0000 {
  50                 label = "factory";
  51                 reg = <0xe0000 0x60000>;
  52         };
  53
  54         partition@140000 {
  55                 label = "kernel1";
  56                 reg = <0x140000 0x300000>;
  57         };
  58
  59         partition@440000 {
  60                 label = "kernel2";
  61                 reg = <0x440000 0x300000>;
  62         };
  63
  64         partition@740000 {
  65                 label = "ubi";
  66                 reg = <0x740000 0xf7c0000>;
  67         };
  68 };
  69
  70 &pinctrl {
  71         state_default: pinctrl0 {
  72                 gpio {
  73                         ralink,group = "uart2", "uart3", "i2c", "pcie", "rgmii2", "jtag";
  74                         ralink,function = "gpio";
  75                 };
  76         };
  77 };
  78
  79 &spi0 {
  80         /*
  81          * This board has 2Mb spi flash soldered in and visible
  82          * from manufacturer's firmware.
  83          * But this SoC shares spi and nand pins,
  84          * and current driver doesn't handle this sharing well
  85          */
  86         status = "disabled";
  87
  88         m25p80@0 {
  89                 #address-cells = <1>;
  90                 #size-cells = <1>;
  91                 compatible = "jedec,spi-nor";
  92                 reg = <1>;
  93                 spi-max-frequency = <10000000>;
  94                 m25p,chunked-io = <32>;
  95
  96                 partition@0 {
  97                         label = "spi";
  98                         reg = <0x0 0x200000>;
  99                         read-only;
 100                 };
 101         };
 102 };
 103
 104 &xhci {
 105         status = "disabled";
 106 };