target/linux/ramips/dts/mt7620a_lb-link_bl-w1200.dts

   1 // SPDX-License-Identifier: GPL-2.0-only
   2
   3 #include "mt7620a.dtsi"
   4
   5 #include <dt-bindings/gpio/gpio.h>
   6 #include <dt-bindings/input/input.h>
   7
   8 / {
   9         compatible = "lb-link,bl-w1200", "ralink,mt7620a-soc";
  10         model = "LB-Link BL-W1200";
  11
  12         aliases {
  13                 led-boot = &led_wps;
  14                 led-failsafe = &led_wps;
  15                 led-upgrade = &led_wps;
  16         };
  17
  18         keys {
  19                 compatible = "gpio-keys";
  20
  21                 reset_wps {
  22                         label = "reset_wps";
  23                         gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
  24                         linux,code = <KEY_RESTART>;
  25                 };
  26         };
  27
  28         leds {
  29                 compatible = "gpio-leds";
  30
  31                 led_wps: wps {
  32                         label = "green:wps";
  33                         gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
  34                 };
  35         };
  36 };
  37
  38 &gpio1 {
  39         status = "okay";
  40 };
  41
  42 &spi0 {
  43         status = "okay";
  44
  45         flash@0 {
  46                 compatible = "jedec,spi-nor";
  47                 reg = <0>;
  48                 spi-max-frequency = <50000000>;
  49
  50                 partitions {
  51                         compatible = "fixed-partitions";
  52                         #address-cells = <1>;
  53                         #size-cells = <1>;
  54
  55                         partition@0 {
  56                                 label = "u-boot";
  57                                 reg = <0x0 0x30000>;
  58                                 read-only;
  59                         };
  60
  61                         partition@30000 {
  62                                 label = "config";
  63                                 reg = <0x30000 0x10000>;
  64                                 read-only;
  65                         };
  66
  67                         factory: partition@40000 {
  68                                 label = "factory";
  69                                 reg = <0x40000 0x10000>;
  70                                 read-only;
  71                         };
  72
  73                         partition@50000 {
  74                                 compatible = "denx,uimage";
  75                                 label = "firmware";
  76                                 reg = <0x50000 0x7b0000>;
  77                         };
  78                 };
  79         };
  80 };
  81
  82 &state_default {
  83         gpio {
  84                 groups = "uartf", "spi refclk";
  85                 function = "gpio";
  86         };
  87 };
  88
  89 &ethernet {
  90         pinctrl-names = "default";
  91         pinctrl-0 = <&rgmii2_pins &mdio_pins>;
  92
  93         nvmem-cells = <&macaddr_factory_28>;
  94         nvmem-cell-names = "mac-address";
  95
  96         mediatek,portmap = "wllll";
  97
  98         port@5 {
  99                 status = "okay";
 100                 mediatek,fixed-link = <1000 1 1 1>;
 101                 phy-mode = "rgmii";
 102         };
 103
 104         mdio-bus {
 105                 status = "okay";
 106
 107                 ethernet-phy@0 {
 108                         reg = <0>;
 109                         phy-mode = "rgmii";
 110                 };
 111
 112                 ethernet-phy@1 {
 113                         reg = <1>;
 114                         phy-mode = "rgmii";
 115                 };
 116
 117                 ethernet-phy@2 {
 118                         reg = <2>;
 119                         phy-mode = "rgmii";
 120                 };
 121
 122                 ethernet-phy@3 {
 123                         reg = <3>;
 124                         phy-mode = "rgmii";
 125                 };
 126
 127                 ethernet-phy@4 {
 128                         reg = <4>;
 129                         phy-mode = "rgmii";
 130                 };
 131
 132                 ethernet-phy@1f {
 133                         reg = <0x1f>;
 134                         phy-mode = "rgmii";
 135                 };
 136         };
 137 };
 138
 139 &gsw {
 140         mediatek,ephy-base = /bits/ 8 <12>;
 141 };
 142
 143 &wmac {
 144         ralink,mtd-eeprom = <&factory 0x0>;
 145 };
 146
 147 &pcie {
 148         status = "okay";
 149 };
 150
 151 &pcie0 {
 152         wifi@0,0 {
 153                 compatible = "mediatek,mt76";
 154                 reg = <0x0000 0 0 0 0>;
 155                 ieee80211-freq-limit = <5000000 6000000>;
 156                 mediatek,mtd-eeprom = <&factory 0x8000>;
 157
 158                 led {
 159                         led-sources = <2>;
 160                         led-active-low;
 161                 };
 162         };
 163 };
 164
 165 &ehci {
 166         status = "okay";
 167 };
 168
 169 &ohci {
 170         status = "okay";
 171 };
 172
 173 &factory {
 174         compatible = "nvmem-cells";
 175         #address-cells = <1>;
 176         #size-cells = <1>;
 177
 178         macaddr_factory_28: macaddr@28 {
 179                 reg = <0x28 0x6>;
 180         };
 181 };