6cb2c8b225d639edf76a8f3f2f1b627a31a40601
[openwrt/staging/mkresin.git] / target / linux / ramips / dts / mt7620a_zte_q7.dts
1 #include "mt7620a.dtsi"
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5
6 / {
7 compatible = "zte,q7", "ralink,mt7620a-soc";
8 model = "ZTE Q7";
9
10 aliases {
11 led-boot = &led_status_blue;
12 led-failsafe = &led_status_blue;
13 led-running = &led_status_blue;
14 led-upgrade = &led_status_blue;
15 };
16
17 leds {
18 compatible = "gpio-leds";
19
20 statred {
21 label = "zte-q7:red:status";
22 gpios = <&gpio0 13 GPIO_ACTIVE_LOW>;
23 };
24
25 led_status_blue: statblue {
26 label = "zte-q7:blue:status";
27 gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
28 };
29 };
30
31 keys {
32 compatible = "gpio-keys";
33
34 reset {
35 label = "reset";
36 gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
37 linux,code = <KEY_RESTART>;
38 };
39 };
40 };
41
42 &gpio0 {
43 status = "okay";
44 };
45
46 &gpio1 {
47 status = "okay";
48 };
49
50 &spi0 {
51 status = "okay";
52
53 flash@0 {
54 compatible = "jedec,spi-nor";
55 reg = <0>;
56 spi-max-frequency = <10000000>;
57
58 partitions {
59 compatible = "fixed-partitions";
60 #address-cells = <1>;
61 #size-cells = <1>;
62
63 partition@0 {
64 label = "u-boot";
65 reg = <0x0 0x30000>;
66 read-only;
67 };
68
69 partition@30000 {
70 label = "u-boot-env";
71 reg = <0x30000 0x10000>;
72 read-only;
73 };
74
75 factory: partition@40000 {
76 label = "factory";
77 reg = <0x40000 0x10000>;
78 read-only;
79 };
80
81 partition@50000 {
82 compatible = "denx,uimage";
83 label = "firmware";
84 reg = <0x50000 0x7b0000>;
85 };
86 };
87 };
88 };
89
90 &state_default {
91 gpio {
92 groups = "i2c", "uartf", "rgmii1", "rgmii2", "ephy", "wled";
93 function = "gpio";
94 };
95 };
96
97 &ethernet {
98 mtd-mac-address = <&factory 0x4>;
99
100 mediatek,portmap = "wllll";
101 };
102
103 &wmac {
104 ralink,mtd-eeprom = <&factory 0x0>;
105 };
106
107 &sdhci {
108 status = "okay";
109 };
110
111 &ehci {
112 status = "okay";
113 };
114
115 &ohci {
116 status = "okay";
117 };
118
119 &gsw {
120 mediatek,port4 = "ephy";
121 };