target/linux/ramips/dts/mt7628an.dtsi

   1 / {
   2         #address-cells = <1>;
   3         #size-cells = <1>;
   4         compatible = "mediatek,mt7628an-soc";
   5
   6         cpus {
   7                 #address-cells = <1>;
   8                 #size-cells = <0>;
   9
  10                 cpu@0 {
  11                         compatible = "mips,mips24KEc";
  12                         reg = <0>;
  13                 };
  14         };
  15
  16         chosen {
  17                 bootargs = "console=ttyS0,57600";
  18         };
  19
  20         aliases {
  21                 serial0 = &uartlite;
  22         };
  23
  24         cpuintc: cpuintc {
  25                 #address-cells = <0>;
  26                 #interrupt-cells = <1>;
  27                 interrupt-controller;
  28                 compatible = "mti,cpu-interrupt-controller";
  29         };
  30
  31         palmbus: palmbus@10000000 {
  32                 compatible = "palmbus";
  33                 reg = <0x10000000 0x200000>;
  34                 ranges = <0x0 0x10000000 0x1FFFFF>;
  35
  36                 #address-cells = <1>;
  37                 #size-cells = <1>;
  38
  39                 sysc: sysc@0 {
  40                         compatible = "ralink,mt7620a-sysc", "syscon";
  41                         reg = <0x0 0x100>;
  42                 };
  43
  44                 watchdog: watchdog@100 {
  45                         compatible = "ralink,mt7628an-wdt", "mediatek,mt7621-wdt";
  46                         reg = <0x100 0x30>;
  47
  48                         resets = <&rstctrl 8>;
  49                         reset-names = "wdt";
  50
  51                         interrupt-parent = <&intc>;
  52                         interrupts = <24>;
  53                 };
  54
  55                 intc: intc@200 {
  56                         compatible = "ralink,mt7628an-intc", "ralink,rt2880-intc";
  57                         reg = <0x200 0x100>;
  58
  59                         resets = <&rstctrl 9>;
  60                         reset-names = "intc";
  61
  62                         interrupt-controller;
  63                         #interrupt-cells = <1>;
  64
  65                         interrupt-parent = <&cpuintc>;
  66                         interrupts = <2>;
  67
  68                         ralink,intc-registers = <0x9c 0xa0
  69                                                  0x6c 0xa4
  70                                                  0x80 0x78>;
  71                 };
  72
  73                 memc: memc@300 {
  74                         compatible = "ralink,mt7620a-memc", "ralink,rt3050-memc";
  75                         reg = <0x300 0x100>;
  76
  77                         resets = <&rstctrl 20>;
  78                         reset-names = "mc";
  79
  80                         interrupt-parent = <&intc>;
  81                         interrupts = <3>;
  82                 };
  83
  84                 gpio@600 {
  85                         #address-cells = <1>;
  86                         #size-cells = <0>;
  87
  88                         compatible = "mtk,mt7628-gpio", "mtk,mt7621-gpio";
  89                         reg = <0x600 0x100>;
  90
  91                         interrupt-parent = <&intc>;
  92                         interrupts = <6>;
  93
  94                         gpio0: bank@0 {
  95                                 reg = <0>;
  96                                 compatible = "mtk,mt7621-gpio-bank";
  97                                 gpio-controller;
  98                                 #gpio-cells = <2>;
  99                         };
 100
 101                         gpio1: bank@1 {
 102                                 reg = <1>;
 103                                 compatible = "mtk,mt7621-gpio-bank";
 104                                 gpio-controller;
 105                                 #gpio-cells = <2>;
 106                         };
 107
 108                         gpio2: bank@2 {
 109                                 reg = <2>;
 110                                 compatible = "mtk,mt7621-gpio-bank";
 111                                 gpio-controller;
 112                                 #gpio-cells = <2>;
 113                         };
 114                 };
 115
 116                 i2c: i2c@900 {
 117                         compatible = "mediatek,mt7621-i2c";
 118                         reg = <0x900 0x100>;
 119
 120                         resets = <&rstctrl 16>;
 121                         reset-names = "i2c";
 122
 123                         #address-cells = <1>;
 124                         #size-cells = <0>;
 125
 126                         status = "disabled";
 127
 128                         pinctrl-names = "default";
 129                         pinctrl-0 = <&i2c_pins>;
 130                 };
 131
 132                 i2s: i2s@a00 {
 133                         compatible = "mediatek,mt7628-i2s";
 134                         reg = <0xa00 0x100>;
 135
 136                         resets = <&rstctrl 17>;
 137                         reset-names = "i2s";
 138
 139                         interrupt-parent = <&intc>;
 140                         interrupts = <10>;
 141
 142                         txdma-req = <2>;
 143                         rxdma-req = <3>;
 144
 145                         dmas = <&gdma 4>,
 146                                 <&gdma 6>;
 147                         dma-names = "tx", "rx";
 148
 149                         status = "disabled";
 150                 };
 151
 152                 spi0: spi@b00 {
 153                         compatible = "ralink,mt7621-spi";
 154                         reg = <0xb00 0x100>;
 155
 156                         resets = <&rstctrl 18>;
 157                         reset-names = "spi";
 158
 159                         #address-cells = <1>;
 160                         #size-cells = <0>;
 161
 162                         pinctrl-names = "default";
 163                         pinctrl-0 = <&spi_pins>;
 164
 165                         status = "disabled";
 166                 };
 167
 168                 uartlite: uartlite@c00 {
 169                         compatible = "ns16550a";
 170                         reg = <0xc00 0x100>;
 171
 172                         reg-shift = <2>;
 173                         reg-io-width = <4>;
 174                         no-loopback-test;
 175
 176                         clock-frequency = <40000000>;
 177
 178                         resets = <&rstctrl 12>;
 179                         reset-names = "uartl";
 180
 181                         interrupt-parent = <&intc>;
 182                         interrupts = <20>;
 183
 184                         pinctrl-names = "default";
 185                         pinctrl-0 = <&uart0_pins>;
 186                 };
 187
 188                 uart1: uart1@d00 {
 189                         compatible = "ns16550a";
 190                         reg = <0xd00 0x100>;
 191
 192                         reg-shift = <2>;
 193                         reg-io-width = <4>;
 194                         no-loopback-test;
 195
 196                         clock-frequency = <40000000>;
 197
 198                         resets = <&rstctrl 19>;
 199                         reset-names = "uart1";
 200
 201                         interrupt-parent = <&intc>;
 202                         interrupts = <21>;
 203
 204                         pinctrl-names = "default";
 205                         pinctrl-0 = <&uart1_pins>;
 206
 207                         status = "disabled";
 208                 };
 209
 210                 uart2: uart2@e00 {
 211                         compatible = "ns16550a";
 212                         reg = <0xe00 0x100>;
 213
 214                         reg-shift = <2>;
 215                         reg-io-width = <4>;
 216                         no-loopback-test;
 217
 218                         clock-frequency = <40000000>;
 219
 220                         resets = <&rstctrl 20>;
 221                         reset-names = "uart2";
 222
 223                         interrupt-parent = <&intc>;
 224                         interrupts = <22>;
 225
 226                         pinctrl-names = "default";
 227                         pinctrl-0 = <&uart2_pins>;
 228
 229                         status = "disabled";
 230                 };
 231
 232                 pwm: pwm@5000 {
 233                         compatible = "mediatek,mt7628-pwm";
 234                         reg = <0x5000 0x1000>;
 235                         #pwm-cells = <2>;
 236
 237                         resets = <&rstctrl 31>;
 238                         reset-names = "pwm";
 239
 240                         pinctrl-names = "default";
 241                         pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>;
 242
 243                         status = "disabled";
 244                 };
 245
 246                 pcm: pcm@2000 {
 247                         compatible = "ralink,mt7620a-pcm";
 248                         reg = <0x2000 0x800>;
 249
 250                         resets = <&rstctrl 11>;
 251                         reset-names = "pcm";
 252
 253                         interrupt-parent = <&intc>;
 254                         interrupts = <4>;
 255
 256                         status = "disabled";
 257                 };
 258
 259                 gdma: gdma@2800 {
 260                         compatible = "ralink,rt3883-gdma";
 261                         reg = <0x2800 0x800>;
 262
 263                         resets = <&rstctrl 14>;
 264                         reset-names = "dma";
 265
 266                         interrupt-parent = <&intc>;
 267                         interrupts = <7>;
 268
 269                         #dma-cells = <1>;
 270                         #dma-channels = <16>;
 271                         #dma-requests = <16>;
 272
 273                         status = "disabled";
 274                 };
 275         };
 276
 277         pinctrl: pinctrl {
 278                 compatible = "ralink,rt2880-pinmux";
 279                 pinctrl-names = "default";
 280                 pinctrl-0 = <&state_default>;
 281
 282                 state_default: pinctrl0 {
 283                 };
 284
 285                 spi_pins: spi_pins {
 286                         spi_pins {
 287                                 ralink,group = "spi";
 288                                 ralink,function = "spi";
 289                         };
 290                 };
 291
 292                 spi_cs1_pins: spi_cs1 {
 293                         spi_cs1 {
 294                                 ralink,group = "spi cs1";
 295                                 ralink,function = "spi cs1";
 296                         };
 297                 };
 298
 299                 i2c_pins: i2c_pins {
 300                         i2c_pins {
 301                                 ralink,group = "i2c";
 302                                 ralink,function = "i2c";
 303                         };
 304                 };
 305
 306                 i2s_pins: i2s {
 307                         i2s {
 308                                 ralink,group = "i2s";
 309                                 ralink,function = "i2s";
 310                         };
 311                 };
 312
 313                 uart0_pins: uartlite {
 314                         uartlite {
 315                                 ralink,group = "uart0";
 316                                 ralink,function = "uart0";
 317                         };
 318                 };
 319
 320                 uart1_pins: uart1 {
 321                         uart1 {
 322                                 ralink,group = "uart1";
 323                                 ralink,function = "uart1";
 324                         };
 325                 };
 326
 327                 uart2_pins: uart2 {
 328                         uart2 {
 329                                 ralink,group = "uart2";
 330                                 ralink,function = "uart2";
 331                         };
 332                 };
 333
 334                 sdxc_pins: sdxc {
 335                         sdxc {
 336                                 ralink,group = "sdmode";
 337                                 ralink,function = "sdxc";
 338                         };
 339                 };
 340
 341                 pwm0_pins: pwm0 {
 342                         pwm0 {
 343                                 ralink,group = "pwm0";
 344                                 ralink,function = "pwm0";
 345                         };
 346                 };
 347
 348                 pwm1_pins: pwm1 {
 349                         pwm1 {
 350                                 ralink,group = "pwm1";
 351                                 ralink,function = "pwm1";
 352                         };
 353                 };
 354
 355                 pcm_i2s_pins: pcm_i2s {
 356                         pcm_i2s {
 357                                 ralink,group = "i2s";
 358                                 ralink,function = "pcm";
 359                         };
 360                 };
 361
 362                 refclk_pins: refclk {
 363                         refclk {
 364                                 ralink,group = "refclk";
 365                                 ralink,function = "refclk";
 366                         };
 367                 };
 368         };
 369
 370         rstctrl: rstctrl {
 371                 compatible = "ralink,mt7620a-reset", "ralink,rt2880-reset";
 372                 #reset-cells = <1>;
 373         };
 374
 375         clkctrl: clkctrl {
 376                 compatible = "ralink,rt2880-clock";
 377                 #clock-cells = <1>;
 378         };
 379
 380         usbphy: usbphy@10120000 {
 381                 compatible = "mediatek,mt7628-usbphy", "mediatek,mt7620-usbphy";
 382                 reg = <0x10120000 0x1000>;
 383                 #phy-cells = <0>;
 384
 385                 ralink,sysctl = <&sysc>;
 386                 resets = <&rstctrl 22 &rstctrl 25>;
 387                 reset-names = "host", "device";
 388                 clocks = <&clkctrl 22 &clkctrl 25>;
 389                 clock-names = "host", "device";
 390         };
 391
 392         sdhci: sdhci@10130000 {
 393                 compatible = "ralink,mt7620-sdhci";
 394                 reg = <0x10130000 0x4000>;
 395
 396                 interrupt-parent = <&intc>;
 397                 interrupts = <14>;
 398
 399                 pinctrl-names = "default";
 400                 pinctrl-0 = <&sdxc_pins>;
 401
 402                 status = "disabled";
 403         };
 404
 405         ehci: ehci@101c0000 {
 406                 #address-cells = <1>;
 407                 #size-cells = <0>;
 408                 compatible = "generic-ehci";
 409                 reg = <0x101c0000 0x1000>;
 410
 411                 phys = <&usbphy>;
 412                 phy-names = "usb";
 413
 414                 interrupt-parent = <&intc>;
 415                 interrupts = <18>;
 416
 417                 ehci_port1: port@1 {
 418                         reg = <1>;
 419                         #trigger-source-cells = <0>;
 420                 };
 421         };
 422
 423         ohci: ohci@101c1000 {
 424                 #address-cells = <1>;
 425                 #size-cells = <0>;
 426                 compatible = "generic-ohci";
 427                 reg = <0x101c1000 0x1000>;
 428
 429                 phys = <&usbphy>;
 430                 phy-names = "usb";
 431
 432                 interrupt-parent = <&intc>;
 433                 interrupts = <18>;
 434
 435                 ohci_port1: port@1 {
 436                         reg = <1>;
 437                         #trigger-source-cells = <0>;
 438                 };
 439         };
 440
 441         ethernet: ethernet@10100000 {
 442                 compatible = "ralink,rt5350-eth";
 443                 reg = <0x10100000 0x10000>;
 444
 445                 interrupt-parent = <&cpuintc>;
 446                 interrupts = <5>;
 447
 448                 resets = <&rstctrl 21 &rstctrl 23>;
 449                 reset-names = "fe", "esw";
 450
 451                 mediatek,switch = <&esw>;
 452         };
 453
 454         esw: esw@10110000 {
 455                 compatible = "mediatek,mt7628-esw", "ralink,rt3050-esw";
 456                 reg = <0x10110000 0x8000>;
 457
 458                 resets = <&rstctrl 23>;
 459                 reset-names = "esw";
 460
 461                 interrupt-parent = <&intc>;
 462                 interrupts = <17>;
 463         };
 464
 465         pcie: pcie@10140000 {
 466                 compatible = "mediatek,mt7620-pci";
 467                 reg = <0x10140000 0x100
 468                         0x10142000 0x100>;
 469
 470                 #address-cells = <3>;
 471                 #size-cells = <2>;
 472
 473                 interrupt-parent = <&cpuintc>;
 474                 interrupts = <4>;
 475
 476                 resets = <&rstctrl 26 &rstctrl 27>;
 477                 reset-names = "pcie0", "pcie1";
 478                 clocks = <&clkctrl 26 &clkctrl 27>;
 479                 clock-names = "pcie0", "pcie1";
 480
 481                 status = "disabled";
 482
 483                 device_type = "pci";
 484
 485                 bus-range = <0 255>;
 486                 ranges = <
 487                         0x02000000 0 0x00000000 0x20000000 0 0x10000000 /* pci memory */
 488                         0x01000000 0 0x00000000 0x10160000 0 0x00010000 /* io space */
 489                 >;
 490
 491                 pcie0: pcie@0,0 {
 492                         reg = <0x0000 0 0 0 0>;
 493
 494                         #address-cells = <3>;
 495                         #size-cells = <2>;
 496
 497                         device_type = "pci";
 498
 499                         ranges;
 500                 };
 501         };
 502
 503         wmac: wmac@10300000 {
 504                 compatible = "mediatek,mt7628-wmac";
 505                 reg = <0x10300000 0x100000>;
 506
 507                 interrupt-parent = <&cpuintc>;
 508                 interrupts = <6>;
 509
 510                 status = "disabled";
 511
 512                 mediatek,mtd-eeprom = <&factory 0x0000>;
 513         };
 514 };