d173f5369727dc6cae9b1a03e9c43ddb75873b23
[openwrt/staging/stintel.git] / target / linux / ramips / dts / mt7628an_zyxel_keenetic-extra-ii.dts
1 #include "mt7628an.dtsi"
2
3 #include <dt-bindings/gpio/gpio.h>
4 #include <dt-bindings/input/input.h>
5
6 / {
7 compatible = "zyxel,keenetic-extra-ii", "mediatek,mt7628an-soc";
8 model = "ZyXEL Keenetic Extra II";
9
10 aliases {
11 led-boot = &led_power;
12 led-failsafe = &led_power;
13 led-running = &led_power;
14 led-upgrade = &led_power;
15 };
16
17 chosen {
18 bootargs = "console=ttyS0,57600n8";
19 };
20
21 keys {
22 compatible = "gpio-keys";
23
24 reset {
25 label = "reset";
26 gpios = <&gpio 2 GPIO_ACTIVE_LOW>;
27 linux,code = <KEY_RESTART>;
28 };
29
30 wps {
31 label = "wps";
32 gpios = <&gpio 46 GPIO_ACTIVE_LOW>;
33 linux,code = <KEY_WPS_BUTTON>;
34 };
35
36 fn {
37 label = "fn";
38 gpios = <&gpio 45 GPIO_ACTIVE_LOW>;
39 linux,code = <BTN_0>;
40 };
41 };
42
43 leds {
44 compatible = "gpio-leds";
45
46 led_power: power {
47 label = "green:power";
48 gpios = <&gpio 11 GPIO_ACTIVE_LOW>;
49 };
50
51 internet {
52 label = "green:internet";
53 gpios = <&gpio 44 GPIO_ACTIVE_LOW>;
54 };
55
56 wifi {
57 label = "green:wifi";
58 gpios = <&gpio 37 GPIO_ACTIVE_LOW>;
59 };
60
61 usb {
62 label = "green:usb";
63 gpios = <&gpio 1 GPIO_ACTIVE_LOW>;
64 trigger-sources = <&ohci_port1>, <&ehci_port1>;
65 linux,default-trigger = "usbport";
66 };
67 };
68
69 gpio_export {
70 compatible = "gpio-export";
71 #size-cells = <0>;
72
73 usbpower {
74 gpio-export,name = "usbpower";
75 gpio-export,output = <1>;
76 gpios = <&gpio 6 GPIO_ACTIVE_HIGH>;
77 };
78 };
79
80 virtual_flash {
81 compatible = "mtd-concat";
82 devices = <&firmware1 &firmware2>;
83
84 partitions {
85 compatible = "fixed-partitions";
86 #address-cells = <1>;
87 #size-cells = <1>;
88
89 partition@0 {
90 compatible = "denx,uimage";
91 label = "firmware";
92 reg = <0x0 0x1d20000>;
93 };
94 };
95 };
96 };
97
98 &spi0 {
99 status = "okay";
100
101 flash@0 {
102 compatible = "jedec,spi-nor";
103 reg = <0>;
104 spi-max-frequency = <32000000>;
105
106 partitions {
107 compatible = "fixed-partitions";
108 #address-cells = <1>;
109 #size-cells = <1>;
110
111 partition@0 {
112 label = "u-boot";
113 reg = <0x0 0x30000>;
114 read-only;
115 };
116
117 partition@30000 {
118 label = "u-config";
119 reg = <0x30000 0x10000>;
120 read-only;
121 };
122
123 factory: partition@40000 {
124 compatible = "nvmem-cells";
125 label = "rf-eeprom";
126 reg = <0x40000 0x10000>;
127 #address-cells = <1>;
128 #size-cells = <1>;
129 read-only;
130
131 eeprom_factory_0: eeprom@0 {
132 reg = <0x0 0x400>;
133 };
134
135 eeprom_factory_8000: eeprom@8000 {
136 reg = <0x8000 0x200>;
137 };
138
139 macaddr_factory_4: macaddr@4 {
140 reg = <0x4 0x6>;
141 };
142 };
143
144 firmware1: partition@50000 {
145 label = "firmware_1";
146 reg = <0x50000 0xe90000>;
147 };
148
149 partition@ee0000 {
150 label = "config_1";
151 reg = <0xee0000 0x10000>;
152 read-only;
153 };
154
155 partition@ef0000 {
156 label = "storage";
157 reg = <0xef0000 0x100000>;
158 read-only;
159 };
160
161 partition@ff0000 {
162 label = "dump";
163 reg = <0xff0000 0x10000>;
164 read-only;
165 };
166
167 partition@1000000 {
168 label = "u-state";
169 reg = <0x1000000 0x30000>;
170 read-only;
171 };
172
173 partition@1030000 {
174 label = "u-config_res";
175 reg = <0x1030000 0x10000>;
176 read-only;
177 };
178
179 partition@1040000 {
180 label = "rf-eeprom_res";
181 reg = <0x1040000 0x10000>;
182 read-only;
183 };
184
185 firmware2: partition@1050000 {
186 label = "firmware_2";
187 reg = <0x1050000 0xe90000>;
188 };
189
190 partition@1ee0000 {
191 label = "config_2";
192 reg = <0x1ee0000 0x10000>;
193 read-only;
194 };
195 };
196 };
197 };
198
199 &ethernet {
200 nvmem-cells = <&macaddr_factory_4>;
201 nvmem-cell-names = "mac-address";
202 };
203
204 &esw {
205 mediatek,portmap = <0x3e>;
206 };
207
208 &wmac {
209 status = "okay";
210
211 nvmem-cells = <&eeprom_factory_0>;
212 nvmem-cell-names = "eeprom";
213 };
214
215 &pcie {
216 status = "okay";
217 };
218
219 &pcie0 {
220 mt76@0,0 {
221 compatible = "mediatek,mt76";
222 reg = <0x0000 0 0 0 0>;
223 nvmem-cells = <&eeprom_factory_8000>;
224 nvmem-cell-names = "eeprom";
225 ieee80211-freq-limit = <5000000 6000000>;
226 };
227 };
228
229 &state_default {
230 gpio {
231 groups = "gpio", "i2s", "refclk", "spi cs1", "uart1", "wled_an";
232 function = "gpio";
233 };
234 };