ramips: remove device tree legacy compatibility
authorNick Hainke <vincent@systemli.org>
Fri, 5 May 2023 04:26:12 +0000 (06:26 +0200)
committerChristian Marangi <ansuelsmth@gmail.com>
Fri, 12 May 2023 11:02:44 +0000 (13:02 +0200)
We switched to 5.15 kernel, so we don't need to maintain 5.10
compatibility anymore.

Signed-off-by: Nick Hainke <vincent@systemli.org>
target/linux/ramips/dts/mt7621.dtsi
target/linux/ramips/image/mt7621.mk

index 0f513f313cfa352787f1819a31414f32a35fa12c..3e076741a91e68c588a318dda033d228b2776f95 100644 (file)
                bootargs = "console=ttyS0,57600";
        };
 
-#ifdef DTS_LEGACY
-       pll: pll {
-               compatible = "mediatek,mt7621-pll", "syscon";
-
-               #clock-cells = <1>;
-               clock-output-names = "cpu", "bus";
-       };
-#endif
-
        sysclock: sysclock {
                #clock-cells = <0>;
                compatible = "fixed-clock";
                #size-cells = <1>;
 
                sysc: syscon@0 {
-#ifdef DTS_LEGACY
-                       compatible = "mtk,mt7621-sysc", "syscon";
-#else
                        compatible = "mediatek,mt7621-sysc", "syscon";
                        #clock-cells = <1>;
                        ralink,memctl = <&memc>;
                        clock-output-names = "xtal", "cpu", "bus",
                                             "50m", "125m", "150m",
                                             "250m", "270m";
-#endif
                        reg = <0x0 0x100>;
                };
 
                };
 
                memc: syscon@5000 {
-#ifdef DTS_LEGACY
-                       compatible = "mtk,mt7621-memc", "syscon";
-#else
                        compatible = "mediatek,mt7621-memc", "syscon";
-#endif
                        reg = <0x5000 0x1000>;
                };
 
                        compatible = "ralink,mt7621-spi";
                        reg = <0xb00 0x100>;
 
-#ifdef DTS_LEGACY
-                       clocks = <&pll MT7621_CLK_BUS>;
-#else
                        clocks = <&sysc MT7621_CLK_BUS>;
-#endif
 
                        resets = <&rstctrl 18>;
                        reset-names = "spi";
                timer {
                        compatible = "mti,gic-timer";
                        interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
-#ifdef DTS_LEGACY
-                       clocks = <&pll MT7621_CLK_CPU>;
-#else
                        clocks = <&sysc MT7621_CLK_CPU>;
-#endif
                };
        };
 
                compatible = "mediatek,mt7621-eth";
                reg = <0x1e100000 0x10000>;
 
-#ifdef DTS_LEGACY
-               clocks = <&sysclock>;
-               clock-names = "ethif";
-#else
                clocks = <&sysc MT7621_CLK_FE>,
                         <&sysc MT7621_CLK_ETH>;
                clock-names = "fe", "ethif";
-#endif
 
                #address-cells = <1>;
                #size-cells = <0>;
 
                device_type = "pci";
 
-#ifdef DTS_LEGACY
-               ranges = <0x02000000 0 0x00000000 0x60000000 0 0x10000000>, /* pci memory */
-                        <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
-#else
                ranges = <0x02000000 0 0x60000000 0x60000000 0 0x10000000>, /* pci memory */
                         <0x01000000 0 0x00000000 0x1e160000 0 0x00010000>; /* io space */
-#endif
 
                status = "disabled";
 
-#ifdef DTS_LEGACY
-               interrupt-parent = <&gic>;
-               interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH
-                               GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH
-                               GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
-
-
-               resets = <&rstctrl 24>, <&rstctrl 25>, <&rstctrl 26>;
-               reset-names = "pcie0", "pcie1", "pcie2";
-               clocks = <&clkctrl 24>, <&clkctrl 25>, <&clkctrl 26>;
-               clock-names = "pcie0", "pcie1", "pcie2";
-               phys = <&pcie0_phy 1>, <&pcie2_phy 0>;
-               phy-names = "pcie-phy0", "pcie-phy2";
-#else
                #interrupt-cells = <1>;
                interrupt-map-mask = <0xF800 0 0 0>;
                interrupt-map = <0x0000 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>,
                                <0x0800 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
                                <0x1000 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
-#endif
 
                reset-gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
 
                        #size-cells = <2>;
                        device_type = "pci";
                        ranges;
-#ifndef DTS_LEGACY
                        #interrupt-cells = <1>;
                        interrupt-map-mask = <0 0 0 0>;
                        interrupt-map = <0 0 0 0 &gic GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&sysc MT7621_CLK_PCIE0>;
                        phys = <&pcie0_phy 1>;
                        phy-names = "pcie-phy0";
-#endif
                };
 
                pcie1: pcie@1,0 {
                        #size-cells = <2>;
                        device_type = "pci";
                        ranges;
-#ifndef DTS_LEGACY
                        #interrupt-cells = <1>;
                        interrupt-map-mask = <0 0 0 0>;
                        interrupt-map = <0 0 0 0 &gic GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&sysc MT7621_CLK_PCIE1>;
                        phys = <&pcie0_phy 1>;
                        phy-names = "pcie-phy1";
-#endif
                };
 
                pcie2: pcie@2,0 {
                        #size-cells = <2>;
                        device_type = "pci";
                        ranges;
-#ifndef DTS_LEGACY
                        #interrupt-cells = <1>;
                        interrupt-map-mask = <0 0 0 0>;
                        interrupt-map = <0 0 0 0 &gic GIC_SHARED 25 IRQ_TYPE_LEVEL_HIGH>;
                        clocks = <&sysc MT7621_CLK_PCIE2>;
                        phys = <&pcie2_phy 0>;
                        phy-names = "pcie-phy2";
-#endif
                };
        };
 
        pcie0_phy: pcie-phy@1e149000 {
                compatible = "mediatek,mt7621-pci-phy";
                reg = <0x1e149000 0x0700>;
-#ifndef DTS_LEGACY
                clocks = <&sysc MT7621_CLK_XTAL>;
-#endif
                #phy-cells = <1>;
        };
 
        pcie2_phy: pcie-phy@1e14a000 {
                compatible = "mediatek,mt7621-pci-phy";
                reg = <0x1e14a000 0x0700>;
-#ifndef DTS_LEGACY
                clocks = <&sysc MT7621_CLK_XTAL>;
-#endif
                #phy-cells = <1>;
        };
 };
index 582d53c4230c63ec135350021054ea05b4b3de3d..fc532966c8c1bfb22f954a8bd093e5f6c02a90df 100644 (file)
@@ -9,10 +9,6 @@ DEFAULT_SOC := mt7621
 
 DEVICE_VARS += ELECOM_HWNAME LINKSYS_HWNAME DLINK_HWID
 
-ifdef CONFIG_LINUX_5_10
-  DTS_CPPFLAGS += -DDTS_LEGACY
-endif
-
 define Build/arcadyan-trx
        echo -ne "hsqs" > $@.hsqs
        $(eval trx_magic=$(word 1,$(1)))