package/boot/uboot-lantiq/patches/0038-MIPS-add-board-support-for-Arcadyan-ARV752DPW22.patch

   1 From 09f411b4d10f10a62f147264121bb853b4649c3e Mon Sep 17 00:00:00 2001
   2 From: Oliver Muth <dr.o.muth@gmx.de>
   3 Date: Sat, 12 Oct 2013 16:49:53 +0200
   4 Subject: MIPS: add board support for Arcadyan ARV752DPW22
   5
   6 Signed-off-by: Oliver Muth <dr.o.muth@gmx.de>
   7 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
   8
   9 diff --git a/board/arcadyan/arv752dpw22/Makefile b/board/arcadyan/arv752dpw22/Makefile
  10 new file mode 100644
  11 index 0000000..3a547c2
  12 --- /dev/null
  13 +++ b/board/arcadyan/arv752dpw22/Makefile
  14 @@ -0,0 +1,27 @@
  15 +#
  16 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
  17 +#
  18 +# SPDX-License-Identifier:     GPL-2.0+
  19 +#
  20 +
  21 +include $(TOPDIR)/config.mk
  22 +
  23 +LIB    = $(obj)lib$(BOARD).o
  24 +
  25 +COBJS  = $(BOARD).o
  26 +
  27 +SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  28 +OBJS   := $(addprefix $(obj),$(COBJS))
  29 +SOBJS  := $(addprefix $(obj),$(SOBJS))
  30 +
  31 +$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
  32 +       $(call cmd_link_o_target, $(OBJS) $(SOBJS))
  33 +
  34 +#########################################################################
  35 +
  36 +# defines $(obj).depend target
  37 +include $(SRCTREE)/rules.mk
  38 +
  39 +sinclude $(obj).depend
  40 +
  41 +#########################################################################
  42 diff --git a/board/arcadyan/arv752dpw22/arv752dpw22.c b/board/arcadyan/arv752dpw22/arv752dpw22.c
  43 new file mode 100644
  44 index 0000000..9b2d89f
  45 --- /dev/null
  46 +++ b/board/arcadyan/arv752dpw22/arv752dpw22.c
  47 @@ -0,0 +1,52 @@
  48 +/*
  49 + * Copyright (C) 2012 Luka Perkov <luka@openwrt.org>
  50 + * Copyright (C) 2013 Oliver Muth <dr.o.muth@gmx.de>
  51 + *
  52 + * SPDX-License-Identifier:    GPL-2.0+
  53 + */
  54 +
  55 +#include <common.h>
  56 +#include <switch.h>
  57 +#include <asm/gpio.h>
  58 +#include <asm/lantiq/eth.h>
  59 +#include <asm/lantiq/reset.h>
  60 +#include <asm/lantiq/chipid.h>
  61 +
  62 +int board_early_init_f(void)
  63 +{
  64 +       return 0;
  65 +}
  66 +
  67 +int checkboard(void)
  68 +{
  69 +       puts("Board: " CONFIG_BOARD_NAME "\n");
  70 +       ltq_chip_print_info();
  71 +
  72 +       return 0;
  73 +}
  74 +
  75 +static const struct ltq_eth_port_config eth_port_config[] = {
  76 +       /* MAC0: Atheros ar8216 switch */
  77 +       { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_MII },
  78 +};
  79 +
  80 +static const struct ltq_eth_board_config eth_board_config = {
  81 +       .ports = eth_port_config,
  82 +       .num_ports = ARRAY_SIZE(eth_port_config),
  83 +};
  84 +
  85 +int board_eth_init(bd_t *bis)
  86 +{
  87 +       return ltq_eth_initialize(&eth_board_config);
  88 +}
  89 +
  90 +static struct switch_device ar8216_dev = {
  91 +       .name = "ar8216",
  92 +       .cpu_port = 0,
  93 +       .port_mask = 0xF,
  94 +};
  95 +
  96 +int board_switch_init(void)
  97 +{
  98 +       return switch_device_register(&ar8216_dev);
  99 +}
 100 diff --git a/board/arcadyan/arv752dpw22/config.mk b/board/arcadyan/arv752dpw22/config.mk
 101 new file mode 100644
 102 index 0000000..9d8953b
 103 --- /dev/null
 104 +++ b/board/arcadyan/arv752dpw22/config.mk
 105 @@ -0,0 +1,7 @@
 106 +#
 107 +# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
 108 +#
 109 +# SPDX-License-Identifier:     GPL-2.0+
 110 +#
 111 +
 112 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
 113 diff --git a/board/arcadyan/arv752dpw22/ddr_settings.h b/board/arcadyan/arv752dpw22/ddr_settings.h
 114 new file mode 100644
 115 index 0000000..a226322
 116 --- /dev/null
 117 +++ b/board/arcadyan/arv752dpw22/ddr_settings.h
 118 @@ -0,0 +1,55 @@
 119 +/*
 120 + * Copyright (C) 2011-2013 Luka Perkov <luka@openwrt.org>
 121 + *
 122 + * This file has been generated with lantiq_ram_extract_magic.awk script.
 123 + *
 124 + * SPDX-License-Identifier:    GPL-2.0+
 125 + */
 126 +
 127 +#define MC_DC00_VALUE  0x1B1B
 128 +#define MC_DC01_VALUE  0x0
 129 +#define MC_DC02_VALUE  0x0
 130 +#define MC_DC03_VALUE  0x0
 131 +#define MC_DC04_VALUE  0x0
 132 +#define MC_DC05_VALUE  0x200
 133 +#define MC_DC06_VALUE  0x605
 134 +#define MC_DC07_VALUE  0x303
 135 +#define MC_DC08_VALUE  0x102
 136 +#define MC_DC09_VALUE  0x70A
 137 +#define MC_DC10_VALUE  0x203
 138 +#define MC_DC11_VALUE  0xC02
 139 +#define MC_DC12_VALUE  0x1C8
 140 +#define MC_DC13_VALUE  0x1
 141 +#define MC_DC14_VALUE  0x0
 142 +#define MC_DC15_VALUE  0x134
 143 +#define MC_DC16_VALUE  0xC800
 144 +#define MC_DC17_VALUE  0xD
 145 +#define MC_DC18_VALUE  0x301
 146 +#define MC_DC19_VALUE  0x200
 147 +#define MC_DC20_VALUE  0xA03
 148 +#define MC_DC21_VALUE  0x1400
 149 +#define MC_DC22_VALUE  0x1414
 150 +#define MC_DC23_VALUE  0x0
 151 +#define MC_DC24_VALUE  0x5B
 152 +#define MC_DC25_VALUE  0x0
 153 +#define MC_DC26_VALUE  0x0
 154 +#define MC_DC27_VALUE  0x0
 155 +#define MC_DC28_VALUE  0x510
 156 +#define MC_DC29_VALUE  0x4E20
 157 +#define MC_DC30_VALUE  0x8235
 158 +#define MC_DC31_VALUE  0x0
 159 +#define MC_DC32_VALUE  0x0
 160 +#define MC_DC33_VALUE  0x0
 161 +#define MC_DC34_VALUE  0x0
 162 +#define MC_DC35_VALUE  0x0
 163 +#define MC_DC36_VALUE  0x0
 164 +#define MC_DC37_VALUE  0x0
 165 +#define MC_DC38_VALUE  0x0
 166 +#define MC_DC39_VALUE  0x0
 167 +#define MC_DC40_VALUE  0x0
 168 +#define MC_DC41_VALUE  0x0
 169 +#define MC_DC42_VALUE  0x0
 170 +#define MC_DC43_VALUE  0x0
 171 +#define MC_DC44_VALUE  0x0
 172 +#define MC_DC45_VALUE  0x500
 173 +#define MC_DC46_VALUE  0x0
 174 diff --git a/boards.cfg b/boards.cfg
 175 index 79cba2d..287f974 100644
 176 --- a/boards.cfg
 177 +++ b/boards.cfg
 178 @@ -521,6 +521,9 @@ Active  mips        mips32         danube      arcadyan        arv7518pw
 179  Active  mips        mips32         danube      arcadyan        arv752dpw           arv752dpw_brn                        arv752dpw:SYS_BOOT_BRN                                                                                                            -
 180  Active  mips        mips32         danube      arcadyan        arv752dpw           arv752dpw_nor                        arv752dpw:SYS_BOOT_NOR                                                                                                            -
 181  Active  mips        mips32         danube      arcadyan        arv752dpw           arv752dpw_ram                        arv752dpw:SYS_BOOT_RAM                                                                                                            -
 182 +Active  mips        mips32         danube      arcadyan        arv752dpw22         arv752dpw22_brn                      arv752dpw22:SYS_BOOT_BRN                                                                                                          -
 183 +Active  mips        mips32         danube      arcadyan        arv752dpw22         arv752dpw22_nor                      arv752dpw22:SYS_BOOT_NOR                                                                                                          -
 184 +Active  mips        mips32         danube      arcadyan        arv752dpw22         arv752dpw22_ram                      arv752dpw22:SYS_BOOT_RAM                                                                                                          -
 185  Active  mips        mips32         danube      audiocodes      acmp252             acmp252_nor                          acmp252:SYS_BOOT_NOR                                                                                                              Daniel Golle <daniel.golle@gmail.com>
 186  Active  mips        mips32         danube      audiocodes      acmp252             acmp252_ram                          acmp252:SYS_BOOT_RAM                                                                                                              Daniel Golle <daniel.golle@gmail.com>
 187  Active  mips        mips32         danube      gigaset         sx76x               gigasx76x_nor                        sx76x:SYS_BOOT_NOR                                                                                                                Luka Perkov <luka@openwrt.org>
 188 diff --git a/include/configs/arv752dpw22.h b/include/configs/arv752dpw22.h
 189 new file mode 100644
 190 index 0000000..f17aa70
 191 --- /dev/null
 192 +++ b/include/configs/arv752dpw22.h
 193 @@ -0,0 +1,68 @@
 194 +/*
 195 + * Copyright (C) 2012-2013 Luka Perkov <luka@openwrt.org>
 196 + *
 197 + * SPDX-License-Identifier:    GPL-2.0+
 198 + */
 199 +
 200 +#ifndef __CONFIG_H
 201 +#define __CONFIG_H
 202 +
 203 +#define CONFIG_MACH_TYPE       "ARV752DPW22"
 204 +#define CONFIG_IDENT_STRING    " "CONFIG_MACH_TYPE
 205 +#define CONFIG_BOARD_NAME      "Arcadyan ARV752DPW22"
 206 +
 207 +/* Configure SoC */
 208 +#define CONFIG_LTQ_SUPPORT_UART                /* Enable ASC and UART */
 209 +
 210 +#define CONFIG_LTQ_SUPPORT_ETHERNET    /* Enable ethernet */
 211 +
 212 +#define CONFIG_LTQ_SUPPORT_NOR_FLASH   /* Have a parallel NOR flash */
 213 +
 214 +/* Switch devices */
 215 +#define CONFIG_SWITCH_MULTI
 216 +#define CONFIG_SWITCH_AR8216
 217 +
 218 +/* Environment */
 219 +#if defined(CONFIG_SYS_BOOT_NOR)
 220 +#define CONFIG_ENV_IS_IN_FLASH
 221 +#define CONFIG_ENV_OVERWRITE
 222 +#define CONFIG_ENV_OFFSET              (192 * 1024)
 223 +#define CONFIG_ENV_SECT_SIZE           (64 * 1024)
 224 +#else
 225 +#define CONFIG_ENV_IS_NOWHERE
 226 +#endif
 227 +
 228 +#define CONFIG_ENV_SIZE                        (8 * 1024)
 229 +#define CONFIG_LOADADDR                        CONFIG_SYS_LOAD_ADDR
 230 +
 231 +/* Burnboot loadable image */
 232 +#if defined(CONFIG_SYS_BOOT_BRN)
 233 +#define CONFIG_SYS_TEXT_BASE           0x80002000
 234 +#define CONFIG_SKIP_LOWLEVEL_INIT
 235 +#define CONFIG_SYS_DISABLE_CACHE
 236 +#define CONFIG_ENV_OVERWRITE 1
 237 +#endif
 238 +
 239 +
 240 +/* Console */
 241 +#define CONFIG_LTQ_ADVANCED_CONSOLE
 242 +#define CONFIG_BAUDRATE                        115200
 243 +#define CONFIG_CONSOLE_ASC             1
 244 +#define CONFIG_CONSOLE_DEV             "ttyLTQ1"
 245 +
 246 +/* Pull in default board configs for Lantiq XWAY Danube */
 247 +#include <asm/lantiq/config.h>
 248 +#include <asm/arch/config.h>
 249 +
 250 +/* Pull in default OpenWrt configs for Lantiq SoC */
 251 +#include "openwrt-lantiq-common.h"
 252 +
 253 +#define CONFIG_ENV_UPDATE_UBOOT_NOR            \
 254 +       "update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
 255 +
 256 +#define CONFIG_EXTRA_ENV_SETTINGS      \
 257 +       CONFIG_ENV_LANTIQ_DEFAULTS      \
 258 +       CONFIG_ENV_UPDATE_UBOOT_NOR     \
 259 +       "kernel_addr=0xB0040000\0"
 260 +
 261 +#endif /* __CONFIG_H */
 262 --
 263 1.8.3.2
 264