package/boot/uboot-lantiq/patches/0039-MIPS-add-board-support-for-Arcadyan-ARV7510.patch

   1 From ba27086a5174130d138d645c2f4a49b08c3f2386 Mon Sep 17 00:00:00 2001
   2 From: Matti Laakso <malaakso@elisanet.fi>
   3 Date: Sat, 2 Mar 2013 23:34:00 +0100
   4 Subject: MIPS: add board support for Arcadyan ARV7510
   5
   6 Signed-off-by: Matti Laakso <malaakso@elisanet.fi>
   7 Signed-off-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
   8
   9 diff --git a/board/arcadyan/arv7510pw/Makefile b/board/arcadyan/arv7510pw/Makefile
  10 new file mode 100644
  11 index 0000000..3a547c2
  12 --- /dev/null
  13 +++ b/board/arcadyan/arv7510pw/Makefile
  14 @@ -0,0 +1,27 @@
  15 +#
  16 +# Copyright (C) 2000-2011 Wolfgang Denk, DENX Software Engineering, wd@denx.de
  17 +#
  18 +# SPDX-License-Identifier:     GPL-2.0+
  19 +#
  20 +
  21 +include $(TOPDIR)/config.mk
  22 +
  23 +LIB    = $(obj)lib$(BOARD).o
  24 +
  25 +COBJS  = $(BOARD).o
  26 +
  27 +SRCS   := $(SOBJS:.o=.S) $(COBJS:.o=.c)
  28 +OBJS   := $(addprefix $(obj),$(COBJS))
  29 +SOBJS  := $(addprefix $(obj),$(SOBJS))
  30 +
  31 +$(LIB):        $(obj).depend $(OBJS) $(SOBJS)
  32 +       $(call cmd_link_o_target, $(OBJS) $(SOBJS))
  33 +
  34 +#########################################################################
  35 +
  36 +# defines $(obj).depend target
  37 +include $(SRCTREE)/rules.mk
  38 +
  39 +sinclude $(obj).depend
  40 +
  41 +#########################################################################
  42 diff --git a/board/arcadyan/arv7510pw/arv7510pw.c b/board/arcadyan/arv7510pw/arv7510pw.c
  43 new file mode 100644
  44 index 0000000..6880b4c
  45 --- /dev/null
  46 +++ b/board/arcadyan/arv7510pw/arv7510pw.c
  47 @@ -0,0 +1,72 @@
  48 +/*
  49 + * Copyright (C) 2013 Matti Laakso <malaakso@elisanet.fi>
  50 + *
  51 + * SPDX-License-Identifier:    GPL-2.0+
  52 + */
  53 +
  54 +#include <common.h>
  55 +#include <switch.h>
  56 +#include <asm/gpio.h>
  57 +#include <asm/lantiq/eth.h>
  58 +#include <asm/lantiq/reset.h>
  59 +#include <asm/lantiq/chipid.h>
  60 +#include <asm/lantiq/cpu.h>
  61 +
  62 +static void gpio_init(void)
  63 +{
  64 +       /* Initialize SSIO GPIOs */
  65 +       gpio_set_altfunc(4, 1, 0, 1);
  66 +       gpio_set_altfunc(5, 1, 0, 1);
  67 +       gpio_set_altfunc(6, 1, 0, 1);
  68 +       ltq_gpio_init();
  69 +
  70 +       /* Power led on */
  71 +       gpio_direction_output(76, 1);
  72 +}
  73 +
  74 +int board_early_init_f(void)
  75 +{
  76 +       gpio_init();
  77 +
  78 +       return 0;
  79 +}
  80 +
  81 +int checkboard(void)
  82 +{
  83 +       puts("Board: " CONFIG_BOARD_NAME "\n");
  84 +       ltq_chip_print_info();
  85 +
  86 +       return 0;
  87 +}
  88 +
  89 +static const struct ltq_eth_port_config eth_port_config[] = {
  90 +       /* MAC0: ADM6996I */
  91 +       { 0, 0x0, LTQ_ETH_PORT_SWITCH, PHY_INTERFACE_MODE_RMII },
  92 +};
  93 +
  94 +static const struct ltq_eth_board_config eth_board_config = {
  95 +       .ports = eth_port_config,
  96 +       .num_ports = ARRAY_SIZE(eth_port_config),
  97 +};
  98 +
  99 +int board_eth_init(bd_t *bis)
 100 +{
 101 +       return ltq_eth_initialize(&eth_board_config);
 102 +}
 103 +
 104 +static struct switch_device adm6996i_dev = {
 105 +       .name = "adm6996i",
 106 +       .cpu_port = 5,
 107 +       .port_mask = 0xF,
 108 +};
 109 +
 110 +int board_switch_init(void)
 111 +{
 112 +       /* Deactivate HRST line to release reset of ADM6996I switch */
 113 +       ltq_reset_once(LTQ_RESET_HARD, 200000);
 114 +
 115 +       /* ADM6996I needs some time to come out of reset */
 116 +       __udelay(50000);
 117 +
 118 +       return switch_device_register(&adm6996i_dev);
 119 +}
 120 diff --git a/board/arcadyan/arv7510pw/config.mk b/board/arcadyan/arv7510pw/config.mk
 121 new file mode 100644
 122 index 0000000..9d8953b
 123 --- /dev/null
 124 +++ b/board/arcadyan/arv7510pw/config.mk
 125 @@ -0,0 +1,7 @@
 126 +#
 127 +# Copyright (C) 2011-2013 Daniel Schwierzeck, daniel.schwierzeck@gmail.com
 128 +#
 129 +# SPDX-License-Identifier:     GPL-2.0+
 130 +#
 131 +
 132 +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(BOARDDIR)
 133 diff --git a/board/arcadyan/arv7510pw/ddr_settings.h b/board/arcadyan/arv7510pw/ddr_settings.h
 134 new file mode 100644
 135 index 0000000..e63f591
 136 --- /dev/null
 137 +++ b/board/arcadyan/arv7510pw/ddr_settings.h
 138 @@ -0,0 +1,53 @@
 139 +/*
 140 + * Copyright (C) 2013 Matti Laakso <malaakso@elisanet.fi>
 141 + *
 142 + * SPDX-License-Identifier:    GPL-2.0+
 143 + */
 144 +
 145 +#define MC_DC00_VALUE  0x1B1B
 146 +#define MC_DC01_VALUE  0x0
 147 +#define MC_DC02_VALUE  0x0
 148 +#define MC_DC03_VALUE  0x0
 149 +#define MC_DC04_VALUE  0x0
 150 +#define MC_DC05_VALUE  0x200
 151 +#define MC_DC06_VALUE  0x605
 152 +#define MC_DC07_VALUE  0x303
 153 +#define MC_DC08_VALUE  0x102
 154 +#define MC_DC09_VALUE  0x70A
 155 +#define MC_DC10_VALUE  0x203
 156 +#define MC_DC11_VALUE  0xC02
 157 +#define MC_DC12_VALUE  0x1C8
 158 +#define MC_DC13_VALUE  0x1
 159 +#define MC_DC14_VALUE  0x0
 160 +#define MC_DC15_VALUE  0x120
 161 +#define MC_DC16_VALUE  0xC800
 162 +#define MC_DC17_VALUE  0xD
 163 +#define MC_DC18_VALUE  0x301
 164 +#define MC_DC19_VALUE  0x200
 165 +#define MC_DC20_VALUE  0xA04
 166 +#define MC_DC21_VALUE  0x1700
 167 +#define MC_DC22_VALUE  0x1717
 168 +#define MC_DC23_VALUE  0x0
 169 +#define MC_DC24_VALUE  0x52
 170 +#define MC_DC25_VALUE  0x0
 171 +#define MC_DC26_VALUE  0x0
 172 +#define MC_DC27_VALUE  0x0
 173 +#define MC_DC28_VALUE  0x510
 174 +#define MC_DC29_VALUE  0x4E20
 175 +#define MC_DC30_VALUE  0x8235
 176 +#define MC_DC31_VALUE  0x0
 177 +#define MC_DC32_VALUE  0x0
 178 +#define MC_DC33_VALUE  0x0
 179 +#define MC_DC34_VALUE  0x0
 180 +#define MC_DC35_VALUE  0x0
 181 +#define MC_DC36_VALUE  0x0
 182 +#define MC_DC37_VALUE  0x0
 183 +#define MC_DC38_VALUE  0x0
 184 +#define MC_DC39_VALUE  0x0
 185 +#define MC_DC40_VALUE  0x0
 186 +#define MC_DC41_VALUE  0x0
 187 +#define MC_DC42_VALUE  0x0
 188 +#define MC_DC43_VALUE  0x0
 189 +#define MC_DC44_VALUE  0x0
 190 +#define MC_DC45_VALUE  0x500
 191 +#define MC_DC46_VALUE  0x0
 192 diff --git a/boards.cfg b/boards.cfg
 193 index 287f974..29156d4 100644
 194 --- a/boards.cfg
 195 +++ b/boards.cfg
 196 @@ -515,6 +515,9 @@ Active  mips        mips32         au1x00      -               pb1x00
 197  Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_brn                        arv4519pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <luka@openwrt.org>
 198  Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_nor                        arv4519pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <luka@openwrt.org>
 199  Active  mips        mips32         danube      arcadyan        arv4519pw           arv4519pw_ram                        arv4519pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <luka@openwrt.org>
 200 +Active  mips        mips32         danube      arcadyan        arv7510pw           arv7510pw_brn                        arv7510pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <luka@openwrt.org>
 201 +Active  mips        mips32         danube      arcadyan        arv7510pw           arv7510pw_nor                        arv7510pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <luka@openwrt.org>
 202 +Active  mips        mips32         danube      arcadyan        arv7510pw           arv7510pw_ram                        arv7510pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <luka@openwrt.org>
 203  Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_brn                        arv7518pw:SYS_BOOT_BRN                                                                                                            Luka Perkov <luka@openwrt.org>
 204  Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_nor                        arv7518pw:SYS_BOOT_NOR                                                                                                            Luka Perkov <luka@openwrt.org>
 205  Active  mips        mips32         danube      arcadyan        arv7518pw           arv7518pw_ram                        arv7518pw:SYS_BOOT_RAM                                                                                                            Luka Perkov <luka@openwrt.org>
 206 diff --git a/include/configs/arv7510pw.h b/include/configs/arv7510pw.h
 207 new file mode 100644
 208 index 0000000..9eacfa1
 209 --- /dev/null
 210 +++ b/include/configs/arv7510pw.h
 211 @@ -0,0 +1,75 @@
 212 +/*
 213 + * Copyright (C) 2013 Matti Laakso <malaakso@elisanet.fi>
 214 + *
 215 + * SPDX-License-Identifier:    GPL-2.0+
 216 + */
 217 +
 218 +#ifndef __CONFIG_H
 219 +#define __CONFIG_H
 220 +
 221 +#define CONFIG_MACH_TYPE       "ARV7510PW"
 222 +#define CONFIG_IDENT_STRING    " "CONFIG_MACH_TYPE
 223 +#define CONFIG_BOARD_NAME      "Arcadyan ARV7510PW"
 224 +
 225 +/* Configure SoC */
 226 +#define CONFIG_LTQ_SUPPORT_UART                /* Enable ASC and UART */
 227 +#define CONFIG_LTQ_SUPPORT_ETHERNET    /* Enable ethernet */
 228 +#define CONFIG_LTQ_SUPPORT_NOR_FLASH   /* Have a parallel NOR flash */
 229 +
 230 +/* Switch devices */
 231 +#define CONFIG_SWITCH_MULTI
 232 +#define CONFIG_SWITCH_ADM6996I
 233 +
 234 +/* SSIO */
 235 +#define CONFIG_LTQ_SSIO_SHIFT_REGS
 236 +#define CONFIG_LTQ_SSIO_EDGE_FALLING
 237 +#define CONFIG_LTQ_SSIO_GPHY1_MODE     0
 238 +#define CONFIG_LTQ_SSIO_GPHY2_MODE     0
 239 +#define CONFIG_LTQ_SSIO_INIT_VALUE     0
 240 +
 241 +/* Environment */
 242 +#if defined(CONFIG_SYS_BOOT_NOR)
 243 +#define CONFIG_ENV_IS_IN_FLASH
 244 +#define CONFIG_ENV_OVERWRITE
 245 +#define CONFIG_ENV_OFFSET              (256 * 1024)
 246 +#define CONFIG_ENV_SECT_SIZE           (128 * 1024)
 247 +#else
 248 +#define CONFIG_ENV_IS_NOWHERE
 249 +#endif
 250 +
 251 +#define CONFIG_ENV_SIZE                        (8 * 1024)
 252 +#define CONFIG_LOADADDR                        CONFIG_SYS_LOAD_ADDR
 253 +
 254 +/* Brnboot loadable image */
 255 +#if defined(CONFIG_SYS_BOOT_BRN)
 256 +#define CONFIG_SYS_TEXT_BASE           0x80002000
 257 +#define CONFIG_SKIP_LOWLEVEL_INIT
 258 +#define CONFIG_SYS_DISABLE_CACHE
 259 +#define CONFIG_ENV_OVERWRITE 1
 260 +#endif
 261 +
 262 +/* Console */
 263 +#define CONFIG_LTQ_ADVANCED_CONSOLE
 264 +#define CONFIG_BAUDRATE                        115200
 265 +#define CONFIG_CONSOLE_ASC             1
 266 +#define CONFIG_CONSOLE_DEV             "ttyLTQ1"
 267 +
 268 +/* Pull in default board configs for Lantiq XWAY Danube */
 269 +#include <asm/lantiq/config.h>
 270 +#include <asm/arch/config.h>
 271 +
 272 +/* Buffered write broken in ARV7510PW */
 273 +#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 274 +
 275 +/* Pull in default OpenWrt configs for Lantiq SoC */
 276 +#include "openwrt-lantiq-common.h"
 277 +
 278 +#define CONFIG_ENV_UPDATE_UBOOT_NOR            \
 279 +       "update-uboot-nor=run load-uboot-nor write-uboot-nor\0"
 280 +
 281 +#define CONFIG_EXTRA_ENV_SETTINGS              \
 282 +       CONFIG_ENV_LANTIQ_DEFAULTS              \
 283 +       CONFIG_ENV_UPDATE_UBOOT_NOR             \
 284 +       "kernel_addr=0xB0060000\0"
 285 +
 286 +#endif /* __CONFIG_H */
 287 --
 288 1.8.3.2
 289