package/kernel/lantiq/ltq-ptm/src/ifxmips_ptm_ar9.c

   1 /******************************************************************************
   2 **
   3 ** FILE NAME    : ifxmips_ptm_ar9.c
   4 ** PROJECT      : UEIP
   5 ** MODULES      : PTM
   6 **
   7 ** DATE         : 7 Jul 2009
   8 ** AUTHOR       : Xu Liang
   9 ** DESCRIPTION  : PTM driver common source file (core functions)
  10 ** COPYRIGHT    :       Copyright (c) 2006
  11 **                      Infineon Technologies AG
  12 **                      Am Campeon 1-12, 85579 Neubiberg, Germany
  13 **
  14 **    This program is free software; you can redistribute it and/or modify
  15 **    it under the terms of the GNU General Public License as published by
  16 **    the Free Software Foundation; either version 2 of the License, or
  17 **    (at your option) any later version.
  18 **
  19 ** HISTORY
  20 ** $Date        $Author         $Comment
  21 ** 07 JUL 2009  Xu Liang        Init Version
  22 *******************************************************************************/
  23
  24
  25
  26 /*
  27  * ####################################
  28  *              Head File
  29  * ####################################
  30  */
  31
  32 /*
  33  *  Common Head File
  34  */
  35 #include <linux/kernel.h>
  36 #include <linux/module.h>
  37 #include <linux/version.h>
  38 #include <linux/types.h>
  39 #include <linux/errno.h>
  40 #include <linux/proc_fs.h>
  41 #include <linux/init.h>
  42 #include <linux/ioctl.h>
  43 #include <linux/platform_device.h>
  44 #include <linux/reset.h>
  45 #include <asm/delay.h>
  46
  47 /*
  48  *  Chip Specific Head File
  49  */
  50 #include "ifxmips_ptm_adsl.h"
  51 #include "ifxmips_ptm_fw_ar9.h"
  52
  53 #include <lantiq_soc.h>
  54
  55
  56 /*
  57  * ####################################
  58  *              Definition
  59  * ####################################
  60  */
  61
  62 /*
  63  *  EMA Settings
  64  */
  65 #define EMA_CMD_BUF_LEN      0x0040
  66 #define EMA_CMD_BASE_ADDR    (0x00001B80 << 2)
  67 #define EMA_DATA_BUF_LEN     0x0100
  68 #define EMA_DATA_BASE_ADDR   (0x00001C00 << 2)
  69 #define EMA_WRITE_BURST      0x2
  70 #define EMA_READ_BURST       0x2
  71
  72
  73
  74 /*
  75  * ####################################
  76  *             Declaration
  77  * ####################################
  78  */
  79
  80 /*
  81  *  Hardware Init/Uninit Functions
  82  */
  83 static inline void init_pmu(void);
  84 static inline void uninit_pmu(void);
  85 static inline void reset_ppe(struct platform_device *pdev);
  86 static inline void init_ema(void);
  87 static inline void init_mailbox(void);
  88 static inline void init_atm_tc(void);
  89 static inline void clear_share_buffer(void);
  90
  91
  92
  93 /*
  94  * ####################################
  95  *            Local Variable
  96  * ####################################
  97  */
  98
  99
 100
 101 /*
 102  * ####################################
 103  *            Local Function
 104  * ####################################
 105  */
 106
 107 #define IFX_PMU_MODULE_PPE_SLL01  BIT(19)
 108 #define IFX_PMU_MODULE_PPE_TC     BIT(21)
 109 #define IFX_PMU_MODULE_PPE_EMA    BIT(22)
 110 #define IFX_PMU_MODULE_PPE_QSB    BIT(18)
 111 #define IFX_PMU_MODULE_TPE       BIT(13)
 112 #define IFX_PMU_MODULE_DSL_DFE    BIT(9)
 113
 114
 115 static inline void init_pmu(void)
 116 {
 117         ltq_pmu_enable(IFX_PMU_MODULE_PPE_SLL01 |
 118                 IFX_PMU_MODULE_PPE_TC |
 119                 IFX_PMU_MODULE_PPE_EMA |
 120                 IFX_PMU_MODULE_TPE |
 121                 IFX_PMU_MODULE_DSL_DFE);
 122
 123 }
 124
 125 static inline void uninit_pmu(void)
 126 {
 127         ltq_pmu_disable(IFX_PMU_MODULE_PPE_SLL01 |
 128                 IFX_PMU_MODULE_PPE_TC |
 129                 IFX_PMU_MODULE_PPE_EMA |
 130                 IFX_PMU_MODULE_TPE |
 131                 IFX_PMU_MODULE_DSL_DFE);
 132
 133 }
 134
 135 static inline void reset_ppe(struct platform_device *pdev)
 136 {
 137 #ifdef MODULE
 138     //  reset PPE
 139 //    ifx_rcu_rst(IFX_RCU_DOMAIN_PPE, IFX_RCU_MODULE_PTM);
 140 #endif
 141 }
 142
 143 static inline void init_ema(void)
 144 {
 145     //  Configure share buffer master selection
 146     IFX_REG_W32(1, SB_MST_PRI0);
 147     IFX_REG_W32(1, SB_MST_PRI1);
 148
 149     //  EMA Settings
 150     IFX_REG_W32((EMA_CMD_BUF_LEN << 16) | (EMA_CMD_BASE_ADDR >> 2), EMA_CMDCFG);
 151     IFX_REG_W32((EMA_DATA_BUF_LEN << 16) | (EMA_DATA_BASE_ADDR >> 2), EMA_DATACFG);
 152     IFX_REG_W32(0x000000FF, EMA_IER);
 153     IFX_REG_W32(EMA_READ_BURST | (EMA_WRITE_BURST << 2), EMA_CFG);
 154 }
 155
 156 static inline void init_mailbox(void)
 157 {
 158     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU1_ISRC);
 159     IFX_REG_W32(0x00000000, MBOX_IGU1_IER);
 160     IFX_REG_W32(0xFFFFFFFF, MBOX_IGU3_ISRC);
 161     IFX_REG_W32(0x00000000, MBOX_IGU3_IER);
 162 }
 163
 164 static inline void init_atm_tc(void)
 165 {
 166     IFX_REG_W32(0x0,        RFBI_CFG);
 167     IFX_REG_W32(0x1800,     SFSM_DBA0);
 168     IFX_REG_W32(0x1921,     SFSM_DBA1);
 169     IFX_REG_W32(0x1A42,     SFSM_CBA0);
 170     IFX_REG_W32(0x1A53,     SFSM_CBA1);
 171     IFX_REG_W32(0x14011,    SFSM_CFG0);
 172     IFX_REG_W32(0x14011,    SFSM_CFG1);
 173     IFX_REG_W32(0x1000,     FFSM_DBA0);
 174     IFX_REG_W32(0x1700,     FFSM_DBA1);
 175     IFX_REG_W32(0x3000C,    FFSM_CFG0);
 176     IFX_REG_W32(0x3000C,    FFSM_CFG1);
 177     IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC0);
 178     IFX_REG_W32(0xF0D10000, FFSM_IDLE_HEAD_BC1);
 179
 180     /*
 181      *  0. Backup port2 value to temp
 182      *  1. Disable CPU port2 in switch (link and learning)
 183      *  2. wait for a while
 184      *  3. Configure DM register and counter
 185      *  4. restore temp to CPU port2 in switch
 186      *  This code will cause network to stop working if there are heavy
 187      *  traffic during bootup. This part should be moved to switch and use
 188      *  the same code as ATM
 189      */
 190     {
 191         int i;
 192         u32 temp;
 193
 194         temp = IFX_REG_R32(SW_P2_CTL);
 195
 196         IFX_REG_W32(0x40020000, SW_P2_CTL);
 197         for (i = 0; i < 200; i++)
 198             udelay(2000);
 199
 200         IFX_REG_W32(0x00007028, DM_RXCFG);
 201         IFX_REG_W32(0x00007028, DS_RXCFG);
 202
 203         IFX_REG_W32(0x00001100, DM_RXDB);
 204         IFX_REG_W32(0x00001100, DS_RXDB);
 205
 206         IFX_REG_W32(0x00001600, DM_RXCB);
 207         IFX_REG_W32(0x00001600, DS_RXCB);
 208
 209         /*
 210          * For dynamic, must reset these counters,
 211          * For once initialization, don't need to reset these counters
 212          */
 213         IFX_REG_W32(0x0, DM_RXPGCNT);
 214         IFX_REG_W32(0x0, DS_RXPGCNT);
 215         IFX_REG_W32(0x0, DM_RXPKTCNT);
 216
 217         IFX_REG_W32_MASK(0, 0x80000000, DM_RXCFG);
 218         IFX_REG_W32_MASK(0, 0x8000, DS_RXCFG);
 219
 220         udelay(2000);
 221         IFX_REG_W32(temp, SW_P2_CTL);
 222         udelay(2000);
 223     }
 224 }
 225
 226 static inline void clear_share_buffer(void)
 227 {
 228     volatile u32 *p = SB_RAM0_ADDR(0);
 229     unsigned int i;
 230
 231     for ( i = 0; i < SB_RAM0_DWLEN + SB_RAM1_DWLEN + SB_RAM2_DWLEN + SB_RAM3_DWLEN + SB_RAM4_DWLEN; i++ )
 232         IFX_REG_W32(0, p++);
 233 }
 234
 235 /*
 236  *  Description:
 237  *    Download PPE firmware binary code.
 238  *  Input:
 239  *    src       --- u32 *, binary code buffer
 240  *    dword_len --- unsigned int, binary code length in DWORD (32-bit)
 241  *  Output:
 242  *    int       --- 0:    Success
 243  *                  else:           Error Code
 244  */
 245 static inline int pp32_download_code(u32 *code_src, unsigned int code_dword_len, u32 *data_src, unsigned int data_dword_len)
 246 {
 247     volatile u32 *dest;
 248
 249     if ( code_src == 0 || ((unsigned long)code_src & 0x03) != 0
 250         || data_src == 0 || ((unsigned long)data_src & 0x03) != 0 )
 251         return -1;
 252
 253     if ( code_dword_len <= CDM_CODE_MEMORYn_DWLEN(0) )
 254         IFX_REG_W32(0x00, CDM_CFG);
 255     else
 256         IFX_REG_W32(0x04, CDM_CFG);
 257
 258     /*  copy code   */
 259     dest = CDM_CODE_MEMORY(0, 0);
 260     while ( code_dword_len-- > 0 )
 261         IFX_REG_W32(*code_src++, dest++);
 262
 263     /*  copy data   */
 264     dest = CDM_DATA_MEMORY(0, 0);
 265     while ( data_dword_len-- > 0 )
 266         IFX_REG_W32(*data_src++, dest++);
 267
 268     return 0;
 269 }
 270
 271
 272
 273 /*
 274  * ####################################
 275  *           Global Function
 276  * ####################################
 277  */
 278
 279 void ifx_ptm_get_fw_ver(unsigned int *major, unsigned int *minor)
 280 {
 281     ASSERT(major != NULL, "pointer is NULL");
 282     ASSERT(minor != NULL, "pointer is NULL");
 283
 284     *major = FW_VER_ID->major;
 285     *minor = FW_VER_ID->minor;
 286 }
 287
 288 void ifx_ptm_init_chip(struct platform_device *pdev)
 289 {
 290     init_pmu();
 291
 292     reset_ppe(pdev);
 293
 294     init_ema();
 295
 296     init_mailbox();
 297
 298     init_atm_tc();
 299
 300     clear_share_buffer();
 301 }
 302
 303 void ifx_ptm_uninit_chip(void)
 304 {
 305     uninit_pmu();
 306 }
 307
 308 /*
 309  *  Description:
 310  *    Initialize and start up PP32.
 311  *  Input:
 312  *    none
 313  *  Output:
 314  *    int  --- 0: Success
 315  *             else:        Error Code
 316  */
 317 int ifx_pp32_start(int pp32)
 318 {
 319     int ret;
 320
 321     /*  download firmware   */
 322     ret = pp32_download_code(firmware_binary_code, sizeof(firmware_binary_code) / sizeof(*firmware_binary_code), firmware_binary_data, sizeof(firmware_binary_data) / sizeof(*firmware_binary_data));
 323     if ( ret != 0 )
 324         return ret;
 325
 326     /*  run PP32    */
 327     IFX_REG_W32(DBG_CTRL_RESTART, PP32_DBG_CTRL(0));
 328
 329     /*  idle for a while to let PP32 init itself    */
 330     udelay(10);
 331
 332     return 0;
 333 }
 334
 335 /*
 336  *  Description:
 337  *    Halt PP32.
 338  *  Input:
 339  *    none
 340  *  Output:
 341  *    none
 342  */
 343 void ifx_pp32_stop(int pp32)
 344 {
 345     /*  halt PP32   */
 346     IFX_REG_W32(DBG_CTRL_STOP, PP32_DBG_CTRL(0));
 347 }
 348
 349 int ifx_ptm_proc_read_regs(char *page, char **start, off_t off, int count, int *eof, void *data)
 350 {
 351     int len = 0;
 352
 353     len += sprintf(page + off + len, "EMA:\n");
 354     len += sprintf(page + off + len, "  SB_MST_PRI0 - 0x%08X, SB_MST_PRI1 - 0x%08X\n", IFX_REG_R32(SB_MST_PRI0), IFX_REG_R32(SB_MST_PRI1));
 355     len += sprintf(page + off + len, "  EMA_CMDCFG  - 0x%08X, EMA_DATACFG - 0x%08X\n", IFX_REG_R32(EMA_CMDCFG), IFX_REG_R32(EMA_DATACFG));
 356     len += sprintf(page + off + len, "  EMA_IER     - 0x%08X, EMA_CFG     - 0x%08X\n", IFX_REG_R32(EMA_IER), IFX_REG_R32(EMA_CFG));
 357
 358     len += sprintf(page + off + len, "Mailbox:\n");
 359     len += sprintf(page + off + len, "  MBOX_IGU1_IER - 0x%08X, MBOX_IGU1_ISR - 0x%08X\n", IFX_REG_R32(MBOX_IGU1_IER), IFX_REG_R32(MBOX_IGU1_ISR));
 360     len += sprintf(page + off + len, "  MBOX_IGU3_IER - 0x%08X, MBOX_IGU3_ISR - 0x%08X\n", IFX_REG_R32(MBOX_IGU3_IER), IFX_REG_R32(MBOX_IGU3_ISR));
 361
 362     len += sprintf(page + off + len, "TC:\n");
 363     len += sprintf(page + off + len, "  RFBI_CFG  - 0x%08X\n", IFX_REG_R32(RFBI_CFG));
 364     len += sprintf(page + off + len, "  SFSM_DBA0 - 0x%08X, SFSM_CBA0 - 0x%08X, SFSM_CFG0 - 0x%08X\n", IFX_REG_R32(SFSM_DBA0), IFX_REG_R32(SFSM_CBA0), IFX_REG_R32(SFSM_CFG0));
 365     len += sprintf(page + off + len, "  SFSM_DBA1 - 0x%08X, SFSM_CBA1 - 0x%08X, SFSM_CFG1 - 0x%08X\n", IFX_REG_R32(SFSM_DBA1), IFX_REG_R32(SFSM_CBA1), IFX_REG_R32(SFSM_CFG1));
 366     len += sprintf(page + off + len, "  FFSM_DBA0 - 0x%08X, FFSM_CFG0 - 0x%08X, IDLE_HEAD - 0x%08X\n", IFX_REG_R32(FFSM_DBA0), IFX_REG_R32(FFSM_CFG0), IFX_REG_R32(FFSM_IDLE_HEAD_BC0));
 367     len += sprintf(page + off + len, "  FFSM_DBA1 - 0x%08X, FFSM_CFG1 - 0x%08X, IDLE_HEAD - 0x%08X\n", IFX_REG_R32(FFSM_DBA1), IFX_REG_R32(FFSM_CFG1), IFX_REG_R32(FFSM_IDLE_HEAD_BC1));
 368
 369     len += sprintf(page + off + len, "DPlus:\n");
 370     len += sprintf(page + off + len, "  DM_RXDB    - 0x%08X, DM_RXCB     - 0x%08X, DM_RXCFG - 0x%08X\n", IFX_REG_R32(DM_RXDB), IFX_REG_R32(DM_RXCB), IFX_REG_R32(DM_RXCFG));
 371     len += sprintf(page + off + len, "  DM_RXPGCNT - 0x%08X, DM_RXPKTCNT - 0x%08X\n", IFX_REG_R32(DM_RXPGCNT), IFX_REG_R32(DM_RXPKTCNT));
 372     len += sprintf(page + off + len, "  DS_RXDB    - 0x%08X, DS_RXCB     - 0x%08X, DS_RXCFG - 0x%08X\n", IFX_REG_R32(DS_RXDB), IFX_REG_R32(DS_RXCB), IFX_REG_R32(DS_RXCFG));
 373     len += sprintf(page + off + len, "  DS_RXPGCNT - 0x%08X\n", IFX_REG_R32(DS_RXPGCNT));
 374
 375     *eof = 1;
 376
 377     return len;
 378 }