package/kernel/mac80211/patches/rt2x00/015-v6.1-rt2x00-set-SoC-wmac-clock-register.patch

   1 From patchwork Sat Sep 17 20:29:55 2022
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   5 X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
   6 X-Patchwork-Id: 12979256
   7 X-Patchwork-Delegate: kvalo@adurom.com
   8 Return-Path: <linux-wireless-owner@kernel.org>
   9 Date: Sat, 17 Sep 2022 21:29:55 +0100
  10 From: Daniel Golle <daniel@makrotopia.org>
  11 To: linux-wireless@vger.kernel.org, Stanislaw Gruszka <stf_xl@wp.pl>,
  12         Helmut Schaa <helmut.schaa@googlemail.com>
  13 Cc: Kalle Valo <kvalo@kernel.org>,
  14         "David S. Miller" <davem@davemloft.net>,
  15         Eric Dumazet <edumazet@google.com>,
  16         Jakub Kicinski <kuba@kernel.org>,
  17         Paolo Abeni <pabeni@redhat.com>,
  18         Johannes Berg <johannes.berg@intel.com>
  19 Subject: [PATCH v3 15/16] rt2x00: set SoC wmac clock register
  20 Message-ID:
  21  <3e275d259f476f597dab91a9c395015ef3fe3284.1663445157.git.daniel@makrotopia.org>
  22 References: <cover.1663445157.git.daniel@makrotopia.org>
  23 MIME-Version: 1.0
  24 Content-Disposition: inline
  25 In-Reply-To: <cover.1663445157.git.daniel@makrotopia.org>
  26 Precedence: bulk
  27 List-ID: <linux-wireless.vger.kernel.org>
  28 X-Mailing-List: linux-wireless@vger.kernel.org
  29
  30 Instead of using the default value 33 (pci), set US_CYC_CNT init based
  31 on Programming guide:
  32 If available, set chipset bus clock with fallback to cpu clock/3.
  33
  34 Reported-by: Serge Vasilugin <vasilugin@yandex.ru>
  35 Signed-off-by: Daniel Golle <daniel@makrotopia.org>
  36 Acked-by: Stanislaw Gruszka <stf_xl@wp.pl>
  37 ---
  38  .../net/wireless/ralink/rt2x00/rt2800lib.c    | 21 +++++++++++++++++++
  39  1 file changed, 21 insertions(+)
  40
  41 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  42 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  43 @@ -6229,6 +6229,27 @@ static int rt2800_init_registers(struct
  44                 reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
  45                 rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, 125);
  46                 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
  47 +       } else if (rt2x00_is_soc(rt2x00dev)) {
  48 +               struct clk *clk = clk_get_sys("bus", NULL);
  49 +               int rate;
  50 +
  51 +               if (IS_ERR(clk)) {
  52 +                       clk = clk_get_sys("cpu", NULL);
  53 +
  54 +                       if (IS_ERR(clk)) {
  55 +                               rate = 125;
  56 +                       } else {
  57 +                               rate = clk_get_rate(clk) / 3000000;
  58 +                               clk_put(clk);
  59 +                       }
  60 +               } else {
  61 +                       rate = clk_get_rate(clk) / 1000000;
  62 +                       clk_put(clk);
  63 +               }
  64 +
  65 +               reg = rt2800_register_read(rt2x00dev, US_CYC_CNT);
  66 +               rt2x00_set_field32(&reg, US_CYC_CNT_CLOCK_CYCLE, rate);
  67 +               rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
  68         }
  69
  70         reg = rt2800_register_read(rt2x00dev, HT_FBK_CFG0);