package/kernel/mac80211/patches/rt2x00/983-rt2x00-add-r-calibration.patch

   1 From b75efecd6473e6a044d214571c17cad8ae88ed42 Mon Sep 17 00:00:00 2001
   2 From: Daniel Golle <daniel@makrotopia.org>
   3 Date: Mon, 8 Jan 2018 13:42:58 +0100
   4 Subject: [PATCH 05/16] rt2x00: add r calibration for MT7620
   5 MIME-Version: 1.0
   6 Content-Type: text/plain; charset=UTF-8
   7 Content-Transfer-Encoding: 8bit
   8 To: linux-wireless@vger.kernel.org,
   9     Stanislaw Gruszka <stf_xl@wp.pl>,
  10     Helmut Schaa <helmut.schaa@googlemail.com>
  11 Cc: Kalle Valo <kvalo@kernel.org>,
  12     David S. Miller <davem@davemloft.net>,
  13     Eric Dumazet <edumazet@google.com>,
  14     Jakub Kicinski <kuba@kernel.org>,
  15     Paolo Abeni <pabeni@redhat.com>,
  16     Johannes Berg <johannes.berg@intel.com>
  17
  18 From: Tomislav Požega <pozega.tomislav@gmail.com>
  19
  20 Add r calibration code as found in mtk driver.
  21
  22 Signed-off-by: Tomislav Požega <pozega.tomislav@gmail.com>
  23 ---
  24  .../net/wireless/ralink/rt2x00/rt2800lib.c    | 150 ++++++++++++++++++
  25  1 file changed, 150 insertions(+)
  26
  27 --- a/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  28 +++ b/drivers/net/wireless/ralink/rt2x00/rt2800lib.c
  29 @@ -8483,6 +8483,155 @@ static void rt2800_rf_self_txdc_cal(stru
  30         rt2800_register_write(rt2x00dev, RF_BYPASS2, mac052c);
  31  }
  32
  33 +static int rt2800_calcrcalibrationcode(struct rt2x00_dev *rt2x00dev, int d1, int d2)
  34 +{
  35 +       int calcode = ((d2 - d1) * 1000) / 43;
  36 +
  37 +       if ((calcode % 10) >= 5)
  38 +               calcode += 10;
  39 +       calcode = (calcode / 10);
  40 +
  41 +       return calcode;
  42 +}
  43 +
  44 +static void rt2800_r_calibration(struct rt2x00_dev *rt2x00dev)
  45 +{
  46 +       u32 savemacsysctrl;
  47 +       u8 saverfb0r1, saverfb0r34, saverfb0r35;
  48 +       u8 saverfb5r4, saverfb5r17, saverfb5r18;
  49 +       u8 saverfb5r19, saverfb5r20;
  50 +       u8 savebbpr22, savebbpr47, savebbpr49;
  51 +       u8 bytevalue = 0;
  52 +       int rcalcode;
  53 +       u8 r_cal_code = 0;
  54 +       char d1 = 0, d2 = 0;
  55 +       u8 rfvalue;
  56 +       u32 MAC_RF_BYPASS0, MAC_RF_CONTROL0, MAC_PWR_PIN_CFG;
  57 +       u32 maccfg, macstatus;
  58 +       int i;
  59 +
  60 +       saverfb0r1 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 1);
  61 +       saverfb0r34 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 34);
  62 +       saverfb0r35 = rt2800_rfcsr_read_bank(rt2x00dev, 0, 35);
  63 +       saverfb5r4 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 4);
  64 +       saverfb5r17 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 17);
  65 +       saverfb5r18 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 18);
  66 +       saverfb5r19 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 19);
  67 +       saverfb5r20 = rt2800_rfcsr_read_bank(rt2x00dev, 5, 20);
  68 +
  69 +       savebbpr22 = rt2800_bbp_read(rt2x00dev, 22);
  70 +       savebbpr47 = rt2800_bbp_read(rt2x00dev, 47);
  71 +       savebbpr49 = rt2800_bbp_read(rt2x00dev, 49);
  72 +
  73 +       savemacsysctrl = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
  74 +       MAC_RF_BYPASS0 = rt2800_register_read(rt2x00dev, RF_BYPASS0);
  75 +       MAC_RF_CONTROL0 = rt2800_register_read(rt2x00dev, RF_CONTROL0);
  76 +       MAC_PWR_PIN_CFG = rt2800_register_read(rt2x00dev, PWR_PIN_CFG);
  77 +
  78 +       maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
  79 +       maccfg &= (~0x04);
  80 +       rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);
  81 +
  82 +       for (i = 0; i < 10000; i++) {
  83 +               macstatus = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
  84 +               if (macstatus & 0x1)
  85 +                       usleep_range(50, 100);
  86 +               else
  87 +                       break;
  88 +       }
  89 +
  90 +       if (i == 10000)
  91 +               rt2x00_warn(rt2x00dev, "Wait MAC Tx Status to MAX !!!\n");
  92 +
  93 +       maccfg = rt2800_register_read(rt2x00dev, MAC_SYS_CTRL);
  94 +       maccfg &= (~0x04);
  95 +       rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, maccfg);
  96 +
  97 +       for (i = 0; i < 10000; i++) {
  98 +               macstatus = rt2800_register_read(rt2x00dev, MAC_STATUS_CFG);
  99 +               if (macstatus & 0x2)
 100 +                       usleep_range(50, 100);
 101 +               else
 102 +                       break;
 103 +               }
 104 +
 105 +       if (i == 10000)
 106 +               rt2x00_warn(rt2x00dev, "Wait MAC Rx Status to MAX !!!\n");
 107 +
 108 +       rfvalue = (MAC_RF_BYPASS0 | 0x3004);
 109 +       rt2800_register_write(rt2x00dev, RF_BYPASS0, rfvalue);
 110 +       rfvalue = (MAC_RF_CONTROL0 | (~0x3002));
 111 +       rt2800_register_write(rt2x00dev, RF_CONTROL0, rfvalue);
 112 +
 113 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, 0x27);
 114 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, 0x80);
 115 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, 0x83);
 116 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, 0x00);
 117 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, 0x20);
 118 +
 119 +       rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, 0x00);
 120 +       rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, 0x13);
 121 +       rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x00);
 122 +
 123 +       rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x1);
 124 +
 125 +       rt2800_bbp_write(rt2x00dev, 47, 0x04);
 126 +       rt2800_bbp_write(rt2x00dev, 22, 0x80);
 127 +       usleep_range(100, 200);
 128 +       bytevalue = rt2800_bbp_read(rt2x00dev, 49);
 129 +       if (bytevalue > 128)
 130 +               d1 = bytevalue - 256;
 131 +       else
 132 +               d1 = (char)bytevalue;
 133 +       rt2800_bbp_write(rt2x00dev, 22, 0x0);
 134 +       rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, 0x01);
 135 +
 136 +       rt2800_bbp_write(rt2x00dev, 22, 0x80);
 137 +       usleep_range(100, 200);
 138 +       bytevalue = rt2800_bbp_read(rt2x00dev, 49);
 139 +       if (bytevalue > 128)
 140 +               d2 = bytevalue - 256;
 141 +       else
 142 +               d2 = (char)bytevalue;
 143 +       rt2800_bbp_write(rt2x00dev, 22, 0x0);
 144 +
 145 +       rcalcode = rt2800_calcrcalibrationcode(rt2x00dev, d1, d2);
 146 +       if (rcalcode < 0)
 147 +               r_cal_code = 256 + rcalcode;
 148 +       else
 149 +               r_cal_code = (u8)rcalcode;
 150 +
 151 +       rt2800_rfcsr_write_bank(rt2x00dev, 0, 7, r_cal_code);
 152 +
 153 +       rt2800_bbp_write(rt2x00dev, 22, 0x0);
 154 +
 155 +       bytevalue = rt2800_bbp_read(rt2x00dev, 21);
 156 +       bytevalue |= 0x1;
 157 +       rt2800_bbp_write(rt2x00dev, 21, bytevalue);
 158 +       bytevalue = rt2800_bbp_read(rt2x00dev, 21);
 159 +       bytevalue &= (~0x1);
 160 +       rt2800_bbp_write(rt2x00dev, 21, bytevalue);
 161 +
 162 +       rt2800_rfcsr_write_bank(rt2x00dev, 0, 1, saverfb0r1);
 163 +       rt2800_rfcsr_write_bank(rt2x00dev, 0, 34, saverfb0r34);
 164 +       rt2800_rfcsr_write_bank(rt2x00dev, 0, 35, saverfb0r35);
 165 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 4, saverfb5r4);
 166 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 17, saverfb5r17);
 167 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 18, saverfb5r18);
 168 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 19, saverfb5r19);
 169 +       rt2800_rfcsr_write_bank(rt2x00dev, 5, 20, saverfb5r20);
 170 +
 171 +       rt2800_bbp_write(rt2x00dev, 22, savebbpr22);
 172 +       rt2800_bbp_write(rt2x00dev, 47, savebbpr47);
 173 +       rt2800_bbp_write(rt2x00dev, 49, savebbpr49);
 174 +
 175 +       rt2800_register_write(rt2x00dev, RF_BYPASS0, MAC_RF_BYPASS0);
 176 +       rt2800_register_write(rt2x00dev, RF_CONTROL0, MAC_RF_CONTROL0);
 177 +
 178 +       rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, savemacsysctrl);
 179 +       rt2800_register_write(rt2x00dev, PWR_PIN_CFG, MAC_PWR_PIN_CFG);
 180 +}
 181 +
 182  static void rt2800_bbp_core_soft_reset(struct rt2x00_dev *rt2x00dev,
 183                                        bool set_bw, bool is_ht40)
 184  {
 185 @@ -9090,6 +9239,7 @@ static void rt2800_init_rfcsr_6352(struc
 186         rt2800_rfcsr_write_dccal(rt2x00dev, 5, 0x00);
 187         rt2800_rfcsr_write_dccal(rt2x00dev, 17, 0x7C);
 188
 189 +       rt2800_r_calibration(rt2x00dev);
 190         rt2800_rf_self_txdc_cal(rt2x00dev);
 191         rt2800_bw_filter_calibration(rt2x00dev, true);
 192         rt2800_bw_filter_calibration(rt2x00dev, false);