target/linux/ar71xx/files/drivers/mtd/nand/rb91x_nand.c

   1 /*
   2  *  NAND flash driver for the MikroTik RouterBOARD 91x series
   3  *
   4  *  Copyright (C) 2013-2014 Gabor Juhos <juhosg@openwrt.org>
   5  *
   6  *  This program is free software; you can redistribute it and/or modify it
   7  *  under the terms of the GNU General Public License version 2 as published
   8  *  by the Free Software Foundation.
   9  */
  10
  11 #include <linux/version.h>
  12 #include <linux/kernel.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/module.h>
  15 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,14,0)
  16 #include <linux/mtd/nand.h>
  17 #else
  18 #include <linux/mtd/rawnand.h>
  19 #endif#include <linux/mtd/mtd.h>
  20 #include <linux/mtd/partitions.h>
  21 #include <linux/platform_device.h>
  22 #include <linux/io.h>
  23 #include <linux/slab.h>
  24 #include <linux/gpio.h>
  25 #include <linux/platform_data/rb91x_nand.h>
  26
  27 #include <asm/mach-ath79/ar71xx_regs.h>
  28 #include <asm/mach-ath79/ath79.h>
  29
  30 #define DRV_DESC        "NAND flash driver for the RouterBOARD 91x series"
  31
  32 #define RB91X_NAND_NRWE         BIT(12)
  33
  34 #define RB91X_NAND_DATA_BITS    (BIT(0) | BIT(1) | BIT(2) | BIT(3) | BIT(4) |\
  35                                  BIT(13) | BIT(14) | BIT(15))
  36
  37 #define RB91X_NAND_INPUT_BITS   (RB91X_NAND_DATA_BITS | RB91X_NAND_RDY)
  38 #define RB91X_NAND_OUTPUT_BITS  (RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE)
  39
  40 #define RB91X_NAND_LOW_DATA_MASK        0x1f
  41 #define RB91X_NAND_HIGH_DATA_MASK       0xe0
  42 #define RB91X_NAND_HIGH_DATA_SHIFT      8
  43
  44 struct rb91x_nand_info {
  45         struct nand_chip chip;
  46 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
  47         struct mtd_info mtd;
  48 #endif
  49         struct device *dev;
  50
  51         int gpio_nce;
  52         int gpio_ale;
  53         int gpio_cle;
  54         int gpio_rdy;
  55         int gpio_read;
  56         int gpio_nrw;
  57         int gpio_nle;
  58 };
  59
  60 static inline struct rb91x_nand_info *mtd_to_rbinfo(struct mtd_info *mtd)
  61 {
  62 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
  63         return container_of(mtd, struct rb91x_nand_info, mtd);
  64 #else
  65         struct nand_chip *chip = mtd_to_nand(mtd);
  66
  67         return container_of(chip, struct rb91x_nand_info, chip);
  68 #endif
  69 }
  70
  71 static struct mtd_info *rbinfo_to_mtd(struct rb91x_nand_info *nfc)
  72 {
  73 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
  74         return &nfc->mtd;
  75 #else
  76         return nand_to_mtd(&nfc->chip);
  77 #endif
  78 }
  79
  80
  81 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
  82 /*
  83  * We need to use the OLD Yaffs-1 OOB layout, otherwise the RB bootloader
  84  * will not be able to find the kernel that we load.
  85  */
  86 static struct nand_ecclayout rb91x_nand_ecclayout = {
  87         .eccbytes       = 6,
  88         .eccpos         = { 8, 9, 10, 13, 14, 15 },
  89         .oobavail       = 9,
  90         .oobfree        = { { 0, 4 }, { 6, 2 }, { 11, 2 }, { 4, 1 } }
  91 };
  92
  93 #else
  94
  95 static int rb91x_ooblayout_ecc(struct mtd_info *mtd, int section,
  96                                struct mtd_oob_region *oobregion)
  97 {
  98         switch (section) {
  99         case 0:
 100                 oobregion->offset = 8;
 101                 oobregion->length = 3;
 102                 return 0;
 103         case 1:
 104                 oobregion->offset = 13;
 105                 oobregion->length = 3;
 106                 return 0;
 107         default:
 108                 return -ERANGE;
 109         }
 110 }
 111
 112 static int rb91x_ooblayout_free(struct mtd_info *mtd, int section,
 113                                 struct mtd_oob_region *oobregion)
 114 {
 115         switch (section) {
 116         case 0:
 117                 oobregion->offset = 0;
 118                 oobregion->length = 4;
 119                 return 0;
 120         case 1:
 121                 oobregion->offset = 4;
 122                 oobregion->length = 1;
 123                 return 0;
 124         case 2:
 125                 oobregion->offset = 6;
 126                 oobregion->length = 2;
 127                 return 0;
 128         case 3:
 129                 oobregion->offset = 11;
 130                 oobregion->length = 2;
 131                 return 0;
 132         default:
 133                 return -ERANGE;
 134         }
 135 }
 136
 137 static const struct mtd_ooblayout_ops rb91x_nand_ecclayout_ops = {
 138         .ecc = rb91x_ooblayout_ecc,
 139         .free = rb91x_ooblayout_free,
 140 };
 141 #endif /* < 4.6 */
 142
 143 static struct mtd_partition rb91x_nand_partitions[] = {
 144         {
 145                 .name   = "booter",
 146                 .offset = 0,
 147                 .size   = (256 * 1024),
 148                 .mask_flags = MTD_WRITEABLE,
 149         }, {
 150                 .name   = "kernel",
 151                 .offset = (256 * 1024),
 152                 .size   = (4 * 1024 * 1024) - (256 * 1024),
 153         }, {
 154                 .name   = "ubi",
 155                 .offset = MTDPART_OFS_NXTBLK,
 156                 .size   = MTDPART_SIZ_FULL,
 157         },
 158 };
 159
 160 static void rb91x_nand_write(struct rb91x_nand_info *rbni,
 161                              const u8 *buf,
 162                              unsigned len)
 163 {
 164         void __iomem *base = ath79_gpio_base;
 165         u32 oe_reg;
 166         u32 out_reg;
 167         u32 out;
 168         unsigned i;
 169
 170         /* enable the latch */
 171         gpio_set_value_cansleep(rbni->gpio_nle, 0);
 172
 173         oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
 174         out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
 175
 176         /* set data lines to output mode */
 177         __raw_writel(oe_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE),
 178                      base + AR71XX_GPIO_REG_OE);
 179
 180         out = out_reg & ~(RB91X_NAND_DATA_BITS | RB91X_NAND_NRWE);
 181         for (i = 0; i != len; i++) {
 182                 u32 data;
 183
 184                 data = (buf[i] & RB91X_NAND_HIGH_DATA_MASK) <<
 185                         RB91X_NAND_HIGH_DATA_SHIFT;
 186                 data |= buf[i] & RB91X_NAND_LOW_DATA_MASK;
 187                 data |= out;
 188                 __raw_writel(data, base + AR71XX_GPIO_REG_OUT);
 189
 190                 /* deactivate WE line */
 191                 data |= RB91X_NAND_NRWE;
 192                 __raw_writel(data, base + AR71XX_GPIO_REG_OUT);
 193                 /* flush write */
 194                 __raw_readl(base + AR71XX_GPIO_REG_OUT);
 195         }
 196
 197         /* restore  registers */
 198         __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
 199         __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
 200         /* flush write */
 201         __raw_readl(base + AR71XX_GPIO_REG_OUT);
 202
 203         /* disable the latch */
 204         gpio_set_value_cansleep(rbni->gpio_nle, 1);
 205 }
 206
 207 static void rb91x_nand_read(struct rb91x_nand_info *rbni,
 208                             u8 *read_buf,
 209                             unsigned len)
 210 {
 211         void __iomem *base = ath79_gpio_base;
 212         u32 oe_reg;
 213         u32 out_reg;
 214         unsigned i;
 215
 216         /* enable read mode */
 217         gpio_set_value_cansleep(rbni->gpio_read, 1);
 218
 219         /* enable latch */
 220         gpio_set_value_cansleep(rbni->gpio_nle, 0);
 221
 222         /* save registers */
 223         oe_reg = __raw_readl(base + AR71XX_GPIO_REG_OE);
 224         out_reg = __raw_readl(base + AR71XX_GPIO_REG_OUT);
 225
 226         /* set data lines to input mode */
 227         __raw_writel(oe_reg | RB91X_NAND_DATA_BITS,
 228                      base + AR71XX_GPIO_REG_OE);
 229
 230         for (i = 0; i < len; i++) {
 231                 u32 in;
 232                 u8 data;
 233
 234                 /* activate RE line */
 235                 __raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_CLEAR);
 236                 /* flush write */
 237                 __raw_readl(base + AR71XX_GPIO_REG_CLEAR);
 238
 239                 /* read input lines */
 240                 in = __raw_readl(base + AR71XX_GPIO_REG_IN);
 241
 242                 /* deactivate RE line */
 243                 __raw_writel(RB91X_NAND_NRWE, base + AR71XX_GPIO_REG_SET);
 244
 245                 data = (in & RB91X_NAND_LOW_DATA_MASK);
 246                 data |= (in >> RB91X_NAND_HIGH_DATA_SHIFT) &
 247                         RB91X_NAND_HIGH_DATA_MASK;
 248
 249                 read_buf[i] = data;
 250         }
 251
 252         /* restore  registers */
 253         __raw_writel(out_reg, base + AR71XX_GPIO_REG_OUT);
 254         __raw_writel(oe_reg, base + AR71XX_GPIO_REG_OE);
 255         /* flush write */
 256         __raw_readl(base + AR71XX_GPIO_REG_OUT);
 257
 258         /* disable latch */
 259         gpio_set_value_cansleep(rbni->gpio_nle, 1);
 260
 261         /* disable read mode */
 262         gpio_set_value_cansleep(rbni->gpio_read, 0);
 263 }
 264
 265 static int rb91x_nand_dev_ready(struct mtd_info *mtd)
 266 {
 267         struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
 268
 269         return gpio_get_value_cansleep(rbni->gpio_rdy);
 270 }
 271
 272 static void rb91x_nand_cmd_ctrl(struct mtd_info *mtd, int cmd,
 273                                 unsigned int ctrl)
 274 {
 275         struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
 276
 277         if (ctrl & NAND_CTRL_CHANGE) {
 278                 gpio_set_value_cansleep(rbni->gpio_cle,
 279                                         (ctrl & NAND_CLE) ? 1 : 0);
 280                 gpio_set_value_cansleep(rbni->gpio_ale,
 281                                         (ctrl & NAND_ALE) ? 1 : 0);
 282                 gpio_set_value_cansleep(rbni->gpio_nce,
 283                                         (ctrl & NAND_NCE) ? 0 : 1);
 284         }
 285
 286         if (cmd != NAND_CMD_NONE) {
 287                 u8 t = cmd;
 288
 289                 rb91x_nand_write(rbni, &t, 1);
 290         }
 291 }
 292
 293 static u8 rb91x_nand_read_byte(struct mtd_info *mtd)
 294 {
 295         struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
 296         u8 data = 0xff;
 297
 298         rb91x_nand_read(rbni, &data, 1);
 299
 300         return data;
 301 }
 302
 303 static void rb91x_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
 304 {
 305         struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
 306
 307         rb91x_nand_read(rbni, buf, len);
 308 }
 309
 310 static void rb91x_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
 311 {
 312         struct rb91x_nand_info *rbni = mtd_to_rbinfo(mtd);
 313
 314         rb91x_nand_write(rbni, buf, len);
 315 }
 316
 317 static int rb91x_nand_gpio_init(struct rb91x_nand_info *info)
 318 {
 319         int ret;
 320
 321         /*
 322          * Ensure that the LATCH is disabled before initializing
 323          * control lines.
 324          */
 325         ret = devm_gpio_request_one(info->dev, info->gpio_nle,
 326                                     GPIOF_OUT_INIT_HIGH, "LATCH enable");
 327         if (ret)
 328                 return ret;
 329
 330         ret = devm_gpio_request_one(info->dev, info->gpio_nce,
 331                                     GPIOF_OUT_INIT_HIGH, "NAND nCE");
 332         if (ret)
 333                 return ret;
 334
 335         ret = devm_gpio_request_one(info->dev, info->gpio_nrw,
 336                                     GPIOF_OUT_INIT_HIGH, "NAND nRW");
 337         if (ret)
 338                 return ret;
 339
 340         ret = devm_gpio_request_one(info->dev, info->gpio_cle,
 341                                     GPIOF_OUT_INIT_LOW, "NAND CLE");
 342         if (ret)
 343                 return ret;
 344
 345         ret = devm_gpio_request_one(info->dev, info->gpio_ale,
 346                                     GPIOF_OUT_INIT_LOW, "NAND ALE");
 347         if (ret)
 348                 return ret;
 349
 350         ret = devm_gpio_request_one(info->dev, info->gpio_read,
 351                                     GPIOF_OUT_INIT_LOW, "NAND READ");
 352         if (ret)
 353                 return ret;
 354
 355         ret = devm_gpio_request_one(info->dev, info->gpio_rdy,
 356                                     GPIOF_IN, "NAND RDY");
 357         return ret;
 358 }
 359
 360 static int rb91x_nand_probe(struct platform_device *pdev)
 361 {
 362         struct rb91x_nand_info  *rbni;
 363         struct rb91x_nand_platform_data *pdata;
 364         struct mtd_info *mtd;
 365         int ret;
 366
 367         pr_info(DRV_DESC "\n");
 368
 369         pdata = dev_get_platdata(&pdev->dev);
 370         if (!pdata)
 371                 return -EINVAL;
 372
 373         rbni = devm_kzalloc(&pdev->dev, sizeof(*rbni), GFP_KERNEL);
 374         if (!rbni)
 375                 return -ENOMEM;
 376
 377         rbni->dev = &pdev->dev;
 378         rbni->gpio_nce = pdata->gpio_nce;
 379         rbni->gpio_ale = pdata->gpio_ale;
 380         rbni->gpio_cle = pdata->gpio_cle;
 381         rbni->gpio_read = pdata->gpio_read;
 382         rbni->gpio_nrw = pdata->gpio_nrw;
 383         rbni->gpio_rdy = pdata->gpio_rdy;
 384         rbni->gpio_nle = pdata->gpio_nle;
 385
 386         rbni->chip.priv = &rbni;
 387         mtd = rbinfo_to_mtd(rbni);
 388
 389 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 390         mtd->priv       = &rbni->chip;
 391 #endif
 392         mtd->owner      = THIS_MODULE;
 393
 394         rbni->chip.cmd_ctrl     = rb91x_nand_cmd_ctrl;
 395         rbni->chip.dev_ready    = rb91x_nand_dev_ready;
 396         rbni->chip.read_byte    = rb91x_nand_read_byte;
 397         rbni->chip.write_buf    = rb91x_nand_write_buf;
 398         rbni->chip.read_buf     = rb91x_nand_read_buf;
 399
 400         rbni->chip.chip_delay   = 25;
 401         rbni->chip.ecc.mode     = NAND_ECC_SOFT;
 402 #if LINUX_VERSION_CODE >= KERNEL_VERSION(4,6,0)
 403         rbni->chip.ecc.algo = NAND_ECC_HAMMING;
 404 #endif
 405         rbni->chip.options = NAND_NO_SUBPAGE_WRITE;
 406
 407         platform_set_drvdata(pdev, rbni);
 408
 409         ret = rb91x_nand_gpio_init(rbni);
 410         if (ret)
 411                 return ret;
 412
 413         ret = nand_scan_ident(mtd, 1, NULL);
 414         if (ret)
 415                 return ret;
 416
 417         if (mtd->writesize == 512)
 418 #if LINUX_VERSION_CODE < KERNEL_VERSION(4,6,0)
 419                 rbni->chip.ecc.layout = &rb91x_nand_ecclayout;
 420 #else
 421                 mtd_set_ooblayout(mtd, &rb91x_nand_ecclayout_ops);
 422 #endif
 423
 424         ret = nand_scan_tail(mtd);
 425         if (ret)
 426                 return ret;
 427
 428         ret = mtd_device_register(mtd, rb91x_nand_partitions,
 429                                  ARRAY_SIZE(rb91x_nand_partitions));
 430         if (ret)
 431                 goto err_release_nand;
 432
 433         return 0;
 434
 435 err_release_nand:
 436         nand_release(mtd);
 437         return ret;
 438 }
 439
 440 static int rb91x_nand_remove(struct platform_device *pdev)
 441 {
 442         struct rb91x_nand_info *info = platform_get_drvdata(pdev);
 443
 444         nand_release(rbinfo_to_mtd(info));
 445
 446         return 0;
 447 }
 448
 449 static struct platform_driver rb91x_nand_driver = {
 450         .probe  = rb91x_nand_probe,
 451         .remove = rb91x_nand_remove,
 452         .driver = {
 453                 .name   = RB91X_NAND_DRIVER_NAME,
 454                 .owner  = THIS_MODULE,
 455         },
 456 };
 457
 458 module_platform_driver(rb91x_nand_driver);
 459
 460 MODULE_DESCRIPTION(DRV_DESC);
 461 MODULE_VERSION(DRV_VERSION);
 462 MODULE_AUTHOR("Gabor Juhos <juhosg@openwrt.org>");
 463 MODULE_LICENSE("GPL v2");