target/linux/at91/patches-5.10/109-clk-at91-sama7g5-do-not-allow-cpu-pll-to-go-higher-t.patch

   1 From 943ed75a2a5ab08582d3bc8025e8111903698763 Mon Sep 17 00:00:00 2001
   2 From: Claudiu Beznea <claudiu.beznea@microchip.com>
   3 Date: Thu, 19 Nov 2020 17:43:15 +0200
   4 Subject: [PATCH 109/247] clk: at91: sama7g5: do not allow cpu pll to go higher
   5  than 1GHz
   6
   7 Since CPU PLL feeds both CPU clock and MCK0, MCK0 cannot go higher
   8 than 200MHz and MCK0 maximum prescaller is 5 limit the CPU PLL at
   9 1GHz to avoid MCK0 overclocking while CPU PLL is changed by DVFS.
  10
  11 Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
  12 Link: https://lore.kernel.org/r/1605800597-16720-10-git-send-email-claudiu.beznea@microchip.com
  13 Signed-off-by: Stephen Boyd <sboyd@kernel.org>
  14 ---
  15  drivers/clk/at91/sama7g5.c | 61 +++++++++++++++++++++++++++++---------
  16  1 file changed, 47 insertions(+), 14 deletions(-)
  17
  18 --- a/drivers/clk/at91/sama7g5.c
  19 +++ b/drivers/clk/at91/sama7g5.c
  20 @@ -89,11 +89,40 @@ static const struct clk_pll_layout pll_l
  21         .endiv_shift    = 30,
  22  };
  23
  24 +/*
  25 + * CPU PLL output range.
  26 + * Notice: The upper limit has been setup to 1000000002 due to hardware
  27 + * block which cannot output exactly 1GHz.
  28 + */
  29 +static const struct clk_range cpu_pll_outputs[] = {
  30 +       { .min = 2343750, .max = 1000000002 },
  31 +};
  32 +
  33 +/* PLL output range. */
  34 +static const struct clk_range pll_outputs[] = {
  35 +       { .min = 2343750, .max = 1200000000 },
  36 +};
  37 +
  38 +/* CPU PLL characteristics. */
  39 +static const struct clk_pll_characteristics cpu_pll_characteristics = {
  40 +       .input = { .min = 12000000, .max = 50000000 },
  41 +       .num_output = ARRAY_SIZE(cpu_pll_outputs),
  42 +       .output = cpu_pll_outputs,
  43 +};
  44 +
  45 +/* PLL characteristics. */
  46 +static const struct clk_pll_characteristics pll_characteristics = {
  47 +       .input = { .min = 12000000, .max = 50000000 },
  48 +       .num_output = ARRAY_SIZE(pll_outputs),
  49 +       .output = pll_outputs,
  50 +};
  51 +
  52  /**
  53   * PLL clocks description
  54   * @n:         clock name
  55   * @p:         clock parent
  56   * @l:         clock layout
  57 + * @c:         clock characteristics
  58   * @t:         clock type
  59   * @f:         clock flags
  60   * @eid:       export index in sama7g5->chws[] array
  61 @@ -102,6 +131,7 @@ static const struct {
  62         const char *n;
  63         const char *p;
  64         const struct clk_pll_layout *l;
  65 +       const struct clk_pll_characteristics *c;
  66         unsigned long f;
  67         u8 t;
  68         u8 eid;
  69 @@ -110,6 +140,7 @@ static const struct {
  70                 { .n = "cpupll_fracck",
  71                   .p = "mainck",
  72                   .l = &pll_layout_frac,
  73 +                 .c = &cpu_pll_characteristics,
  74                   .t = PLL_TYPE_FRAC,
  75                    /*
  76                     * This feeds cpupll_divpmcck which feeds CPU. It should
  77 @@ -120,6 +151,7 @@ static const struct {
  78                 { .n = "cpupll_divpmcck",
  79                   .p = "cpupll_fracck",
  80                   .l = &pll_layout_divpmc,
  81 +                 .c = &cpu_pll_characteristics,
  82                   .t = PLL_TYPE_DIV,
  83                    /* This feeds CPU. It should not be disabled. */
  84                   .f = CLK_IS_CRITICAL | CLK_SET_RATE_PARENT,
  85 @@ -130,6 +162,7 @@ static const struct {
  86                 { .n = "syspll_fracck",
  87                   .p = "mainck",
  88                   .l = &pll_layout_frac,
  89 +                 .c = &pll_characteristics,
  90                   .t = PLL_TYPE_FRAC,
  91                    /*
  92                     * This feeds syspll_divpmcck which may feed critial parts
  93 @@ -141,6 +174,7 @@ static const struct {
  94                 { .n = "syspll_divpmcck",
  95                   .p = "syspll_fracck",
  96                   .l = &pll_layout_divpmc,
  97 +                 .c = &pll_characteristics,
  98                   .t = PLL_TYPE_DIV,
  99                    /*
 100                     * This may feed critial parts of the systems like timers.
 101 @@ -154,6 +188,7 @@ static const struct {
 102                 { .n = "ddrpll_fracck",
 103                   .p = "mainck",
 104                   .l = &pll_layout_frac,
 105 +                 .c = &pll_characteristics,
 106                   .t = PLL_TYPE_FRAC,
 107                    /*
 108                     * This feeds ddrpll_divpmcck which feeds DDR. It should not
 109 @@ -164,6 +199,7 @@ static const struct {
 110                 { .n = "ddrpll_divpmcck",
 111                   .p = "ddrpll_fracck",
 112                   .l = &pll_layout_divpmc,
 113 +                 .c = &pll_characteristics,
 114                   .t = PLL_TYPE_DIV,
 115                    /* This feeds DDR. It should not be disabled. */
 116                   .f = CLK_IS_CRITICAL | CLK_SET_RATE_GATE, },
 117 @@ -173,12 +209,14 @@ static const struct {
 118                 { .n = "imgpll_fracck",
 119                   .p = "mainck",
 120                   .l = &pll_layout_frac,
 121 +                 .c = &pll_characteristics,
 122                   .t = PLL_TYPE_FRAC,
 123                   .f = CLK_SET_RATE_GATE, },
 124
 125                 { .n = "imgpll_divpmcck",
 126                   .p = "imgpll_fracck",
 127                   .l = &pll_layout_divpmc,
 128 +                 .c = &pll_characteristics,
 129                   .t = PLL_TYPE_DIV,
 130                   .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 131                        CLK_SET_RATE_PARENT, },
 132 @@ -188,12 +226,14 @@ static const struct {
 133                 { .n = "baudpll_fracck",
 134                   .p = "mainck",
 135                   .l = &pll_layout_frac,
 136 +                 .c = &pll_characteristics,
 137                   .t = PLL_TYPE_FRAC,
 138                   .f = CLK_SET_RATE_GATE, },
 139
 140                 { .n = "baudpll_divpmcck",
 141                   .p = "baudpll_fracck",
 142                   .l = &pll_layout_divpmc,
 143 +                 .c = &pll_characteristics,
 144                   .t = PLL_TYPE_DIV,
 145                   .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 146                        CLK_SET_RATE_PARENT, },
 147 @@ -203,12 +243,14 @@ static const struct {
 148                 { .n = "audiopll_fracck",
 149                   .p = "main_xtal",
 150                   .l = &pll_layout_frac,
 151 +                 .c = &pll_characteristics,
 152                   .t = PLL_TYPE_FRAC,
 153                   .f = CLK_SET_RATE_GATE, },
 154
 155                 { .n = "audiopll_divpmcck",
 156                   .p = "audiopll_fracck",
 157                   .l = &pll_layout_divpmc,
 158 +                 .c = &pll_characteristics,
 159                   .t = PLL_TYPE_DIV,
 160                   .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 161                        CLK_SET_RATE_PARENT,
 162 @@ -217,6 +259,7 @@ static const struct {
 163                 { .n = "audiopll_diviock",
 164                   .p = "audiopll_fracck",
 165                   .l = &pll_layout_divio,
 166 +                 .c = &pll_characteristics,
 167                   .t = PLL_TYPE_DIV,
 168                   .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 169                        CLK_SET_RATE_PARENT,
 170 @@ -227,12 +270,14 @@ static const struct {
 171                 { .n = "ethpll_fracck",
 172                   .p = "main_xtal",
 173                   .l = &pll_layout_frac,
 174 +                 .c = &pll_characteristics,
 175                   .t = PLL_TYPE_FRAC,
 176                   .f = CLK_SET_RATE_GATE, },
 177
 178                 { .n = "ethpll_divpmcck",
 179                   .p = "ethpll_fracck",
 180                   .l = &pll_layout_divpmc,
 181 +                 .c = &pll_characteristics,
 182                   .t = PLL_TYPE_DIV,
 183                   .f = CLK_SET_RATE_GATE | CLK_SET_PARENT_GATE |
 184                        CLK_SET_RATE_PARENT, },
 185 @@ -793,18 +838,6 @@ static const struct {
 186           .pp_chg_id = INT_MIN, },
 187  };
 188
 189 -/* PLL output range. */
 190 -static const struct clk_range pll_outputs[] = {
 191 -       { .min = 2343750, .max = 1200000000 },
 192 -};
 193 -
 194 -/* PLL characteristics. */
 195 -static const struct clk_pll_characteristics pll_characteristics = {
 196 -       .input = { .min = 12000000, .max = 50000000 },
 197 -       .num_output = ARRAY_SIZE(pll_outputs),
 198 -       .output = pll_outputs,
 199 -};
 200 -
 201  /* MCK0 characteristics. */
 202  static const struct clk_master_characteristics mck0_characteristics = {
 203         .output = { .min = 50000000, .max = 200000000 },
 204 @@ -921,7 +954,7 @@ static void __init sama7g5_pmc_setup(str
 205                                 hw = sam9x60_clk_register_frac_pll(regmap,
 206                                         &pmc_pll_lock, sama7g5_plls[i][j].n,
 207                                         sama7g5_plls[i][j].p, parent_hw, i,
 208 -                                       &pll_characteristics,
 209 +                                       sama7g5_plls[i][j].c,
 210                                         sama7g5_plls[i][j].l,
 211                                         sama7g5_plls[i][j].f);
 212                                 break;
 213 @@ -930,7 +963,7 @@ static void __init sama7g5_pmc_setup(str
 214                                 hw = sam9x60_clk_register_div_pll(regmap,
 215                                         &pmc_pll_lock, sama7g5_plls[i][j].n,
 216                                         sama7g5_plls[i][j].p, i,
 217 -                                       &pll_characteristics,
 218 +                                       sama7g5_plls[i][j].c,
 219                                         sama7g5_plls[i][j].l,
 220                                         sama7g5_plls[i][j].f);
 221                                 break;