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[openwrt/staging/wigyori.git] / target / linux / at91 / patches-5.10 / 180-media-atmel-atmel-isc-move-the-formats-list-into-pro.patch
1 From dda51aa2e4524914d25022864466fa9d8713a5e9 Mon Sep 17 00:00:00 2001
2 From: Eugen Hristev <eugen.hristev@microchip.com>
3 Date: Tue, 13 Apr 2021 12:57:22 +0200
4 Subject: [PATCH 180/247] media: atmel: atmel-isc: move the formats list into
5 product specific code
6
7 The list of input and output formats has to be product specific.
8 Move this list into the product specific code.
9 Have pointers to these arrays inside the device struct.
10
11 Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
12 Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
13 Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
14 ---
15 drivers/media/platform/atmel/atmel-isc-base.c | 167 ++----------------
16 drivers/media/platform/atmel/atmel-isc.h | 12 +-
17 .../media/platform/atmel/atmel-sama5d2-isc.c | 136 ++++++++++++++
18 3 files changed, 165 insertions(+), 150 deletions(-)
19
20 --- a/drivers/media/platform/atmel/atmel-isc-base.c
21 +++ b/drivers/media/platform/atmel/atmel-isc-base.c
22 @@ -45,137 +45,6 @@ module_param(sensor_preferred, uint, 064
23 MODULE_PARM_DESC(sensor_preferred,
24 "Sensor is preferred to output the specified format (1-on 0-off), default 1");
25
26 -/* This is a list of the formats that the ISC can *output* */
27 -const struct isc_format controller_formats[] = {
28 - {
29 - .fourcc = V4L2_PIX_FMT_ARGB444,
30 - },
31 - {
32 - .fourcc = V4L2_PIX_FMT_ARGB555,
33 - },
34 - {
35 - .fourcc = V4L2_PIX_FMT_RGB565,
36 - },
37 - {
38 - .fourcc = V4L2_PIX_FMT_ABGR32,
39 - },
40 - {
41 - .fourcc = V4L2_PIX_FMT_XBGR32,
42 - },
43 - {
44 - .fourcc = V4L2_PIX_FMT_YUV420,
45 - },
46 - {
47 - .fourcc = V4L2_PIX_FMT_YUYV,
48 - },
49 - {
50 - .fourcc = V4L2_PIX_FMT_YUV422P,
51 - },
52 - {
53 - .fourcc = V4L2_PIX_FMT_GREY,
54 - },
55 - {
56 - .fourcc = V4L2_PIX_FMT_Y10,
57 - },
58 -};
59 -
60 -/* This is a list of formats that the ISC can receive as *input* */
61 -struct isc_format formats_list[] = {
62 - {
63 - .fourcc = V4L2_PIX_FMT_SBGGR8,
64 - .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
65 - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
66 - .cfa_baycfg = ISC_BAY_CFG_BGBG,
67 - },
68 - {
69 - .fourcc = V4L2_PIX_FMT_SGBRG8,
70 - .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
71 - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
72 - .cfa_baycfg = ISC_BAY_CFG_GBGB,
73 - },
74 - {
75 - .fourcc = V4L2_PIX_FMT_SGRBG8,
76 - .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
77 - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
78 - .cfa_baycfg = ISC_BAY_CFG_GRGR,
79 - },
80 - {
81 - .fourcc = V4L2_PIX_FMT_SRGGB8,
82 - .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
83 - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
84 - .cfa_baycfg = ISC_BAY_CFG_RGRG,
85 - },
86 - {
87 - .fourcc = V4L2_PIX_FMT_SBGGR10,
88 - .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
89 - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
90 - .cfa_baycfg = ISC_BAY_CFG_RGRG,
91 - },
92 - {
93 - .fourcc = V4L2_PIX_FMT_SGBRG10,
94 - .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
95 - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
96 - .cfa_baycfg = ISC_BAY_CFG_GBGB,
97 - },
98 - {
99 - .fourcc = V4L2_PIX_FMT_SGRBG10,
100 - .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
101 - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
102 - .cfa_baycfg = ISC_BAY_CFG_GRGR,
103 - },
104 - {
105 - .fourcc = V4L2_PIX_FMT_SRGGB10,
106 - .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
107 - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
108 - .cfa_baycfg = ISC_BAY_CFG_RGRG,
109 - },
110 - {
111 - .fourcc = V4L2_PIX_FMT_SBGGR12,
112 - .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
113 - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
114 - .cfa_baycfg = ISC_BAY_CFG_BGBG,
115 - },
116 - {
117 - .fourcc = V4L2_PIX_FMT_SGBRG12,
118 - .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
119 - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
120 - .cfa_baycfg = ISC_BAY_CFG_GBGB,
121 - },
122 - {
123 - .fourcc = V4L2_PIX_FMT_SGRBG12,
124 - .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
125 - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
126 - .cfa_baycfg = ISC_BAY_CFG_GRGR,
127 - },
128 - {
129 - .fourcc = V4L2_PIX_FMT_SRGGB12,
130 - .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
131 - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
132 - .cfa_baycfg = ISC_BAY_CFG_RGRG,
133 - },
134 - {
135 - .fourcc = V4L2_PIX_FMT_GREY,
136 - .mbus_code = MEDIA_BUS_FMT_Y8_1X8,
137 - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
138 - },
139 - {
140 - .fourcc = V4L2_PIX_FMT_YUYV,
141 - .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
142 - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
143 - },
144 - {
145 - .fourcc = V4L2_PIX_FMT_RGB565,
146 - .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
147 - .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
148 - },
149 - {
150 - .fourcc = V4L2_PIX_FMT_Y10,
151 - .mbus_code = MEDIA_BUS_FMT_Y10_1X10,
152 - .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
153 - },
154 -
155 -};
156 -
157 #define ISC_IS_FORMAT_RAW(mbus_code) \
158 (((mbus_code) & 0xf000) == 0x3000)
159
160 @@ -919,24 +788,25 @@ static int isc_querycap(struct file *fil
161 static int isc_enum_fmt_vid_cap(struct file *file, void *priv,
162 struct v4l2_fmtdesc *f)
163 {
164 + struct isc_device *isc = video_drvdata(file);
165 u32 index = f->index;
166 u32 i, supported_index;
167
168 - if (index < ARRAY_SIZE(controller_formats)) {
169 - f->pixelformat = controller_formats[index].fourcc;
170 + if (index < isc->controller_formats_size) {
171 + f->pixelformat = isc->controller_formats[index].fourcc;
172 return 0;
173 }
174
175 - index -= ARRAY_SIZE(controller_formats);
176 + index -= isc->controller_formats_size;
177
178 supported_index = 0;
179
180 - for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
181 - if (!ISC_IS_FORMAT_RAW(formats_list[i].mbus_code) ||
182 - !formats_list[i].sd_support)
183 + for (i = 0; i < isc->formats_list_size; i++) {
184 + if (!ISC_IS_FORMAT_RAW(isc->formats_list[i].mbus_code) ||
185 + !isc->formats_list[i].sd_support)
186 continue;
187 if (supported_index == index) {
188 - f->pixelformat = formats_list[i].fourcc;
189 + f->pixelformat = isc->formats_list[i].fourcc;
190 return 0;
191 }
192 supported_index++;
193 @@ -1477,8 +1347,8 @@ static int isc_enum_framesizes(struct fi
194 if (isc->user_formats[i]->fourcc == fsize->pixel_format)
195 ret = 0;
196
197 - for (i = 0; i < ARRAY_SIZE(controller_formats); i++)
198 - if (controller_formats[i].fourcc == fsize->pixel_format)
199 + for (i = 0; i < isc->controller_formats_size; i++)
200 + if (isc->controller_formats[i].fourcc == fsize->pixel_format)
201 ret = 0;
202
203 if (ret)
204 @@ -1514,8 +1384,8 @@ static int isc_enum_frameintervals(struc
205 if (isc->user_formats[i]->fourcc == fival->pixel_format)
206 ret = 0;
207
208 - for (i = 0; i < ARRAY_SIZE(controller_formats); i++)
209 - if (controller_formats[i].fourcc == fival->pixel_format)
210 + for (i = 0; i < isc->controller_formats_size; i++)
211 + if (isc->controller_formats[i].fourcc == fival->pixel_format)
212 ret = 0;
213
214 if (ret)
215 @@ -2126,12 +1996,13 @@ static void isc_async_unbind(struct v4l2
216 v4l2_ctrl_handler_free(&isc->ctrls.handler);
217 }
218
219 -static struct isc_format *find_format_by_code(unsigned int code, int *index)
220 +static struct isc_format *find_format_by_code(struct isc_device *isc,
221 + unsigned int code, int *index)
222 {
223 - struct isc_format *fmt = &formats_list[0];
224 + struct isc_format *fmt = &isc->formats_list[0];
225 unsigned int i;
226
227 - for (i = 0; i < ARRAY_SIZE(formats_list); i++) {
228 + for (i = 0; i < isc->formats_list_size; i++) {
229 if (fmt->mbus_code == code) {
230 *index = i;
231 return fmt;
232 @@ -2148,7 +2019,7 @@ static int isc_formats_init(struct isc_d
233 struct isc_format *fmt;
234 struct v4l2_subdev *subdev = isc->current_subdev->sd;
235 unsigned int num_fmts, i, j;
236 - u32 list_size = ARRAY_SIZE(formats_list);
237 + u32 list_size = isc->formats_list_size;
238 struct v4l2_subdev_mbus_code_enum mbus_code = {
239 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
240 };
241 @@ -2158,7 +2029,7 @@ static int isc_formats_init(struct isc_d
242 NULL, &mbus_code)) {
243 mbus_code.index++;
244
245 - fmt = find_format_by_code(mbus_code.code, &i);
246 + fmt = find_format_by_code(isc, mbus_code.code, &i);
247 if (!fmt) {
248 v4l2_warn(&isc->v4l2_dev, "Mbus code %x not supported\n",
249 mbus_code.code);
250 @@ -2179,7 +2050,7 @@ static int isc_formats_init(struct isc_d
251 if (!isc->user_formats)
252 return -ENOMEM;
253
254 - fmt = &formats_list[0];
255 + fmt = &isc->formats_list[0];
256 for (i = 0, j = 0; i < list_size; i++) {
257 if (fmt->sd_support)
258 isc->user_formats[j++] = fmt;
259 --- a/drivers/media/platform/atmel/atmel-isc.h
260 +++ b/drivers/media/platform/atmel/atmel-isc.h
261 @@ -236,6 +236,12 @@ struct isc_reg_offsets {
262 * specific v4l2 controls.
263 *
264 * @offsets: struct holding the product specific register offsets
265 + * @controller_formats: pointer to the array of possible formats that the
266 + * controller can output
267 + * @formats_list: pointer to the array of possible formats that can
268 + * be used as an input to the controller
269 + * @controller_formats_size: size of controller_formats array
270 + * @formats_list_size: size of formats_list array
271 */
272 struct isc_device {
273 struct regmap *regmap;
274 @@ -317,10 +323,12 @@ struct isc_device {
275 };
276
277 struct isc_reg_offsets offsets;
278 + const struct isc_format *controller_formats;
279 + struct isc_format *formats_list;
280 + u32 controller_formats_size;
281 + u32 formats_list_size;
282 };
283
284 -extern struct isc_format formats_list[];
285 -extern const struct isc_format controller_formats[];
286 extern const struct regmap_config isc_regmap_config;
287 extern const struct v4l2_async_notifier_operations isc_async_ops;
288
289 --- a/drivers/media/platform/atmel/atmel-sama5d2-isc.c
290 +++ b/drivers/media/platform/atmel/atmel-sama5d2-isc.c
291 @@ -54,6 +54,137 @@
292
293 #define ISC_CLK_MAX_DIV 255
294
295 +/* This is a list of the formats that the ISC can *output* */
296 +static const struct isc_format sama5d2_controller_formats[] = {
297 + {
298 + .fourcc = V4L2_PIX_FMT_ARGB444,
299 + },
300 + {
301 + .fourcc = V4L2_PIX_FMT_ARGB555,
302 + },
303 + {
304 + .fourcc = V4L2_PIX_FMT_RGB565,
305 + },
306 + {
307 + .fourcc = V4L2_PIX_FMT_ABGR32,
308 + },
309 + {
310 + .fourcc = V4L2_PIX_FMT_XBGR32,
311 + },
312 + {
313 + .fourcc = V4L2_PIX_FMT_YUV420,
314 + },
315 + {
316 + .fourcc = V4L2_PIX_FMT_YUYV,
317 + },
318 + {
319 + .fourcc = V4L2_PIX_FMT_YUV422P,
320 + },
321 + {
322 + .fourcc = V4L2_PIX_FMT_GREY,
323 + },
324 + {
325 + .fourcc = V4L2_PIX_FMT_Y10,
326 + },
327 +};
328 +
329 +/* This is a list of formats that the ISC can receive as *input* */
330 +static struct isc_format sama5d2_formats_list[] = {
331 + {
332 + .fourcc = V4L2_PIX_FMT_SBGGR8,
333 + .mbus_code = MEDIA_BUS_FMT_SBGGR8_1X8,
334 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
335 + .cfa_baycfg = ISC_BAY_CFG_BGBG,
336 + },
337 + {
338 + .fourcc = V4L2_PIX_FMT_SGBRG8,
339 + .mbus_code = MEDIA_BUS_FMT_SGBRG8_1X8,
340 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
341 + .cfa_baycfg = ISC_BAY_CFG_GBGB,
342 + },
343 + {
344 + .fourcc = V4L2_PIX_FMT_SGRBG8,
345 + .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
346 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
347 + .cfa_baycfg = ISC_BAY_CFG_GRGR,
348 + },
349 + {
350 + .fourcc = V4L2_PIX_FMT_SRGGB8,
351 + .mbus_code = MEDIA_BUS_FMT_SRGGB8_1X8,
352 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
353 + .cfa_baycfg = ISC_BAY_CFG_RGRG,
354 + },
355 + {
356 + .fourcc = V4L2_PIX_FMT_SBGGR10,
357 + .mbus_code = MEDIA_BUS_FMT_SBGGR10_1X10,
358 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
359 + .cfa_baycfg = ISC_BAY_CFG_RGRG,
360 + },
361 + {
362 + .fourcc = V4L2_PIX_FMT_SGBRG10,
363 + .mbus_code = MEDIA_BUS_FMT_SGBRG10_1X10,
364 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
365 + .cfa_baycfg = ISC_BAY_CFG_GBGB,
366 + },
367 + {
368 + .fourcc = V4L2_PIX_FMT_SGRBG10,
369 + .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
370 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
371 + .cfa_baycfg = ISC_BAY_CFG_GRGR,
372 + },
373 + {
374 + .fourcc = V4L2_PIX_FMT_SRGGB10,
375 + .mbus_code = MEDIA_BUS_FMT_SRGGB10_1X10,
376 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
377 + .cfa_baycfg = ISC_BAY_CFG_RGRG,
378 + },
379 + {
380 + .fourcc = V4L2_PIX_FMT_SBGGR12,
381 + .mbus_code = MEDIA_BUS_FMT_SBGGR12_1X12,
382 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
383 + .cfa_baycfg = ISC_BAY_CFG_BGBG,
384 + },
385 + {
386 + .fourcc = V4L2_PIX_FMT_SGBRG12,
387 + .mbus_code = MEDIA_BUS_FMT_SGBRG12_1X12,
388 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
389 + .cfa_baycfg = ISC_BAY_CFG_GBGB,
390 + },
391 + {
392 + .fourcc = V4L2_PIX_FMT_SGRBG12,
393 + .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
394 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
395 + .cfa_baycfg = ISC_BAY_CFG_GRGR,
396 + },
397 + {
398 + .fourcc = V4L2_PIX_FMT_SRGGB12,
399 + .mbus_code = MEDIA_BUS_FMT_SRGGB12_1X12,
400 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TWELVE,
401 + .cfa_baycfg = ISC_BAY_CFG_RGRG,
402 + },
403 + {
404 + .fourcc = V4L2_PIX_FMT_GREY,
405 + .mbus_code = MEDIA_BUS_FMT_Y8_1X8,
406 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
407 + },
408 + {
409 + .fourcc = V4L2_PIX_FMT_YUYV,
410 + .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
411 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
412 + },
413 + {
414 + .fourcc = V4L2_PIX_FMT_RGB565,
415 + .mbus_code = MEDIA_BUS_FMT_RGB565_2X8_LE,
416 + .pfe_cfg0_bps = ISC_PFE_CFG0_BPS_EIGHT,
417 + },
418 + {
419 + .fourcc = V4L2_PIX_FMT_Y10,
420 + .mbus_code = MEDIA_BUS_FMT_Y10_1X10,
421 + .pfe_cfg0_bps = ISC_PFG_CFG0_BPS_TEN,
422 + },
423 +
424 +};
425 +
426 static void isc_sama5d2_config_csc(struct isc_device *isc)
427 {
428 struct regmap *regmap = isc->regmap;
429 @@ -310,6 +441,11 @@ static int atmel_isc_probe(struct platfo
430 isc->offsets.version = ISC_SAMA5D2_VERSION_OFFSET;
431 isc->offsets.his_entry = ISC_SAMA5D2_HIS_ENTRY_OFFSET;
432
433 + isc->controller_formats = sama5d2_controller_formats;
434 + isc->controller_formats_size = ARRAY_SIZE(sama5d2_controller_formats);
435 + isc->formats_list = sama5d2_formats_list;
436 + isc->formats_list_size = ARRAY_SIZE(sama5d2_formats_list);
437 +
438 /* sama5d2-isc - 8 bits per beat */
439 isc->dcfg = ISC_DCFG_YMBSIZE_BEATS8 | ISC_DCFG_CMBSIZE_BEATS8;
440
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